3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
24 * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
28 * cpci750.c - main board support/init for the esd cpci750.
34 #include "../../Marvell/include/memory.h"
35 #include "../../Marvell/include/pci.h"
36 #include "../../Marvell/include/mv_gen_reg.h"
50 #endif /* of CONFIG_PCI */
58 static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
59 {"PCI0DLL_1 "}, /* 30 */
60 {"PCI0DLL_0 "}, /* 29 */
61 {"PCI1DLL_2 "}, /* 28 */
62 {"PCI1DLL_1 "}, /* 27 */
63 {"PCI1DLL_0 "}, /* 26 */
64 {"BbEP2En "}, /* 25 */
65 {"SDRAMRdDataDel"}, /* 24 */
66 {"SDRAMRdDel "}, /* 23 */
67 {"SDRAMSync "}, /* 22 */
68 {"SDRAMPipeSel_1"}, /* 21 */
69 {"SDRAMPipeSel_0"}, /* 20 */
70 {"SDRAMAddDel "}, /* 19 */
71 {"SDRAMClkSel "}, /* 18 */
72 {"Reserved(1!) "}, /* 17 */
74 {"BootCSWidth_1 "}, /* 15 */
75 {"BootCSWidth_0 "}, /* 14 */
76 {"PCI1PadsCal "}, /* 13 */
77 {"PCI0PadsCal "}, /* 12 */
78 {"MultiMVId_1 "}, /* 11 */
79 {"MultiMVId_0 "}, /* 10 */
80 {"MultiGTEn "}, /* 09 */
81 {"Int60xArb "}, /* 08 */
82 {"CPUBusConfig_1"}, /* 07 */
83 {"CPUBusConfig_0"}, /* 06 */
84 {"DefIntSpc "}, /* 05 */
86 {"SROMAdd_1 "}, /* 03 */
87 {"SROMAdd_0 "}, /* 02 */
88 {"DRAMPadCal "}, /* 01 */
89 {"SInitEn "}, /* 00 */
100 {"JTAGCalBy "}, /* 21 */
101 {"GB2Sel "}, /* 20 */
102 {"GB1Sel "}, /* 19 */
103 {"DRAMPLL_MDiv_5"}, /* 18 */
104 {"DRAMPLL_MDiv_4"}, /* 17 */
105 {"DRAMPLL_MDiv_3"}, /* 16 */
106 {"DRAMPLL_MDiv_2"}, /* 15 */
107 {"DRAMPLL_MDiv_1"}, /* 14 */
108 {"DRAMPLL_MDiv_0"}, /* 13 */
109 {"GB0Sel "}, /* 12 */
110 {"DRAMPLLPU "}, /* 11 */
111 {"DRAMPLL_HIKVCO"}, /* 10 */
112 {"DRAMPLLNP "}, /* 09 */
113 {"DRAMPLL_NDiv_7"}, /* 08 */
114 {"DRAMPLL_NDiv_6"}, /* 07 */
115 {"CPUPadCal "}, /* 06 */
116 {"DRAMPLL_NDiv_5"}, /* 05 */
117 {"DRAMPLL_NDiv_4"}, /* 04 */
118 {"DRAMPLL_NDiv_3"}, /* 03 */
119 {"DRAMPLL_NDiv_2"}, /* 02 */
120 {"DRAMPLL_NDiv_1"}, /* 01 */
121 {"DRAMPLL_NDiv_0"}}; /* 00 */
123 extern flash_info_t flash_info[];
125 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
126 extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
128 /* ------------------------------------------------------------------------- */
130 /* this is the current GT register space location */
131 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
133 /* Unfortunately, we cant change it while we are in flash, so we initialize it
134 * to the "final" value. This means that any debug_led calls before
135 * board_early_init_f wont work right (like in cpu_init_f).
136 * See also my_remap_gt_regs below. (NTL)
139 void board_prebootm_init (void);
140 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
141 int display_mem_map (void);
143 /* ------------------------------------------------------------------------- */
146 * This is a version of the GT register space remapping function that
147 * doesn't touch globals (meaning, it's ok to run from flash.)
149 * Unfortunately, this has the side effect that a writable
150 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
153 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
157 /* check and see if it's already moved */
159 /* original ppcboot 1.1.6 source
161 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
162 if ((temp & 0xffff) == new_loc >> 20)
165 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
166 0xffff0000) | (new_loc >> 20);
168 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
170 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
171 original ppcboot 1.1.6 source end */
173 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
174 if ((temp & 0xffff) == new_loc >> 16)
177 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
178 0xffff0000) | (new_loc >> 16);
180 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
182 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
187 static void gt_pci_config (void)
190 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
192 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
193 * config registers by writing ones to the bus and device.
194 * We then update the Virtual register with the correct value for the bus and device.
196 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
197 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
199 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
201 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
202 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
203 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
206 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
207 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
208 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
210 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
211 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
212 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
216 PCI_MASTER_ENABLE (0, SELF);
217 PCI_MASTER_ENABLE (1, SELF);
219 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
220 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
221 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
224 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
225 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
227 /* ronen- add write to pci remap registers for 64460.
228 in 64360 when writing to pci base go and overide remap automaticaly,
229 in 64460 it doesn't */
230 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
231 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
232 GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
234 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
235 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
236 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
238 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
239 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
240 GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
242 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
243 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
244 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
246 /* PCI interface settings */
247 /* Timeout set to retry forever */
248 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
249 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
251 /* ronen - enable only CS0 and Internal reg!! */
252 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
253 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
255 /*ronen update the pci internal registers base address.*/
257 for (stat = 0; stat <= PCI_HOST1; stat++)
258 pciWriteConfigReg (stat,
259 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
260 SELF, CONFIG_SYS_GT_REGS);
266 /* Setup CPU interface paramaters */
267 static void gt_cpu_config (void)
269 cpu_t cpu = get_cpu_type ();
272 /* cpu configuration register */
273 tmp = GTREGREAD (CPU_CONFIGURATION);
275 /* set the SINGLE_CPU bit see MV64360 P.399 */
276 #ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
277 tmp |= CPU_CONF_SINGLE_CPU;
280 tmp &= ~CPU_CONF_AACK_DELAY_2;
282 tmp |= CPU_CONF_DP_VALID;
283 tmp |= CPU_CONF_AP_VALID;
285 tmp |= CPU_CONF_PIPELINE;
287 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
289 /* CPU master control register */
290 tmp = GTREGREAD (CPU_MASTER_CONTROL);
292 tmp |= CPU_MAST_CTL_ARB_EN;
294 if ((cpu == CPU_7400) ||
295 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
297 tmp |= CPU_MAST_CTL_CLEAN_BLK;
298 tmp |= CPU_MAST_CTL_FLUSH_BLK;
301 /* cleanblock must be cleared for CPUs
302 * that do not support this command (603e, 750)
304 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
305 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
307 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
311 * board_early_init_f.
313 * set up gal. device mappings, etc.
315 int board_early_init_f (void)
319 * set up the GT the way the kernel wants it
320 * the call to move the GT register space will obviously
321 * fail if it has already been done, but we're going to assume
322 * that if it's not at the power-on location, it's where we put
323 * it last time. (huber)
326 my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
328 /* No PCI in first release of Port To_do: enable it. */
332 /* mask all external interrupt sources */
333 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
334 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
336 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
337 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
338 /* --------------------- */
339 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
340 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
341 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
342 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
343 /* does not exist in MV6436x
344 GT_REG_WRITE(CPU_INT_0_MASK, 0);
345 GT_REG_WRITE(CPU_INT_1_MASK, 0);
346 GT_REG_WRITE(CPU_INT_2_MASK, 0);
347 GT_REG_WRITE(CPU_INT_3_MASK, 0);
348 --------------------- */
351 /* ----- DEVICE BUS SETTINGS ------ */
358 * 3 - Flash checked 32Bit Intel Strata
359 * boot - BootCS checked 8Bit 29LV040B
364 * the dual 7450 module requires burst access to the boot
365 * device, so the serial rom copies the boot device to the
366 * on-board sram on the eval board, and updates the correct
367 * registers to boot from the sram. (device0)
370 memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
371 memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
372 memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
373 memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
376 /* configure device timing */
377 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
378 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
379 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
380 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
382 #ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
383 /* detect if we are booting from the 32 bit flash */
384 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
385 /* 32 bit boot flash */
386 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
387 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
388 CONFIG_SYS_32BIT_BOOT_PAR);
390 /* 8 bit boot flash */
391 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
392 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
395 /* 8 bit boot flash only */
396 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
403 GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
404 GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
405 GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
406 GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
408 GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
416 /* various things to do after relocation */
431 /* disable the dcache and MMU */
434 if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
435 unsigned int flash_offset;
438 flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
439 for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
440 if (flash_info[3].start[l] != 0) {
441 flash_info[3].start[l] += flash_offset;
444 flash_protect (FLAG_PROTECT_SET,
445 CONFIG_SYS_MONITOR_BASE,
446 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
452 void after_reloc (ulong dest_addr, gd_t * gd)
454 memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
457 /* now, jump to the main ppcboot board init code */
458 board_init_r (gd, dest_addr);
462 /* ------------------------------------------------------------------------- */
465 * Check Board Identity:
467 * right now, assume borad type. (there is just one...after all)
470 int checkboard (void)
474 printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
478 /* utility functions */
479 void debug_led (int led, int mode)
483 int display_mem_map (void)
486 unsigned int base, size, width;
489 printf ("SD (DDR) RAM\n");
490 for (i = 0; i <= BANK3; i++) {
491 base = memoryGetBankBaseAddress (i);
492 size = memoryGetBankSize (i);
494 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
495 i, base, size >> 20);
499 /* CPU's PCI windows */
500 for (i = 0; i <= PCI_HOST1; i++) {
501 printf ("\nCPU's PCI %d windows\n", i);
502 base = pciGetSpaceBase (i, PCI_IO);
503 size = pciGetSpaceSize (i, PCI_IO);
504 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
509 /*ronen currently only first PCI MEM is used 3 */ ;
511 base = pciGetSpaceBase (i, j);
512 size = pciGetSpaceSize (i, j);
513 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
516 #endif /* of CONFIG_PCI */
518 printf ("\nDEVICES\n");
519 for (i = 0; i <= DEVICE3; i++) {
520 base = memoryGetDeviceBaseAddress (i);
521 size = memoryGetDeviceSize (i);
522 width = memoryGetDeviceWidth (i) * 8;
523 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
525 printf ("\t- FLASH\n");
527 printf ("\t- FLASH\n");
529 printf ("\t- FLASH\n");
531 printf ("\t- RTC/REGS/CAN\n");
535 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
536 size = memoryGetDeviceSize (BOOT_DEVICE);
537 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
538 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
539 base, size >> 20, width);
544 * Command loadpci: wait for signal from host and boot image.
546 int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
548 volatile unsigned int *ptr;
553 char str[] = "\\|/-";
562 puts("\nWaiting for image from pci host -");
565 * Wait for host to write the start address
567 while (*ptr == 0xffffffff) {
569 if (!(count % 100)) {
571 putc(0x08); /* backspace */
572 putc(str[count2 % 4]);
575 /* Abort if ctrl-c was pressed */
584 sprintf(addr, "%08x", *ptr);
585 printf("\nBooting Image at addr 0x%s ...\n", addr);
586 setenv("loadaddr", addr);
588 switch (ptr[1] == 0) {
591 * Boot image via bootm
593 local_args[0] = argv[0];
594 local_args[1] = NULL;
595 status = do_bootm (cmdtp, 0, 1, local_args);
599 * Boot image via bootvx
601 local_args[0] = argv[0];
602 local_args[1] = NULL;
603 status = do_bootvx (cmdtp, 0, 1, local_args);
611 loadpci, 1, 1, do_loadpci,
612 "loadpci - Wait for pci-image and boot it\n",
616 /* DRAM check routines copied from gw8260 */
618 #if defined (CONFIG_SYS_DRAM_TEST)
620 /*********************************************************************/
621 /* NAME: move64() - moves a double word (64-bit) */
624 /* this function performs a double word move from the data at */
625 /* the source pointer to the location at the destination pointer. */
628 /* unsigned long long *src - pointer to data to move */
631 /* unsigned long long *dest - pointer to locate to move data */
636 /* RESTRICTIONS/LIMITATIONS: */
637 /* May cloober fr0. */
639 /*********************************************************************/
640 static void move64 (unsigned long long *src, unsigned long long *dest)
642 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
643 "stfd 0, 0(4)" /* *dest = fpr0 */
644 : : : "fr0"); /* Clobbers fr0 */
649 #if defined (CONFIG_SYS_DRAM_TEST_DATA)
651 unsigned long long pattern[] = {
652 0xaaaaaaaaaaaaaaaaLL,
653 0xccccccccccccccccLL,
654 0xf0f0f0f0f0f0f0f0LL,
655 0xff00ff00ff00ff00LL,
656 0xffff0000ffff0000LL,
657 0xffffffff00000000LL,
658 0x00000000ffffffffLL,
659 0x0000ffff0000ffffLL,
660 0x00ff00ff00ff00ffLL,
661 0x0f0f0f0f0f0f0f0fLL,
662 0x3333333333333333LL,
663 0x5555555555555555LL,
666 /*********************************************************************/
667 /* NAME: mem_test_data() - test data lines for shorts and opens */
670 /* Tests data lines for shorts and opens by forcing adjacent data */
671 /* to opposite states. Because the data lines could be routed in */
672 /* an arbitrary manner the must ensure test patterns ensure that */
673 /* every case is tested. By using the following series of binary */
674 /* patterns every combination of adjacent bits is test regardless */
677 /* ...101010101010101010101010 */
678 /* ...110011001100110011001100 */
679 /* ...111100001111000011110000 */
680 /* ...111111110000000011111111 */
682 /* Carrying this out, gives us six hex patterns as follows: */
684 /* 0xaaaaaaaaaaaaaaaa */
685 /* 0xcccccccccccccccc */
686 /* 0xf0f0f0f0f0f0f0f0 */
687 /* 0xff00ff00ff00ff00 */
688 /* 0xffff0000ffff0000 */
689 /* 0xffffffff00000000 */
691 /* The number test patterns will always be given by: */
693 /* log(base 2)(number data bits) = log2 (64) = 6 */
695 /* To test for short and opens to other signals on our boards. we */
697 /* test with the 1's complemnt of the paterns as well. */
700 /* Displays failing test pattern */
703 /* 0 - Passed test */
704 /* 1 - Failed test */
706 /* RESTRICTIONS/LIMITATIONS: */
707 /* Assumes only one one SDRAM bank */
709 /*********************************************************************/
710 int mem_test_data (void)
712 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
713 unsigned long long temp64 = 0;
714 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
718 for (i = 0; i < num_patterns; i++) {
719 move64 (&(pattern[i]), pmem);
720 move64 (pmem, &temp64);
722 /* hi = (temp64>>32) & 0xffffffff; */
723 /* lo = temp64 & 0xffffffff; */
724 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
726 hi = (pattern[i] >> 32) & 0xffffffff;
727 lo = pattern[i] & 0xffffffff;
728 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
730 if (temp64 != pattern[i]) {
731 printf ("\n Data Test Failed, pattern 0x%08x%08x",
739 #endif /* CONFIG_SYS_DRAM_TEST_DATA */
741 #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
742 /*********************************************************************/
743 /* NAME: mem_test_address() - test address lines */
746 /* This function performs a test to verify that each word im */
747 /* memory is uniquly addressable. The test sequence is as follows: */
749 /* 1) write the address of each word to each word. */
750 /* 2) verify that each location equals its address */
753 /* Displays failing test pattern and address */
756 /* 0 - Passed test */
757 /* 1 - Failed test */
759 /* RESTRICTIONS/LIMITATIONS: */
762 /*********************************************************************/
763 int mem_test_address (void)
765 volatile unsigned int *pmem =
766 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
767 const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
770 /* write address to each location */
771 for (i = 0; i < size; i++) {
775 /* verify each loaction */
776 for (i = 0; i < size; i++) {
778 printf ("\n Address Test Failed at 0x%x", i);
784 #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
786 #if defined (CONFIG_SYS_DRAM_TEST_WALK)
787 /*********************************************************************/
788 /* NAME: mem_march() - memory march */
791 /* Marches up through memory. At each location verifies rmask if */
792 /* read = 1. At each location write wmask if write = 1. Displays */
793 /* failing address and pattern. */
796 /* volatile unsigned long long * base - start address of test */
797 /* unsigned int size - number of dwords(64-bit) to test */
798 /* unsigned long long rmask - read verify mask */
799 /* unsigned long long wmask - wrtie verify mask */
800 /* short read - verifies rmask if read = 1 */
801 /* short write - writes wmask if write = 1 */
804 /* Displays failing test pattern and address */
807 /* 0 - Passed test */
808 /* 1 - Failed test */
810 /* RESTRICTIONS/LIMITATIONS: */
813 /*********************************************************************/
814 int mem_march (volatile unsigned long long *base,
816 unsigned long long rmask,
817 unsigned long long wmask, short read, short write)
820 unsigned long long temp = 0;
821 unsigned int hitemp, lotemp, himask, lomask;
823 for (i = 0; i < size; i++) {
825 /* temp = base[i]; */
826 move64 ((unsigned long long *) &(base[i]), &temp);
828 hitemp = (temp >> 32) & 0xffffffff;
829 lotemp = temp & 0xffffffff;
830 himask = (rmask >> 32) & 0xffffffff;
831 lomask = rmask & 0xffffffff;
833 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
838 /* base[i] = wmask; */
839 move64 (&wmask, (unsigned long long *) &(base[i]));
844 #endif /* CONFIG_SYS_DRAM_TEST_WALK */
846 /*********************************************************************/
847 /* NAME: mem_test_walk() - a simple walking ones test */
850 /* Performs a walking ones through entire physical memory. The */
851 /* test uses as series of memory marches, mem_march(), to verify */
852 /* and write the test patterns to memory. The test sequence is as */
854 /* 1) march writing 0000...0001 */
855 /* 2) march verifying 0000...0001 , writing 0000...0010 */
856 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
857 /* the write mask equals 1000...0000 */
858 /* 4) march verifying 1000...0000 */
859 /* The test fails if any of the memory marches return a failure. */
862 /* Displays which pass on the memory test is executing */
865 /* 0 - Passed test */
866 /* 1 - Failed test */
868 /* RESTRICTIONS/LIMITATIONS: */
871 /*********************************************************************/
872 int mem_test_walk (void)
874 unsigned long long mask;
875 volatile unsigned long long *pmem =
876 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
877 const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
883 printf ("Initial Pass");
884 mem_march (pmem, size, 0x0, 0x1, 0, 1);
886 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
889 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
891 for (i = 0; i < 63; i++) {
892 printf ("Pass %2d", i + 2);
893 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
894 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
898 printf ("\b\b\b\b\b\b\b");
901 printf ("Last Pass");
902 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
903 /* printf("mask: 0x%x", mask); */
906 printf ("\b\b\b\b\b\b\b\b\b");
908 printf ("\b\b\b\b\b\b\b\b\b");
913 /*********************************************************************/
914 /* NAME: testdram() - calls any enabled memory tests */
917 /* Runs memory tests if the environment test variables are set to */
921 /* testdramdata - If set to 'y', data test is run. */
922 /* testdramaddress - If set to 'y', address test is run. */
923 /* testdramwalk - If set to 'y', walking ones test is run */
929 /* 0 - Passed test */
930 /* 1 - Failed test */
932 /* RESTRICTIONS/LIMITATIONS: */
935 /*********************************************************************/
943 #ifdef CONFIG_SYS_DRAM_TEST_DATA
944 s = getenv ("testdramdata");
945 rundata = (s && (*s == 'y')) ? 1 : 0;
947 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
948 s = getenv ("testdramaddress");
949 runaddress = (s && (*s == 'y')) ? 1 : 0;
951 #ifdef CONFIG_SYS_DRAM_TEST_WALK
952 s = getenv ("testdramwalk");
953 runwalk = (s && (*s == 'y')) ? 1 : 0;
956 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
957 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
959 #ifdef CONFIG_SYS_DRAM_TEST_DATA
961 printf ("Test DATA ... ");
962 if (mem_test_data () == 1) {
963 printf ("failed \n");
969 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
970 if (runaddress == 1) {
971 printf ("Test ADDRESS ... ");
972 if (mem_test_address () == 1) {
973 printf ("failed \n");
979 #ifdef CONFIG_SYS_DRAM_TEST_WALK
981 printf ("Test WALKING ONEs ... ");
982 if (mem_test_walk () == 1) {
983 printf ("failed \n");
989 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
995 #endif /* CONFIG_SYS_DRAM_TEST */
997 /* ronen - the below functions are used by the bootm function */
998 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
999 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
1000 /* the kernel data areas. */
1001 /* - we diable and invalidate the icache and dcache. */
1002 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
1006 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
1007 if ((temp & 0xffff) == new_loc >> 16)
1010 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
1011 0xffff0000) | (new_loc >> 16);
1013 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
1015 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
1017 (INTERNAL_SPACE_DECODE)))))
1022 void board_prebootm_init ()
1025 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
1026 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
1028 /* Stop GigE Rx DMA engines */
1029 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
1030 /* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
1031 /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
1033 /* Relocate MV64360 internal regs */
1034 my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
1040 int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1042 unsigned int reset_sample_low;
1043 unsigned int reset_sample_high;
1044 unsigned int l, l1, l2;
1046 GT_REG_READ(0x3c4, &reset_sample_low);
1047 GT_REG_READ(0x3d4, &reset_sample_high);
1048 printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
1051 for (l=0; l<63; l++) {
1052 if (show_config_tab[l][0] != 0) {
1053 printf("%14s:%1x ", show_config_tab[l],
1054 ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
1062 reset_sample_low = reset_sample_high;
1070 show_config, 1, 1, do_show_config,
1071 "Show Marvell strapping register",
1072 "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"