3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
24 * extra improvments by Brain Waite
25 * for cpci750 by reinhard.arlt@esd-electronics.com
30 #include "../../Marvell/include/mv_gen_reg.h"
31 #include "../../Marvell/include/core.h"
42 /* Assuming that there is only one master on the bus (us) */
44 static void i2c_init (int speed, int slaveaddr)
46 unsigned int n, m, freq, margin, power;
47 unsigned int actualN = 0, actualM = 0;
48 unsigned int minMargin = 0xffffffff;
49 unsigned int tclk = CFG_TCLK;
50 unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
52 DP (puts ("i2c_init\n"));
54 for (n = 0; n < 8; n++) {
55 for (m = 0; m < 16; m++) {
56 power = 2 << n; /* power = 2^(n+1) */
57 freq = tclk / (10 * (m + 1) * power);
59 margin = i2cFreq - freq;
61 margin = freq - i2cFreq;
62 if (margin < minMargin) {
70 DP (puts ("setup i2c bus\n"));
74 GT_REG_WRITE (I2C_SOFT_RESET, 0);
76 GT_REG_WRITE (I2C_CONTROL, 0);
79 DP (puts ("set baudrate\n"));
81 GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
84 DP (puts ("udelay...\n"));
88 GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
93 static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
95 unsigned int status, data, bits = 7;
99 DP (puts ("i2c_select_device\n"));
101 /* Output slave address */
107 GT_REG_READ (I2C_CONTROL, &control);
108 control |= (0x1 << 2);
109 GT_REG_WRITE (I2C_CONTROL, control);
112 GT_REG_READ (I2C_CONTROL, &control);
113 control |= (0x1 << 5); /* generate the I2C_START_BIT */
114 GT_REG_WRITE (I2C_CONTROL, control);
116 RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
119 GT_REG_READ (I2C_CONTROL, &status);
120 while ((status & 0x08) != 0x08) {
121 GT_REG_READ (I2C_CONTROL, &status);
127 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
128 while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
131 printf ("Failed to set startbit: 0x%02x\n", status);
133 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
137 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
141 DP (puts ("i2c_select_device:write addr byte\n"));
143 /* assert the address */
145 data = (dev_addr << 1);
146 /* set the read bit */
148 GT_REG_WRITE (I2C_DATA, data);
150 RESET_REG_BITS (I2C_CONTROL, BIT3);
153 GT_REG_READ (I2C_CONTROL, &status);
154 while ((status & 0x08) != 0x08) {
155 GT_REG_READ (I2C_CONTROL, &status);
158 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
160 while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
163 printf ("Failed to write address: 0x%02x\n", status);
165 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
168 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
174 printf ("10 bit I2C addressing not yet implemented\n");
181 static uchar i2c_get_data (uchar * return_data, int len)
184 unsigned int data, status;
187 DP (puts ("i2c_get_data\n"));
191 RESET_REG_BITS (I2C_CONTROL, BIT3);
194 /* Get and return the data */
196 GT_REG_READ (I2C_CONTROL, &status);
197 while ((status & 0x08) != 0x08) {
198 GT_REG_READ (I2C_CONTROL, &status);
201 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
203 while ((status & 0xff) != 0x50) {
206 printf ("Failed to get data len status: 0x%02x\n", status);
208 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
212 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
215 GT_REG_READ (I2C_DATA, &data);
217 *return_data = (uchar) data;
221 RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
225 GT_REG_READ (I2C_CONTROL, &status);
226 while ((status & 0x08) != 0x08) {
227 GT_REG_READ (I2C_CONTROL, &status);
230 while ((status & 0xff) != 0x58) {
232 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
235 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
238 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
240 RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
247 static uchar i2c_write_data (unsigned int *data, int len)
252 unsigned int *temp_ptr = data;
254 DP (puts ("i2c_write_data\n"));
258 temp = (unsigned int) (*temp_ptr);
259 GT_REG_WRITE (I2C_DATA, temp);
261 RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
264 GT_REG_READ (I2C_CONTROL, &status);
265 while ((status & 0x08) != 0x08) {
266 GT_REG_READ (I2C_CONTROL, &status);
269 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
271 while ((status & 0xff) != 0x28) {
273 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
277 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
287 static uchar i2c_write_byte (unsigned char *data, int len)
292 unsigned char *temp_ptr = data;
294 DP (puts ("i2c_write_byte\n"));
298 /* Set and assert the data */
300 GT_REG_WRITE (I2C_DATA, temp);
302 RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
306 GT_REG_READ (I2C_CONTROL, &status);
307 while ((status & 0x08) != 0x08) {
308 GT_REG_READ (I2C_CONTROL, &status);
311 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
313 while ((status & 0xff) != 0x28) {
315 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
319 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
329 i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
333 unsigned int table[2];
335 table[1] = (offset ) & 0x0ff; /* low byte */
336 table[0] = (offset >> 8) & 0x0ff; /* high byte */
338 DP (puts ("i2c_set_dev_offset\n"));
340 status = i2c_select_device (dev_addr, 0, ten_bit);
343 22 printf ("Failed to select device setting offset: 0x%02x\n",
348 /* check the address offset length */
350 /* no address offset */
352 else if (alen == 1) {
353 /* 1 byte address offset */
354 status = i2c_write_data (&offset, 1);
357 printf ("Failed to write data: 0x%02x\n", status);
361 } else if (alen == 2) {
362 /* 2 bytes address offset */
363 status = i2c_write_data (table, 2);
366 printf ("Failed to write data: 0x%02x\n", status);
371 /* address offset unknown or not supported */
372 printf ("Address length offset %d is not supported\n", alen);
375 return 0; /* sucessful completion */
379 i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
383 unsigned int i2cFreq = CFG_I2C_SPEED;
385 DP (puts ("i2c_read\n"));
387 i2c_init (i2cFreq, 0); /* set the i2c frequency */
389 status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
392 printf ("Failed to set slave address & offset: 0x%02x\n",
398 status = i2c_select_device (dev_addr, 1, 0);
401 printf ("Failed to select device for data read: 0x%02x\n",
407 status = i2c_get_data (data, len);
410 printf ("Data not read: 0x%02x\n", status);
421 GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
427 i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
431 unsigned int i2cFreq = CFG_I2C_SPEED;
433 DP (puts ("i2c_write\n"));
435 i2c_init (i2cFreq, 0); /* set the i2c frequency */
437 status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
440 printf ("Failed to set slave address & offset: 0x%02x\n",
447 status = i2c_write_byte (data, len); /* write the data */
450 printf ("Data not written: 0x%02x\n", status);
454 /* issue a stop bit */
460 int i2c_probe (uchar chip)
464 unsigned int i2c_status;
467 unsigned int i2cFreq = CFG_I2C_SPEED;
469 DP (puts ("i2c_probe\n"));
471 i2c_init (i2cFreq, 0); /* set the i2c frequency */
473 status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
476 printf ("Failed to set slave address: 0x%02x\n", status);
481 GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
482 printf ("address %#x returned %#x\n", chip, i2c_status);
484 /* issue a stop bit */
486 return 0; /* successful completion */