3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /*************************************************************************
9 * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
11 ************************************************************************/
14 * mpsc.c - driver for console over the MPSC.
20 #include <asm/cache.h>
27 #include "../../Marvell/include/memory.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 /* Define this if you wish to use the MPSC as a register based UART.
32 * This will force the serial port to not use the SDMA engine at all.
35 #undef CONFIG_MPSC_DEBUG_PORT
38 int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
39 char (*mpsc_getchar) (void) = mpsc_getchar_debug;
40 int (*mpsc_test_char) (void) = mpsc_test_char_debug;
43 static volatile unsigned int *rx_desc_base = NULL;
44 static unsigned int rx_desc_index = 0;
45 static volatile unsigned int *tx_desc_base = NULL;
46 static unsigned int tx_desc_index = 0;
48 /* local function declarations */
49 static int galmpsc_connect (int channel, int connect);
50 static int galmpsc_route_rx_clock (int channel, int brg);
51 static int galmpsc_route_tx_clock (int channel, int brg);
52 static int galmpsc_write_config_regs (int mpsc, int mode);
53 static int galmpsc_config_channel_regs (int mpsc);
54 static int galmpsc_set_char_length (int mpsc, int value);
55 static int galmpsc_set_stop_bit_length (int mpsc, int value);
56 static int galmpsc_set_parity (int mpsc, int value);
57 static int galmpsc_enter_hunt (int mpsc);
58 static int galmpsc_set_brkcnt (int mpsc, int value);
59 static int galmpsc_set_tcschar (int mpsc, int value);
60 static int galmpsc_set_snoop (int mpsc, int value);
61 static int galmpsc_shutdown (int mpsc);
63 static int galsdma_set_RFT (int channel);
64 static int galsdma_set_SFM (int channel);
65 static int galsdma_set_rxle (int channel);
66 static int galsdma_set_txle (int channel);
67 static int galsdma_set_burstsize (int channel, unsigned int value);
68 static int galsdma_set_RC (int channel, unsigned int value);
70 static int galbrg_set_CDV (int channel, int value);
71 static int galbrg_enable (int channel);
72 static int galbrg_disable (int channel);
73 static int galbrg_set_clksrc (int channel, int value);
74 static int galbrg_set_CUV (int channel, int value);
76 static void galsdma_enable_rx (void);
77 static int galsdma_set_mem_space (unsigned int memSpace,
78 unsigned int memSpaceTarget,
79 unsigned int memSpaceAttr,
80 unsigned int baseAddress,
84 #define SOFTWARE_CACHE_MANAGEMENT
86 #ifdef SOFTWARE_CACHE_MANAGEMENT
87 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
88 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
89 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
91 #define FLUSH_DCACHE(a,b)
92 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
93 #define INVALIDATE_DCACHE(a,b)
96 #ifdef CONFIG_MPSC_DEBUG_PORT
97 static void mpsc_debug_init (void)
100 volatile unsigned int temp;
102 /* Clear the CFR (CHR4) */
103 /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
104 temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
107 GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
110 /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
111 temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
112 temp |= (BIT12 | BIT15);
113 GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
117 temp = GTREGREAD (GALMPSC_0_INT_MASK);
119 GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
123 char mpsc_getchar_debug (void)
126 volatile unsigned int cause;
128 cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
129 while ((cause & BIT6) == 0) {
130 cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
133 temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
134 (CHANNEL * GALMPSC_REG_GAP));
135 /* By writing 1's to the set bits, the register is cleared */
136 GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
138 GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
139 return (temp >> 16) & 0xff;
142 /* special function for running out of flash. doesn't modify any
143 * global variables [josh] */
144 int mpsc_putchar_early (char ch)
148 GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
149 galmpsc_set_tcschar (mpsc, ch);
150 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
153 #define MAGIC_FACTOR (10*1000000)
155 udelay (MAGIC_FACTOR / gd->baudrate);
159 /* This is used after relocation, see serial.c and mpsc_init2 */
160 static int mpsc_putchar_sdma (char ch)
162 volatile unsigned int *p;
166 /* align the descriptor */
168 memset ((void *) p, 0, 8 * sizeof (unsigned int));
170 /* fill one 64 bit buffer */
171 /* word swap, pad with 0 */
173 p[5] = (unsigned int) ch; /* x */
175 /* CHANGED completely according to GT64260A dox - NTL */
176 p[0] = 0x00010001; /* 0 */
177 p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
179 p[3] = (unsigned int) &p[4]; /* c */
182 p[9] = DESC_FIRST | DESC_LAST;
183 p[10] = (unsigned int) &p[0];
184 p[11] = (unsigned int) &p[12];
187 FLUSH_DCACHE (&p[0], &p[8]);
189 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
190 (unsigned int) &p[0]);
191 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
192 (unsigned int) &p[0]);
194 temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
195 temp |= (TX_DEMAND | TX_STOP);
196 GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
198 INVALIDATE_DCACHE (&p[1], &p[2]);
200 while (p[1] & DESC_OWNER_BIT) {
202 INVALIDATE_DCACHE (&p[1], &p[2]);
207 char mpsc_getchar_sdma (void)
209 static unsigned int done = 0;
211 unsigned int len = 0, idx = 0, temp;
213 volatile unsigned int *p;
217 p = &rx_desc_base[rx_desc_index * 8];
219 INVALIDATE_DCACHE (&p[0], &p[1]);
220 /* Wait for character */
221 while (p[1] & DESC_OWNER_BIT) {
223 INVALIDATE_DCACHE (&p[0], &p[1]);
226 /* Handle error case */
227 if (p[1] & (1 << 15)) {
228 printf ("oops, error: %08x\n", p[1]);
230 temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
231 (CHANNEL * GALMPSC_REG_GAP));
233 GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
234 (CHANNEL * GALMPSC_REG_GAP), temp);
236 /* Can't poll on abort bit, so we just wait. */
239 galsdma_enable_rx ();
242 /* Number of bytes left in this descriptor */
255 INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
261 /* this descriptor has more bytes still
262 * shift down the char we just read, and leave the
263 * buffer in place for the next time around
265 p[idx] = p[idx] >> 8;
266 FLUSH_DCACHE (&p[idx], &p[idx + 1]);
270 /* nothing left in this descriptor.
273 p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
275 FLUSH_DCACHE (&p[0], &p[1]);
276 /* Next descriptor */
277 rx_desc_index = (rx_desc_index + 1) % RX_DESC;
280 } while (len == 0); /* galileo bug.. len might be zero */
286 int mpsc_test_char_debug (void)
288 if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
296 int mpsc_test_char_sdma (void)
298 volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
300 INVALIDATE_DCACHE (&p[1], &p[2]);
302 if (p[1] & DESC_OWNER_BIT)
308 int mpsc_init (int baud)
311 galbrg_set_baudrate (CHANNEL, baud);
312 galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
313 galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
314 galbrg_enable (CHANNEL); /* Enable BRG */
316 /* Set up clock routing */
317 galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
319 galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
320 galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
322 /* reset MPSC state */
323 galmpsc_shutdown (CHANNEL);
326 galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
327 galsdma_set_txle (CHANNEL);
328 galsdma_set_rxle (CHANNEL);
329 galsdma_set_RC (CHANNEL, 0xf);
330 galsdma_set_SFM (CHANNEL);
331 galsdma_set_RFT (CHANNEL);
334 galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
335 galmpsc_config_channel_regs (CHANNEL);
336 galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
337 galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
338 galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
340 #ifdef CONFIG_MPSC_DEBUG_PORT
344 /* COMM_MPSC CONFIG */
345 #ifdef SOFTWARE_CACHE_MANAGEMENT
346 galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
348 galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
355 void mpsc_sdma_init (void)
357 /* Setup SDMA channel0 SDMA_CONFIG_REG*/
358 GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
360 /* Enable MPSC-Window0 for DRAM Bank0 */
361 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
362 MV64360_SDMA_DRAM_CS_0_TARGET,
364 memoryGetBankBaseAddress
365 (CS_0_LOW_DECODE_ADDRESS),
366 memoryGetBankSize (BANK0)) != true)
367 printf ("%s: SDMA_Window0 memory setup failed !!! \n",
371 /* Disable MPSC-Window1 */
372 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
373 MV64360_SDMA_DRAM_CS_0_TARGET,
375 memoryGetBankBaseAddress
376 (CS_1_LOW_DECODE_ADDRESS),
377 memoryGetBankSize (BANK3)) != true)
378 printf ("%s: SDMA_Window1 memory setup failed !!! \n",
382 /* Disable MPSC-Window2 */
383 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
384 MV64360_SDMA_DRAM_CS_0_TARGET,
386 memoryGetBankBaseAddress
387 (CS_2_LOW_DECODE_ADDRESS),
388 memoryGetBankSize (BANK3)) != true)
389 printf ("%s: SDMA_Window2 memory setup failed !!! \n",
393 /* Disable MPSC-Window3 */
394 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
395 MV64360_SDMA_DRAM_CS_0_TARGET,
397 memoryGetBankBaseAddress
398 (CS_3_LOW_DECODE_ADDRESS),
399 memoryGetBankSize (BANK3)) != true)
400 printf ("%s: SDMA_Window3 memory setup failed !!! \n",
403 /* Setup MPSC0 access mode Window0 full access */
404 GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
405 (MV64360_SDMA_WIN_ACCESS_FULL <<
406 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
408 /* Setup MPSC1 access mode Window1 full access */
409 GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
410 (MV64360_SDMA_WIN_ACCESS_FULL <<
411 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
413 /* Setup MPSC internal address space base address */
414 GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
416 /* no high address remap*/
417 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
418 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
420 /* clear interrupt cause register for MPSC (fault register)*/
421 GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
425 void mpsc_init2 (void)
429 #ifndef CONFIG_MPSC_DEBUG_PORT
430 mpsc_putchar = mpsc_putchar_sdma;
431 mpsc_getchar = mpsc_getchar_sdma;
432 mpsc_test_char = mpsc_test_char_sdma;
435 rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
436 sizeof (unsigned int));
438 /* align descriptors */
439 rx_desc_base = (unsigned int *)
440 (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
444 memset ((void *) rx_desc_base, 0,
445 (RX_DESC * 8) * sizeof (unsigned int));
447 for (i = 0; i < RX_DESC; i++) {
448 rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
449 rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
450 rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
451 rx_desc_base[i * 8] = 0x00100000;
453 rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
455 FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
456 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
457 (unsigned int) &rx_desc_base[0]);
460 tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
461 sizeof (unsigned int));
463 /* align descriptors */
464 tx_desc_base = (unsigned int *)
465 (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
469 memset ((void *) tx_desc_base, 0,
470 (TX_DESC * 8) * sizeof (unsigned int));
472 for (i = 0; i < TX_DESC; i++) {
473 tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
474 tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
475 tx_desc_base[i * 8 + 3] =
476 (unsigned int) &tx_desc_base[i * 8 + 4];
477 tx_desc_base[i * 8 + 2] =
478 (unsigned int) &tx_desc_base[(i + 1) * 8];
479 tx_desc_base[i * 8 + 1] =
480 DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
482 /* set sbytecnt and shadow byte cnt to 1 */
483 tx_desc_base[i * 8] = 0x00010001;
485 tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
487 FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
491 galsdma_enable_rx ();
496 int galbrg_set_baudrate (int channel, int rate)
500 galbrg_disable (channel); /*ok */
504 clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
506 clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
509 galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
511 galbrg_enable (channel);
518 /* ------------------------------------------------------------------ */
520 /* Below are all the private functions that no one else needs */
522 static int galbrg_set_CDV (int channel, int value)
526 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
528 temp |= (value & 0x0000FFFF);
529 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
534 static int galbrg_enable (int channel)
538 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
540 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
545 static int galbrg_disable (int channel)
549 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
551 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
556 static int galbrg_set_clksrc (int channel, int value)
560 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
561 temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
562 temp |= (value << 18);
563 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
567 static int galbrg_set_CUV (int channel, int value)
569 /* set CountUpValue */
570 GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
576 static int galbrg_reset (int channel)
580 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
582 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
588 static int galsdma_set_RFT (int channel)
592 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
594 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
600 static int galsdma_set_SFM (int channel)
604 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
606 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
612 static int galsdma_set_rxle (int channel)
616 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
618 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
624 static int galsdma_set_txle (int channel)
628 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
630 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
636 static int galsdma_set_RC (int channel, unsigned int value)
640 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
642 temp |= (value << 2);
643 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
649 static int galsdma_set_burstsize (int channel, unsigned int value)
653 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
657 GT_REG_WRITE (GALSDMA_0_CONF_REG +
658 (channel * GALSDMA_REG_DIFF),
659 (temp | (0x3 << 12)));
663 GT_REG_WRITE (GALSDMA_0_CONF_REG +
664 (channel * GALSDMA_REG_DIFF),
665 (temp | (0x2 << 12)));
669 GT_REG_WRITE (GALSDMA_0_CONF_REG +
670 (channel * GALSDMA_REG_DIFF),
671 (temp | (0x1 << 12)));
675 GT_REG_WRITE (GALSDMA_0_CONF_REG +
676 (channel * GALSDMA_REG_DIFF),
677 (temp | (0x0 << 12)));
688 static int galmpsc_connect (int channel, int connect)
692 temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
694 if ((channel == 0) && connect)
696 else if ((channel == 1) && connect)
697 temp &= ~(0x00000007 << 6);
698 else if ((channel == 0) && !connect)
701 temp |= (0x00000007 << 6);
703 /* Just in case... */
706 GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
711 static int galmpsc_route_rx_clock (int channel, int brg)
715 temp = GTREGREAD (GALMPSC_RxC_ROUTE);
725 GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
730 static int galmpsc_route_tx_clock (int channel, int brg)
734 temp = GTREGREAD (GALMPSC_TxC_ROUTE);
744 GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
749 static int galmpsc_write_config_regs (int mpsc, int mode)
751 if (mode == GALMPSC_UART) {
752 /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
753 GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
756 /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
757 GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
761 /* 0000 0010 0000 0000 */
764 /* 0000 0011 1111 1000 */
771 static int galmpsc_config_channel_regs (int mpsc)
773 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
774 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
775 GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
776 GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
777 GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
778 GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
779 GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
780 GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
781 GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
782 GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
784 galmpsc_set_brkcnt (mpsc, 0x3);
785 galmpsc_set_tcschar (mpsc, 0xab);
790 static int galmpsc_set_brkcnt (int mpsc, int value)
794 temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
796 temp |= (value << 16);
797 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
802 static int galmpsc_set_tcschar (int mpsc, int value)
806 temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
809 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
814 static int galmpsc_set_char_length (int mpsc, int value)
818 temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
820 temp |= (value << 12);
821 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
826 static int galmpsc_set_stop_bit_length (int mpsc, int value)
830 temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
832 temp |= (value << 14);
833 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
838 static int galmpsc_set_parity (int mpsc, int value)
842 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
845 temp |= ((value << 18) | (value << 2));
846 temp |= ((value << 17) | (value << 1));
851 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
856 static int galmpsc_enter_hunt (int mpsc)
860 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
862 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
864 while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
872 static int galmpsc_shutdown (int mpsc)
876 /* cause RX abort (clears RX) */
877 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
878 temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
879 temp &= ~MPSC_ENTER_HUNT;
880 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
882 GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
883 GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
885 /* shut down the MPSC */
886 GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
887 GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
888 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
892 /* shut down the sdma engines. */
893 /* reset config to default */
894 GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
898 /* clear the SDMA current and first TX and RX pointers */
899 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
900 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
901 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
908 static void galsdma_enable_rx (void)
912 /* Enable RX processing */
913 temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
915 GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
917 galmpsc_enter_hunt (CHANNEL);
920 static int galmpsc_set_snoop (int mpsc, int value)
923 mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
924 MPSC_0_ADDRESS_CONTROL_LOW;
925 int temp = GTREGREAD (reg);
928 temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
930 temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
931 GT_REG_WRITE (reg, temp);
935 /*******************************************************************************
936 * galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
939 * the MV64360 SDMA has its own address decoding map that is de-coupled
940 * from the CPU interface address decoding windows. The SDMA channels
941 * share four address windows. Each region can be individually configured
942 * by this function by associating it to a target interface and setting
943 * base and size values.
946 * The size must be in 64Kbyte granularity.
947 * The base address must be aligned to the size.
948 * The size must be a series of 1s followed by a series of zeros
954 * true for success, false otherwise.
956 *******************************************************************************/
958 static int galsdma_set_mem_space (unsigned int memSpace,
959 unsigned int memSpaceTarget,
960 unsigned int memSpaceAttr,
961 unsigned int baseAddress, unsigned int size)
966 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
971 /* The base address must be aligned to the size. */
972 if (baseAddress % size != 0) {
975 if (size < 0x10000) {
979 /* Align size and base to 64K */
980 baseAddress &= 0xffff0000;
984 /* Checking that the size is a sequence of '1' followed by a
985 sequence of '0' starting from LSB to MSB. */
986 while ((temp > 0) && (temp & 0x1)) {
991 GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
992 (baseAddress | memSpaceTarget | memSpaceAttr));
993 GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
994 (size - 1) & 0xffff0000);
995 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
998 /* An invalid size was specified */