3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * SPDX-License-Identifier: GPL-2.0+
12 * mv_eth.c - header file for the polled mode GT ethernet driver
20 /* enable Debug outputs */
31 #undef MV64360_CHECKSUM_OFFLOAD
32 /*************************************************************************
33 **************************************************************************
34 **************************************************************************
35 * The first part is the high level driver of the gigE ethernet ports. *
36 **************************************************************************
37 **************************************************************************
38 *************************************************************************/
40 /* Definition for configuring driver */
41 /* #define UPDATE_STATS_BY_SOFTWARE */
42 #undef MV64360_RX_QUEUE_FILL_ON_TASK
46 #define MAGIC_ETH_RUNNING 8031971
47 #define MV64360_INTERNAL_SRAM_SIZE _256K
48 #define EXTRA_BYTES 32
49 #define WRAP ETH_HLEN + 2 + 4 + 16
50 #define BUFFER_MTU dev->mtu + WRAP
51 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
52 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
53 #ifdef MV64360_RX_FILL_ON_TASK
54 #define INT_CAUSE_MASK_ALL 0x00000000
55 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
56 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
59 /* Read/Write to/from MV64360 internal registers */
60 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
61 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
62 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
63 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
65 /* Static function declarations */
66 static int mv64360_eth_real_open (struct eth_device *eth);
67 static int mv64360_eth_real_stop (struct eth_device *eth);
68 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
70 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
71 static void mv64360_eth_update_stat (struct eth_device *dev);
72 bool db64360_eth_start (struct eth_device *eth);
73 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
74 unsigned int mib_offset);
75 int mv64360_eth_receive (struct eth_device *dev);
77 int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
79 #ifndef UPDATE_STATS_BY_SOFTWARE
80 static void mv64360_eth_print_stat (struct eth_device *dev);
83 extern unsigned int INTERNAL_REG_BASE_ADDR;
85 /*************************************************
86 *Helper functions - used inside the driver only *
87 *************************************************/
89 void print_globals (struct eth_device *dev)
91 printf ("Ethernet PRINT_Globals-Debug function\n");
92 printf ("Base Address for ETH_PORT_INFO: %08x\n",
93 (unsigned int) dev->priv);
94 printf ("Base Address for mv64360_eth_priv: %08x\n",
95 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
98 printf ("GT Internal Base Address: %08x\n",
99 INTERNAL_REG_BASE_ADDR);
100 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
101 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
102 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
103 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
105 (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
106 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
107 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
109 (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
113 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
115 unsigned long my_le32_to_cpu (unsigned long x)
117 return (((x & 0x000000ffU) << 24) |
118 ((x & 0x0000ff00U) << 8) |
119 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
123 /**********************************************************************
124 * mv64360_eth_print_phy_status
126 * Prints gigabit ethenret phy status
128 * Input : pointer to ethernet interface network device structure
130 **********************************************************************/
132 static void mv64360_eth_print_phy_status (struct eth_device *dev)
134 struct mv64360_eth_priv *port_private;
135 unsigned int port_num;
136 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
137 unsigned int port_status, phy_reg_data;
140 (struct mv64360_eth_priv *) ethernet_private->port_private;
141 port_num = port_private->port_num;
143 /* Check Link status on phy */
144 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
145 if (!(phy_reg_data & 0x20)) {
146 printf ("Ethernet port changed link status to DOWN\n");
149 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
150 printf ("Ethernet status port %d: Link up", port_num);
152 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
153 if (port_status & BIT4)
154 printf (", Speed 1 Gbps");
157 (port_status & BIT5) ? "Speed 100 Mbps" :
163 /**********************************************************************
164 * u-boot entry functions for mv64360_eth
166 **********************************************************************/
167 int db64360_eth_probe (struct eth_device *dev)
169 return ((int) db64360_eth_start (dev));
172 int db64360_eth_poll (struct eth_device *dev)
174 return mv64360_eth_receive (dev);
177 int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
179 mv64360_eth_xmit (dev, packet, length);
183 void db64360_eth_disable (struct eth_device *dev)
185 mv64360_eth_stop (dev);
189 void mv6436x_eth_initialize (bd_t * bis)
191 struct eth_device *dev;
192 ETH_PORT_INFO *ethernet_private;
193 struct mv64360_eth_priv *port_private;
195 char *s, *e, buf[64];
197 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
198 dev = calloc (sizeof (*dev), 1);
200 printf ("%s: mv_enet%d allocation failure, %s\n",
201 __FUNCTION__, devnum, "eth_device structure");
205 /* must be less than sizeof(dev->name) */
206 sprintf (dev->name, "mv_enet%d", devnum);
209 printf ("Initializing %s\n", dev->name);
212 /* Extract the MAC address from the environment */
226 default: /* this should never happen */
227 printf ("%s: Invalid device number %d\n",
228 __FUNCTION__, devnum);
232 temp = getenv_f(s, buf, sizeof (buf));
233 s = (temp > 0) ? buf : NULL;
236 printf ("Setting MAC %d to %s\n", devnum, s);
238 for (x = 0; x < 6; ++x) {
239 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
241 s = (*e) ? e + 1 : e;
243 /* ronen - set the MAC addr in the HW */
244 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
246 dev->init = (void *) db64360_eth_probe;
247 dev->halt = (void *) ethernet_phy_reset;
248 dev->send = (void *) db64360_eth_transmit;
249 dev->recv = (void *) db64360_eth_poll;
252 calloc (sizeof (*ethernet_private), 1);
253 dev->priv = (void *) ethernet_private;
254 if (!ethernet_private) {
255 printf ("%s: %s allocation failure, %s\n",
256 __FUNCTION__, dev->name,
257 "Private Device Structure");
261 /* start with an zeroed ETH_PORT_INFO */
262 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
263 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
265 /* set pointer to memory for stats data structure etc... */
267 calloc (sizeof (*ethernet_private), 1);
268 ethernet_private->port_private = (void *)port_private;
270 printf ("%s: %s allocation failure, %s\n",
271 __FUNCTION__, dev->name,
272 "Port Private Device Structure");
274 free (ethernet_private);
279 port_private->stats =
280 calloc (sizeof (struct net_device_stats), 1);
281 if (!port_private->stats) {
282 printf ("%s: %s allocation failure, %s\n",
283 __FUNCTION__, dev->name,
284 "Net stat Structure");
287 free (ethernet_private);
291 memset (ethernet_private->port_private, 0,
292 sizeof (struct mv64360_eth_priv));
295 ethernet_private->port_num = ETH_0;
298 ethernet_private->port_num = ETH_1;
301 ethernet_private->port_num = ETH_2;
304 printf ("Invalid device number %d\n", devnum);
308 port_private->port_num = devnum;
310 * Read MIB counter on the GT in order to reset them,
311 * then zero all the stats fields in memory
313 mv64360_eth_update_stat (dev);
314 memset (port_private->stats, 0,
315 sizeof (struct net_device_stats));
316 /* Extract the MAC address from the environment */
330 default: /* this should never happen */
331 printf ("%s: Invalid device number %d\n",
332 __FUNCTION__, devnum);
336 temp = getenv_f(s, buf, sizeof (buf));
337 s = (temp > 0) ? buf : NULL;
340 printf ("Setting MAC %d to %s\n", devnum, s);
342 for (x = 0; x < 6; ++x) {
343 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
345 s = (*e) ? e + 1 : e;
348 DP (printf ("Allocating descriptor and buffer rings\n"));
350 ethernet_private->p_rx_desc_area_base[0] =
351 (ETH_RX_DESC *) memalign (16,
352 RX_DESC_ALIGNED_SIZE *
353 MV64360_RX_QUEUE_SIZE + 1);
354 ethernet_private->p_tx_desc_area_base[0] =
355 (ETH_TX_DESC *) memalign (16,
356 TX_DESC_ALIGNED_SIZE *
357 MV64360_TX_QUEUE_SIZE + 1);
359 ethernet_private->p_rx_buffer_base[0] =
360 (char *) memalign (16,
361 MV64360_RX_QUEUE_SIZE *
362 MV64360_TX_BUFFER_SIZE + 1);
363 ethernet_private->p_tx_buffer_base[0] =
364 (char *) memalign (16,
365 MV64360_RX_QUEUE_SIZE *
366 MV64360_TX_BUFFER_SIZE + 1);
369 /* DEBUG OUTPUT prints adresses of globals */
375 DP (printf ("%s: exit\n", __FUNCTION__));
379 /**********************************************************************
382 * This function is called when openning the network device. The function
383 * should initialize all the hardware, initialize cyclic Rx/Tx
384 * descriptors chain and buffers and allocate an IRQ to the network
387 * Input : a pointer to the network device structure
388 * / / ronen - changed the output to match net/eth.c needs
389 * Output : nonzero of success , zero if fails.
391 **********************************************************************/
393 int mv64360_eth_open (struct eth_device *dev)
395 return (mv64360_eth_real_open (dev));
398 /* Helper function for mv64360_eth_open */
399 static int mv64360_eth_real_open (struct eth_device *dev)
403 ETH_PORT_INFO *ethernet_private;
404 struct mv64360_eth_priv *port_private;
405 unsigned int port_num;
408 ethernet_private = (ETH_PORT_INFO *) dev->priv;
409 /* ronen - when we update the MAC env params we only update dev->enetaddr
410 see ./net/eth.c eth_set_enetaddr() */
411 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
414 (struct mv64360_eth_priv *) ethernet_private->port_private;
415 port_num = port_private->port_num;
418 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
421 /* Clear the ethernet port interrupts */
422 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
423 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
425 /* Unmask RX buffer and TX end interrupt */
426 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
427 INT_CAUSE_UNMASK_ALL);
429 /* Unmask phy and link status changes interrupts */
430 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
431 INT_CAUSE_UNMASK_ALL_EXT);
433 /* Set phy address of the port */
434 ethernet_private->port_phy_addr = 0x8 + port_num;
436 /* Activate the DMA channels etc */
437 eth_port_init (ethernet_private);
440 /* "Allocate" setup TX rings */
442 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
445 port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
446 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
447 ethernet_private->tx_desc_area_size[queue] = size;
449 /* first clear desc area completely */
450 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
451 0, ethernet_private->tx_desc_area_size[queue]);
453 /* initialize tx desc ring with low level driver */
454 if (ether_init_tx_desc_ring
455 (ethernet_private, ETH_Q0,
456 port_private->tx_ring_size[queue],
457 MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
458 (unsigned int) ethernet_private->
459 p_tx_desc_area_base[queue],
460 (unsigned int) ethernet_private->
461 p_tx_buffer_base[queue]) == false)
462 printf ("### Error initializing TX Ring\n");
465 /* "Allocate" setup RX rings */
466 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
469 /* Meantime RX Ring are fixed - but must be configurable by user */
470 port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
471 size = (port_private->rx_ring_size[queue] *
472 RX_DESC_ALIGNED_SIZE);
473 ethernet_private->rx_desc_area_size[queue] = size;
475 /* first clear desc area completely */
476 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
477 0, ethernet_private->rx_desc_area_size[queue]);
478 if ((ether_init_rx_desc_ring
479 (ethernet_private, ETH_Q0,
480 port_private->rx_ring_size[queue],
481 MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
482 (unsigned int) ethernet_private->
483 p_rx_desc_area_base[queue],
484 (unsigned int) ethernet_private->
485 p_rx_buffer_base[queue])) == false)
486 printf ("### Error initializing RX Ring\n");
489 eth_port_start (ethernet_private);
491 /* Set maximum receive buffer to 9700 bytes */
492 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
495 (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
499 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
500 * disable the leaky bucket mechanism .
503 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
504 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
506 /* Check Link status on phy */
507 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
508 if (!(phy_reg_data & 0x20)) {
510 if ((ethernet_phy_reset (port_num)) != true) {
511 printf ("$$ Warnning: No link on port %d \n",
515 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
516 if (!(phy_reg_data & 0x20)) {
517 printf ("### Error: Phy is not active\n");
522 mv64360_eth_print_phy_status (dev);
524 port_private->eth_running = MAGIC_ETH_RUNNING;
529 static int mv64360_eth_free_tx_rings (struct eth_device *dev)
532 ETH_PORT_INFO *ethernet_private;
533 struct mv64360_eth_priv *port_private;
534 unsigned int port_num;
535 volatile ETH_TX_DESC *p_tx_curr_desc;
537 ethernet_private = (ETH_PORT_INFO *) dev->priv;
539 (struct mv64360_eth_priv *) ethernet_private->port_private;
540 port_num = port_private->port_num;
543 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
547 DP (printf ("Clearing previously allocated TX queues... "));
548 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
549 /* Free on TX rings */
550 for (p_tx_curr_desc =
551 ethernet_private->p_tx_desc_area_base[queue];
552 ((unsigned int) p_tx_curr_desc <= (unsigned int)
553 ethernet_private->p_tx_desc_area_base[queue] +
554 ethernet_private->tx_desc_area_size[queue]);
556 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
557 TX_DESC_ALIGNED_SIZE)) {
558 /* this is inside for loop */
559 if (p_tx_curr_desc->return_info != 0) {
560 p_tx_curr_desc->return_info = 0;
561 DP (printf ("freed\n"));
564 DP (printf ("Done\n"));
569 static int mv64360_eth_free_rx_rings (struct eth_device *dev)
572 ETH_PORT_INFO *ethernet_private;
573 struct mv64360_eth_priv *port_private;
574 unsigned int port_num;
575 volatile ETH_RX_DESC *p_rx_curr_desc;
577 ethernet_private = (ETH_PORT_INFO *) dev->priv;
579 (struct mv64360_eth_priv *) ethernet_private->port_private;
580 port_num = port_private->port_num;
584 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
588 DP (printf ("Clearing previously allocated RX queues... "));
589 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
590 /* Free preallocated skb's on RX rings */
591 for (p_rx_curr_desc =
592 ethernet_private->p_rx_desc_area_base[queue];
593 (((unsigned int) p_rx_curr_desc <
594 ((unsigned int) ethernet_private->
595 p_rx_desc_area_base[queue] +
596 ethernet_private->rx_desc_area_size[queue])));
598 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
599 RX_DESC_ALIGNED_SIZE)) {
600 if (p_rx_curr_desc->return_info != 0) {
601 p_rx_curr_desc->return_info = 0;
602 DP (printf ("freed\n"));
605 DP (printf ("Done\n"));
610 /**********************************************************************
613 * This function is used when closing the network device.
614 * It updates the hardware,
615 * release all memory that holds buffers and descriptors and release the IRQ.
616 * Input : a pointer to the device structure
617 * Output : zero if success , nonzero if fails
618 *********************************************************************/
620 int mv64360_eth_stop (struct eth_device *dev)
622 /* Disable all gigE address decoder */
623 MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
624 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
625 mv64360_eth_real_stop (dev);
630 /* Helper function for mv64360_eth_stop */
632 static int mv64360_eth_real_stop (struct eth_device *dev)
634 ETH_PORT_INFO *ethernet_private;
635 struct mv64360_eth_priv *port_private;
636 unsigned int port_num;
638 ethernet_private = (ETH_PORT_INFO *) dev->priv;
640 (struct mv64360_eth_priv *) ethernet_private->port_private;
641 port_num = port_private->port_num;
644 mv64360_eth_free_tx_rings (dev);
645 mv64360_eth_free_rx_rings (dev);
647 eth_port_reset (ethernet_private->port_num);
648 /* Disable ethernet port interrupts */
649 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
650 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
651 /* Mask RX buffer and TX end interrupt */
652 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
653 /* Mask phy and link status changes interrupts */
654 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
655 MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
657 /* Print Network statistics */
658 #ifndef UPDATE_STATS_BY_SOFTWARE
660 * Print statistics (only if ethernet is running),
661 * then zero all the stats fields in memory
663 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
664 port_private->eth_running = 0;
665 mv64360_eth_print_stat (dev);
667 memset (port_private->stats, 0, sizeof (struct net_device_stats));
669 DP (printf ("\nEthernet stopped ... \n"));
674 /**********************************************************************
675 * mv64360_eth_start_xmit
677 * This function is queues a packet in the Tx descriptor for
680 * Input : skb - a pointer to socket buffer
681 * dev - a pointer to the required port
683 * Output : zero upon success
684 **********************************************************************/
686 int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
689 ETH_PORT_INFO *ethernet_private;
690 struct mv64360_eth_priv *port_private;
692 ETH_FUNC_RET_STATUS status;
693 struct net_device_stats *stats;
694 ETH_FUNC_RET_STATUS release_result;
696 ethernet_private = (ETH_PORT_INFO *) dev->priv;
698 (struct mv64360_eth_priv *) ethernet_private->port_private;
700 stats = port_private->stats;
702 /* Update packet info data structure */
703 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
704 pkt_info.byte_cnt = dataSize;
705 pkt_info.buf_ptr = (unsigned int) dataPtr;
706 pkt_info.return_info = 0;
708 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
709 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
710 printf ("Error on transmitting packet ..");
711 if (status == ETH_QUEUE_FULL)
712 printf ("ETH Queue is full. \n");
713 if (status == ETH_QUEUE_LAST_RESOURCE)
714 printf ("ETH Queue: using last available resource. \n");
718 /* Update statistics and start of transmittion time */
719 stats->tx_bytes += dataSize;
722 /* Check if packet(s) is(are) transmitted correctly (release everything) */
725 eth_tx_return_desc (ethernet_private, ETH_Q0,
727 switch (release_result) {
729 DP (printf ("descriptor released\n"));
730 if (pkt_info.cmd_sts & BIT0) {
731 printf ("Error in TX\n");
737 DP (printf ("transmission still in process\n"));
741 printf ("routine can not access Tx desc ring\n");
745 DP (printf ("the routine has nothing to release\n"));
747 default: /* should not happen */
750 } while (release_result == ETH_OK);
753 return 0; /* success */
755 return 1; /* Failed - higher layers will free the skb */
758 /**********************************************************************
759 * mv64360_eth_receive
761 * This function is forward packets that are received from the port's
762 * queues toward kernel core or FastRoute them to another interface.
764 * Input : dev - a pointer to the required interface
765 * max - maximum number to receive (0 means unlimted)
767 * Output : number of served packets
768 **********************************************************************/
770 int mv64360_eth_receive (struct eth_device *dev)
772 ETH_PORT_INFO *ethernet_private;
773 struct mv64360_eth_priv *port_private;
775 struct net_device_stats *stats;
778 ethernet_private = (ETH_PORT_INFO *) dev->priv;
780 (struct mv64360_eth_priv *) ethernet_private->port_private;
781 stats = port_private->stats;
783 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
787 if (pkt_info.byte_cnt != 0) {
788 printf ("%s: Received %d byte Packet @ 0x%x\n",
789 __FUNCTION__, pkt_info.byte_cnt,
793 /* Update statistics. Note byte count includes 4 byte CRC count */
795 stats->rx_bytes += pkt_info.byte_cnt;
798 * In case received a packet without first / last bits on OR the error
799 * summary bit is on, the packets needs to be dropeed.
802 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
803 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
804 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
807 printf ("Received packet spread on multiple descriptors\n");
809 /* Is this caused by an error ? */
810 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
814 /* free these descriptors again without forwarding them to the higher layers */
815 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
816 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
818 if (eth_rx_return_buff
819 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
820 printf ("Error while returning the RX Desc to Ring\n");
822 DP (printf ("RX Desc returned to Ring\n"));
824 /* /free these descriptors again */
827 /* !!! call higher layer processing */
829 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
831 /* let the upper layer handle the packet */
832 NetReceive ((uchar *) pkt_info.buf_ptr,
833 (int) pkt_info.byte_cnt);
835 /* **************************************************************** */
836 /* free descriptor */
837 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
838 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
840 ("RX: pkt_info.buf_ptr = %x\n",
842 if (eth_rx_return_buff
843 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
844 printf ("Error while returning the RX Desc to Ring\n");
846 DP (printf ("RX Desc returned to Ring\n"));
849 /* **************************************************************** */
853 mv64360_eth_get_stats (dev); /* update statistics */
857 /**********************************************************************
858 * mv64360_eth_get_stats
860 * Returns a pointer to the interface statistics.
862 * Input : dev - a pointer to the required interface
864 * Output : a pointer to the interface's statistics
865 **********************************************************************/
867 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
869 ETH_PORT_INFO *ethernet_private;
870 struct mv64360_eth_priv *port_private;
872 ethernet_private = (ETH_PORT_INFO *) dev->priv;
874 (struct mv64360_eth_priv *) ethernet_private->port_private;
876 mv64360_eth_update_stat (dev);
878 return port_private->stats;
882 /**********************************************************************
883 * mv64360_eth_update_stat
885 * Update the statistics structure in the private data structure
887 * Input : pointer to ethernet interface network device structure
889 **********************************************************************/
891 static void mv64360_eth_update_stat (struct eth_device *dev)
893 ETH_PORT_INFO *ethernet_private;
894 struct mv64360_eth_priv *port_private;
895 struct net_device_stats *stats;
897 ethernet_private = (ETH_PORT_INFO *) dev->priv;
899 (struct mv64360_eth_priv *) ethernet_private->port_private;
900 stats = port_private->stats;
902 /* These are false updates */
903 stats->rx_packets += (unsigned long)
904 eth_read_mib_counter (ethernet_private->port_num,
905 ETH_MIB_GOOD_FRAMES_RECEIVED);
906 stats->tx_packets += (unsigned long)
907 eth_read_mib_counter (ethernet_private->port_num,
908 ETH_MIB_GOOD_FRAMES_SENT);
909 stats->rx_bytes += (unsigned long)
910 eth_read_mib_counter (ethernet_private->port_num,
911 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
913 * Ideally this should be as follows -
915 * stats->rx_bytes += stats->rx_bytes +
916 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
917 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
919 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
920 * is just a dummy read for proper work of the GigE port
922 (void)eth_read_mib_counter (ethernet_private->port_num,
923 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
924 stats->tx_bytes += (unsigned long)
925 eth_read_mib_counter (ethernet_private->port_num,
926 ETH_MIB_GOOD_OCTETS_SENT_LOW);
927 (void)eth_read_mib_counter (ethernet_private->port_num,
928 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
929 stats->rx_errors += (unsigned long)
930 eth_read_mib_counter (ethernet_private->port_num,
931 ETH_MIB_MAC_RECEIVE_ERROR);
933 /* Rx dropped is for received packet with CRC error */
935 (unsigned long) eth_read_mib_counter (ethernet_private->
937 ETH_MIB_BAD_CRC_EVENT);
938 stats->multicast += (unsigned long)
939 eth_read_mib_counter (ethernet_private->port_num,
940 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
942 (unsigned long) eth_read_mib_counter (ethernet_private->
945 (unsigned long) eth_read_mib_counter (ethernet_private->
947 ETH_MIB_LATE_COLLISION);
948 /* detailed rx errors */
949 stats->rx_length_errors +=
950 (unsigned long) eth_read_mib_counter (ethernet_private->
952 ETH_MIB_UNDERSIZE_RECEIVED)
954 (unsigned long) eth_read_mib_counter (ethernet_private->
956 ETH_MIB_OVERSIZE_RECEIVED);
957 /* detailed tx errors */
960 #ifndef UPDATE_STATS_BY_SOFTWARE
961 /**********************************************************************
962 * mv64360_eth_print_stat
964 * Update the statistics structure in the private data structure
966 * Input : pointer to ethernet interface network device structure
968 **********************************************************************/
970 static void mv64360_eth_print_stat (struct eth_device *dev)
972 ETH_PORT_INFO *ethernet_private;
973 struct mv64360_eth_priv *port_private;
974 struct net_device_stats *stats;
976 ethernet_private = (ETH_PORT_INFO *) dev->priv;
978 (struct mv64360_eth_priv *) ethernet_private->port_private;
979 stats = port_private->stats;
981 /* These are false updates */
982 printf ("\n### Network statistics: ###\n");
983 printf ("--------------------------\n");
984 printf (" Packets received: %ld\n", stats->rx_packets);
985 printf (" Packets send: %ld\n", stats->tx_packets);
986 printf (" Received bytes: %ld\n", stats->rx_bytes);
987 printf (" Send bytes: %ld\n", stats->tx_bytes);
988 if (stats->rx_errors != 0)
989 printf (" Rx Errors: %ld\n",
991 if (stats->rx_dropped != 0)
992 printf (" Rx dropped (CRC Errors): %ld\n",
994 if (stats->multicast != 0)
995 printf (" Rx mulicast frames: %ld\n",
997 if (stats->collisions != 0)
998 printf (" No. of collisions: %ld\n",
1000 if (stats->rx_length_errors != 0)
1001 printf (" Rx length errors: %ld\n",
1002 stats->rx_length_errors);
1006 /**************************************************************************
1007 *network_start - Network Kick Off Routine UBoot
1010 **************************************************************************/
1012 bool db64360_eth_start (struct eth_device *dev)
1014 return (mv64360_eth_open (dev)); /* calls real open */
1017 /*************************************************************************
1018 **************************************************************************
1019 **************************************************************************
1020 * The second part is the low level driver of the gigE ethernet ports. *
1021 **************************************************************************
1022 **************************************************************************
1023 *************************************************************************/
1025 * based on Linux code
1026 * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
1027 * Copyright (C) 2002 rabeeh@galileo.co.il
1029 * This program is free software; you can redistribute it and/or
1030 * modify it under the terms of the GNU General Public License
1031 * as published by the Free Software Foundation; either version 2
1032 * of the License, or (at your option) any later version.
1034 * This program is distributed in the hope that it will be useful,
1035 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1036 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1037 * GNU General Public License for more details.
1039 * You should have received a copy of the GNU General Public License
1040 * along with this program; if not, write to the Free Software
1041 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
1045 /********************************************************************************
1046 * Marvell's Gigabit Ethernet controller low level driver
1049 * This file introduce low level API to Marvell's Gigabit Ethernet
1050 * controller. This Gigabit Ethernet Controller driver API controls
1051 * 1) Operations (i.e. port init, start, reset etc').
1052 * 2) Data flow (i.e. port send, receive etc').
1053 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1055 * This struct includes user configuration information as well as
1056 * driver internal data needed for its operations.
1058 * Supported Features:
1059 * - This low level driver is OS independent. Allocating memory for
1060 * the descriptor rings and buffers are not within the scope of
1062 * - The user is free from Rx/Tx queue managing.
1063 * - This low level driver introduce functionality API that enable
1064 * the to operate Marvell's Gigabit Ethernet Controller in a
1066 * - Simple Gigabit Ethernet port operation API.
1067 * - Simple Gigabit Ethernet port data flow API.
1068 * - Data flow and operation API support per queue functionality.
1069 * - Support cached descriptors for better performance.
1070 * - Enable access to all four DRAM banks and internal SRAM memory
1072 * - PHY access and control API.
1073 * - Port control register configuration API.
1074 * - Full control over Unicast and Multicast MAC configurations.
1078 * Initialization phase
1079 * This phase complete the initialization of the ETH_PORT_INFO
1081 * User information regarding port configuration has to be set
1082 * prior to calling the port initialization routine. For example,
1083 * the user has to assign the port_phy_addr field which is board
1084 * depended parameter.
1085 * In this phase any port Tx/Rx activity is halted, MIB counters
1086 * are cleared, PHY address is set according to user parameter and
1087 * access to DRAM and internal SRAM memory spaces.
1089 * Driver ring initialization
1090 * Allocating memory for the descriptor rings and buffers is not
1091 * within the scope of this driver. Thus, the user is required to
1092 * allocate memory for the descriptors ring and buffers. Those
1093 * memory parameters are used by the Rx and Tx ring initialization
1094 * routines in order to curve the descriptor linked list in a form
1096 * Note: Pay special attention to alignment issues when using
1097 * cached descriptors/buffers. In this phase the driver store
1098 * information in the ETH_PORT_INFO struct regarding each queue
1102 * This phase prepares the Ethernet port for Rx and Tx activity.
1103 * It uses the information stored in the ETH_PORT_INFO struct to
1104 * initialize the various port registers.
1107 * All packet references to/from the driver are done using PKT_INFO
1109 * This struct is a unified struct used with Rx and Tx operations.
1110 * This way the user is not required to be familiar with neither
1111 * Tx nor Rx descriptors structures.
1112 * The driver's descriptors rings are management by indexes.
1113 * Those indexes controls the ring resources and used to indicate
1114 * a SW resource error:
1116 * This index points to the current available resource for use. For
1117 * example in Rx process this index will point to the descriptor
1118 * that will be passed to the user upon calling the receive routine.
1119 * In Tx process, this index will point to the descriptor
1120 * that will be assigned with the user packet info and transmitted.
1122 * This index points to the descriptor that need to restore its
1123 * resources. For example in Rx process, using the Rx buffer return
1124 * API will attach the buffer returned in packet info to the
1125 * descriptor pointed by 'used'. In Tx process, using the Tx
1126 * descriptor return will merely return the user packet info with
1127 * the command status of the transmitted buffer pointed by the
1128 * 'used' index. Nevertheless, it is essential to use this routine
1129 * to update the 'used' index.
1131 * This index supports Tx Scatter-Gather. It points to the first
1132 * descriptor of a packet assembled of multiple buffers. For example
1133 * when in middle of Such packet we have a Tx resource error the
1134 * 'curr' index get the value of 'first' to indicate that the ring
1135 * returned to its state before trying to transmit this packet.
1137 * Receive operation:
1138 * The eth_port_receive API set the packet information struct,
1139 * passed by the caller, with received information from the
1140 * 'current' SDMA descriptor.
1141 * It is the user responsibility to return this resource back
1142 * to the Rx descriptor ring to enable the reuse of this source.
1143 * Return Rx resource is done using the eth_rx_return_buff API.
1145 * Transmit operation:
1146 * The eth_port_send API supports Scatter-Gather which enables to
1147 * send a packet spanned over multiple buffers. This means that
1148 * for each packet info structure given by the user and put into
1149 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1150 * bit will be set in the packet info command status field. This
1151 * API also consider restriction regarding buffer alignments and
1153 * The user must return a Tx resource after ensuring the buffer
1154 * has been transmitted to enable the Tx ring indexes to update.
1157 * This device is on-board. No jumper diagram is necessary.
1159 * EXTERNAL INTERFACE
1161 * Prior to calling the initialization routine eth_port_init() the user
1162 * must set the following fields under ETH_PORT_INFO struct:
1163 * port_num User Ethernet port number.
1164 * port_phy_addr User PHY address of Ethernet port.
1165 * port_mac_addr[6] User defined port MAC address.
1166 * port_config User port configuration value.
1167 * port_config_extend User port config extend value.
1168 * port_sdma_config User port SDMA config value.
1169 * port_serial_control User port serial control value.
1170 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1171 * *port_private User scratch pad for user specific data structures.
1173 * This driver introduce a set of default values:
1174 * PORT_CONFIG_VALUE Default port configuration value
1175 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1176 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1177 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1179 * This driver data flow is done using the PKT_INFO struct which is
1180 * a unified struct for Rx and Tx operations:
1181 * byte_cnt Tx/Rx descriptor buffer byte count.
1182 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1183 * cmd_sts Tx/Rx descriptor command status.
1184 * buf_ptr Tx/Rx descriptor buffer pointer.
1185 * return_info Tx/Rx user resource return information.
1188 * EXTERNAL SUPPORT REQUIREMENTS
1190 * This driver requires the following external support:
1192 * D_CACHE_FLUSH_LINE (address, address offset)
1194 * This macro applies assembly code to flush and invalidate cache
1196 * address - address base.
1197 * address offset - address offset
1202 * This macro applies assembly code to flush the CPU pipeline.
1204 *******************************************************************************/
1208 /* SDMA command macros */
1209 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1210 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1212 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1213 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1214 (1 << (8 + tx_queue)))
1216 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1217 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1219 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1220 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1222 #define CURR_RFD_GET(p_curr_desc, queue) \
1223 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1225 #define CURR_RFD_SET(p_curr_desc, queue) \
1226 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1228 #define USED_RFD_GET(p_used_desc, queue) \
1229 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1231 #define USED_RFD_SET(p_used_desc, queue)\
1232 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1235 #define CURR_TFD_GET(p_curr_desc, queue) \
1236 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1238 #define CURR_TFD_SET(p_curr_desc, queue) \
1239 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1241 #define USED_TFD_GET(p_used_desc, queue) \
1242 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1244 #define USED_TFD_SET(p_used_desc, queue) \
1245 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1247 #define FIRST_TFD_GET(p_first_desc, queue) \
1248 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1250 #define FIRST_TFD_SET(p_first_desc, queue) \
1251 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1254 /* Macros that save access to desc in order to find next desc pointer */
1255 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1257 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1259 #define LINK_UP_TIMEOUT 100000
1260 #define PHY_BUSY_TIMEOUT 10000000
1265 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1266 static int ethernet_phy_get (ETH_PORT eth_port_num);
1268 /* Ethernet Port routines */
1269 static void eth_set_access_control (ETH_PORT eth_port_num,
1270 ETH_WIN_PARAM * param);
1271 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1272 ETH_QUEUE queue, int option);
1274 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1275 unsigned char mc_byte,
1276 ETH_QUEUE queue, int option);
1277 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1279 ETH_QUEUE queue, int option);
1282 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1285 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1288 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1289 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1292 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1294 if (enable & (1 << bank))
1297 result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
1299 result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
1301 result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
1303 result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
1304 result &= 0x0000ffff;
1305 result = result << 16;
1309 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1312 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1314 if (enable & (1 << bank))
1317 result = MV_REG_READ (MV64360_CS_0_SIZE);
1319 result = MV_REG_READ (MV64360_CS_1_SIZE);
1321 result = MV_REG_READ (MV64360_CS_2_SIZE);
1323 result = MV_REG_READ (MV64360_CS_3_SIZE);
1325 result &= 0x0000ffff;
1326 result = result << 16;
1330 u32 mv_get_internal_sram_base (void)
1334 result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
1335 result &= 0x0000ffff;
1336 result = result << 16;
1340 /*******************************************************************************
1341 * eth_port_init - Initialize the Ethernet port driver
1344 * This function prepares the ethernet port to start its activity:
1345 * 1) Completes the ethernet port driver struct initialization toward port
1347 * 2) Resets the device to a quiescent state in case of warm reboot.
1348 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1349 * 4) Clean MAC tables. The reset status of those tables is unknown.
1350 * 5) Set PHY address.
1351 * Note: Call this routine prior to eth_port_start routine and after setting
1352 * user values in the user fields of Ethernet port control struct (i.e.
1356 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1364 *******************************************************************************/
1365 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1368 ETH_WIN_PARAM win_param;
1370 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1371 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1372 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1373 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1375 p_eth_port_ctrl->port_rx_queue_command = 0;
1376 p_eth_port_ctrl->port_tx_queue_command = 0;
1378 /* Zero out SW structs */
1379 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1380 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1381 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1382 p_eth_port_ctrl->rx_resource_err[queue] = false;
1385 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1386 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1387 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1388 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1389 p_eth_port_ctrl->tx_resource_err[queue] = false;
1392 eth_port_reset (p_eth_port_ctrl->port_num);
1394 /* Set access parameters for DRAM bank 0 */
1395 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1396 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1397 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1398 #ifndef CONFIG_NOT_COHERENT_CACHE
1399 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1401 win_param.high_addr = 0;
1403 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1404 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1405 if (win_param.size == 0)
1406 win_param.enable = 0;
1408 win_param.enable = 1; /* Enable the access */
1409 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1411 /* Set the access control for address window (EPAPR) READ & WRITE */
1412 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1414 /* Set access parameters for DRAM bank 1 */
1415 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1416 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1417 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1418 #ifndef CONFIG_NOT_COHERENT_CACHE
1419 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1421 win_param.high_addr = 0;
1423 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1424 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1425 if (win_param.size == 0)
1426 win_param.enable = 0;
1428 win_param.enable = 1; /* Enable the access */
1429 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1431 /* Set the access control for address window (EPAPR) READ & WRITE */
1432 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1434 /* Set access parameters for DRAM bank 2 */
1435 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1436 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1437 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1438 #ifndef CONFIG_NOT_COHERENT_CACHE
1439 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1441 win_param.high_addr = 0;
1443 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1444 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1445 if (win_param.size == 0)
1446 win_param.enable = 0;
1448 win_param.enable = 1; /* Enable the access */
1449 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1451 /* Set the access control for address window (EPAPR) READ & WRITE */
1452 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1454 /* Set access parameters for DRAM bank 3 */
1455 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1456 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1457 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1458 #ifndef CONFIG_NOT_COHERENT_CACHE
1459 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1461 win_param.high_addr = 0;
1463 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1464 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1465 if (win_param.size == 0)
1466 win_param.enable = 0;
1468 win_param.enable = 1; /* Enable the access */
1469 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1471 /* Set the access control for address window (EPAPR) READ & WRITE */
1472 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1474 /* Set access parameters for Internal SRAM */
1475 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1476 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1477 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1478 win_param.high_addr = 0;
1479 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1480 win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
1481 win_param.enable = 1; /* Enable the access */
1482 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1484 /* Set the access control for address window (EPAPR) READ & WRITE */
1485 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1487 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1489 ethernet_phy_set (p_eth_port_ctrl->port_num,
1490 p_eth_port_ctrl->port_phy_addr);
1496 /*******************************************************************************
1497 * eth_port_start - Start the Ethernet port activity.
1500 * This routine prepares the Ethernet port for Rx and Tx activity:
1501 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1502 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1503 * for Tx and ether_init_rx_desc_ring for Rx)
1504 * 2. Initialize and enable the Ethernet configuration port by writing to
1505 * the port's configuration and command registers.
1506 * 3. Initialize and enable the SDMA by writing to the SDMA's
1507 * configuration and command registers.
1508 * After completing these steps, the ethernet port SDMA can starts to
1509 * perform Rx and Tx activities.
1511 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1512 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1513 * ether_init_rx_desc_ring for Rx queues).
1516 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1519 * Ethernet port is ready to receive and transmit.
1522 * false if the port PHY is not up.
1525 *******************************************************************************/
1526 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1529 volatile ETH_TX_DESC *p_tx_curr_desc;
1530 volatile ETH_RX_DESC *p_rx_curr_desc;
1531 unsigned int phy_reg_data;
1532 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1535 /* Assignment of Tx CTRP of given queue */
1536 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1537 CURR_TFD_GET (p_tx_curr_desc, queue);
1538 MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1541 ((unsigned int) p_tx_curr_desc));
1545 /* Assignment of Rx CRDP of given queue */
1546 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1547 CURR_RFD_GET (p_rx_curr_desc, queue);
1548 MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1551 ((unsigned int) p_rx_curr_desc));
1553 if (p_rx_curr_desc != NULL)
1554 /* Add the assigned Ethernet address to the port's address table */
1555 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1556 p_eth_port_ctrl->port_mac_addr,
1560 /* Assign port configuration and command. */
1561 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
1562 p_eth_port_ctrl->port_config);
1564 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1565 p_eth_port_ctrl->port_config_extend);
1567 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1568 p_eth_port_ctrl->port_serial_control);
1570 MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1571 ETH_SERIAL_PORT_ENABLE);
1573 /* Assign port SDMA configuration */
1574 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
1575 p_eth_port_ctrl->port_sdma_config);
1577 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1578 (eth_port_num), 0x3fffffff);
1579 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1580 (eth_port_num), 0x03fffcff);
1581 /* Turn off the port/queue bandwidth limitation */
1582 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1584 /* Enable port Rx. */
1585 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1586 p_eth_port_ctrl->port_rx_queue_command);
1588 /* Check if link is up */
1589 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1591 if (!(phy_reg_data & 0x20))
1597 /*******************************************************************************
1598 * eth_port_uc_addr_set - This function Set the port Unicast address.
1601 * This function Set the port Ethernet MAC address.
1604 * ETH_PORT eth_port_num Port number.
1605 * char * p_addr Address to be set
1606 * ETH_QUEUE queue Rx queue number for this MAC address.
1609 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1610 * To set the unicast table with the proper information.
1615 *******************************************************************************/
1616 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1617 unsigned char *p_addr, ETH_QUEUE queue)
1622 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1623 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1624 (p_addr[2] << 8) | (p_addr[3] << 0);
1626 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1627 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1629 /* Accept frames of this address */
1630 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1635 /*******************************************************************************
1636 * eth_port_uc_addr - This function Set the port unicast address table
1639 * This function locates the proper entry in the Unicast table for the
1640 * specified MAC nibble and sets its properties according to function
1644 * ETH_PORT eth_port_num Port number.
1645 * unsigned char uc_nibble Unicast MAC Address last nibble.
1646 * ETH_QUEUE queue Rx queue number for this MAC address.
1647 * int option 0 = Add, 1 = remove address.
1650 * This function add/removes MAC addresses from the port unicast address
1654 * true is output succeeded.
1655 * false if option parameter is invalid.
1657 *******************************************************************************/
1658 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1659 unsigned char uc_nibble,
1660 ETH_QUEUE queue, int option)
1662 unsigned int unicast_reg;
1663 unsigned int tbl_offset;
1664 unsigned int reg_offset;
1666 /* Locate the Unicast table entry */
1667 uc_nibble = (0xf & uc_nibble);
1668 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1669 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1672 case REJECT_MAC_ADDR:
1673 /* Clear accepts frame bit at specified unicast DA table entry */
1675 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1679 unicast_reg &= (0x0E << (8 * reg_offset));
1681 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1683 + tbl_offset), unicast_reg);
1686 case ACCEPT_MAC_ADDR:
1687 /* Set accepts frame bit at unicast DA filter table entry */
1689 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1693 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1695 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1697 + tbl_offset), unicast_reg);
1708 /*******************************************************************************
1709 * eth_port_mc_addr - Multicast address settings.
1712 * This API controls the MV device MAC multicast support.
1713 * The MV device supports multicast using two tables:
1714 * 1) Special Multicast Table for MAC addresses of the form
1715 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1716 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1717 * Table entries in the DA-Filter table.
1718 * In this case, the function calls eth_port_smc_addr() routine to set the
1719 * Special Multicast Table.
1720 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1721 * is used as an index to the Other Multicast Table entries in the
1723 * In this case, the function calculates the CRC-8bit value and calls
1724 * eth_port_omc_addr() routine to set the Other Multicast Table.
1726 * ETH_PORT eth_port_num Port number.
1727 * unsigned char *p_addr Unicast MAC Address.
1728 * ETH_QUEUE queue Rx queue number for this MAC address.
1729 * int option 0 = Add, 1 = remove address.
1735 * true is output succeeded.
1736 * false if add_address_table_entry( ) failed.
1738 *******************************************************************************/
1739 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1740 unsigned char *p_addr,
1741 ETH_QUEUE queue, int option)
1745 unsigned char crc_result = 0;
1751 if ((p_addr[0] == 0x01) &&
1752 (p_addr[1] == 0x00) &&
1753 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1755 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1757 /* Calculate CRC-8 out of the given address */
1758 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1759 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1760 (p_addr[4] << 8) | (p_addr[5] << 0);
1762 for (i = 0; i < 32; i++)
1763 mac_array[i] = (mac_l >> i) & 0x1;
1764 for (i = 32; i < 48; i++)
1765 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1768 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1769 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1770 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1771 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1772 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1773 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1774 mac_array[6] ^ mac_array[0];
1776 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1777 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1778 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1779 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1780 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1781 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1782 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1783 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1784 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1787 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1788 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1789 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1790 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1791 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1792 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1793 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1794 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1796 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1797 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1798 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1799 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1800 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1801 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1802 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1803 mac_array[2] ^ mac_array[1];
1805 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1806 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1807 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1808 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1809 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1810 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1811 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1814 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1815 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1816 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1817 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1818 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
1819 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
1820 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
1823 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
1824 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
1825 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
1826 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1827 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
1828 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1829 mac_array[6] ^ mac_array[5] ^ mac_array[4];
1831 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
1832 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
1833 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
1834 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1835 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
1836 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
1837 mac_array[6] ^ mac_array[5];
1839 for (i = 0; i < 8; i++)
1840 crc_result = crc_result | (crc[i] << i);
1842 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
1847 /*******************************************************************************
1848 * eth_port_smc_addr - Special Multicast address settings.
1851 * This routine controls the MV device special MAC multicast support.
1852 * The Special Multicast Table for MAC addresses supports MAC of the form
1853 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1854 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1855 * Table entries in the DA-Filter table.
1856 * This function set the Special Multicast Table appropriate entry
1857 * according to the argument given.
1860 * ETH_PORT eth_port_num Port number.
1861 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
1862 * ETH_QUEUE queue Rx queue number for this MAC address.
1863 * int option 0 = Add, 1 = remove address.
1869 * true is output succeeded.
1870 * false if option parameter is invalid.
1872 *******************************************************************************/
1873 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1874 unsigned char mc_byte,
1875 ETH_QUEUE queue, int option)
1877 unsigned int smc_table_reg;
1878 unsigned int tbl_offset;
1879 unsigned int reg_offset;
1881 /* Locate the SMC table entry */
1882 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
1883 reg_offset = mc_byte % 4; /* Entry offset within the above register */
1887 case REJECT_MAC_ADDR:
1888 /* Clear accepts frame bit at specified Special DA table entry */
1890 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1891 smc_table_reg &= (0x0E << (8 * reg_offset));
1893 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1896 case ACCEPT_MAC_ADDR:
1897 /* Set accepts frame bit at specified Special DA table entry */
1899 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1900 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1902 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1911 /*******************************************************************************
1912 * eth_port_omc_addr - Multicast address settings.
1915 * This routine controls the MV device Other MAC multicast support.
1916 * The Other Multicast Table is used for multicast of another type.
1917 * A CRC-8bit is used as an index to the Other Multicast Table entries
1918 * in the DA-Filter table.
1919 * The function gets the CRC-8bit value from the calling routine and
1920 * set the Other Multicast Table appropriate entry according to the
1921 * CRC-8 argument given.
1924 * ETH_PORT eth_port_num Port number.
1925 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
1926 * ETH_QUEUE queue Rx queue number for this MAC address.
1927 * int option 0 = Add, 1 = remove address.
1933 * true is output succeeded.
1934 * false if option parameter is invalid.
1936 *******************************************************************************/
1937 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1939 ETH_QUEUE queue, int option)
1941 unsigned int omc_table_reg;
1942 unsigned int tbl_offset;
1943 unsigned int reg_offset;
1945 /* Locate the OMC table entry */
1946 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1947 reg_offset = crc8 % 4; /* Entry offset within the above register */
1951 case REJECT_MAC_ADDR:
1952 /* Clear accepts frame bit at specified Other DA table entry */
1954 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1955 omc_table_reg &= (0x0E << (8 * reg_offset));
1957 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1960 case ACCEPT_MAC_ADDR:
1961 /* Set accepts frame bit at specified Other DA table entry */
1963 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1964 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1966 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1976 /*******************************************************************************
1977 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1980 * Go through all the DA filter tables (Unicast, Special Multicast & Other
1981 * Multicast) and set each entry to 0.
1984 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
1987 * Multicast and Unicast packets are rejected.
1992 *******************************************************************************/
1993 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
1997 /* Clear DA filter unicast table (Ex_dFUT) */
1998 for (table_index = 0; table_index <= 0xC; table_index += 4)
1999 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
2000 (eth_port_num) + table_index), 0);
2002 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2003 /* Clear DA filter special multicast table (Ex_dFSMT) */
2004 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2005 /* Clear DA filter other multicast table (Ex_dFOMT) */
2006 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2010 /*******************************************************************************
2011 * eth_clear_mib_counters - Clear all MIB counters
2014 * This function clears all MIB counters of a specific ethernet port.
2015 * A read from the MIB counter will reset the counter.
2018 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2021 * After reading all MIB counters, the counters resets.
2024 * MIB counter value.
2026 *******************************************************************************/
2027 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2031 /* Perform dummy reads from MIB counters */
2032 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2034 (void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
2035 (eth_port_num) + i));
2041 /*******************************************************************************
2042 * eth_read_mib_counter - Read a MIB counter
2045 * This function reads a MIB counter of a specific ethernet port.
2046 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2047 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2048 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2049 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2052 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2053 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2056 * After reading the MIB counter, the counter resets.
2059 * MIB counter value.
2061 *******************************************************************************/
2062 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2063 unsigned int mib_offset)
2065 return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
2069 /*******************************************************************************
2070 * ethernet_phy_set - Set the ethernet port PHY address.
2073 * This routine set the ethernet port PHY address according to given
2077 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2080 * Set PHY Address Register with given PHY address parameter.
2085 *******************************************************************************/
2086 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2088 unsigned int reg_data;
2090 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2092 reg_data &= ~(0x1F << (5 * eth_port_num));
2093 reg_data |= (phy_addr << (5 * eth_port_num));
2095 MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
2100 /*******************************************************************************
2101 * ethernet_phy_get - Get the ethernet port PHY address.
2104 * This routine returns the given ethernet port PHY address.
2107 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2115 *******************************************************************************/
2116 static int ethernet_phy_get (ETH_PORT eth_port_num)
2118 unsigned int reg_data;
2120 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2122 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2125 /*******************************************************************************
2126 * ethernet_phy_reset - Reset Ethernet port PHY.
2129 * This routine utilize the SMI interface to reset the ethernet port PHY.
2130 * The routine waits until the link is up again or link up is timeout.
2133 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2136 * The ethernet port PHY renew its link.
2141 *******************************************************************************/
2142 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2144 unsigned int time_out = 50;
2145 unsigned int phy_reg_data;
2148 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2149 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2150 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2152 /* Poll on the PHY LINK */
2154 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2156 if (time_out-- == 0)
2159 while (!(phy_reg_data & 0x20));
2164 /*******************************************************************************
2165 * eth_port_reset - Reset Ethernet port
2168 * This routine resets the chip by aborting any SDMA engine activity and
2169 * clearing the MIB counters. The Receiver and the Transmit unit are in
2170 * idle state after this command is performed and the port is disabled.
2173 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2176 * Channel activity is halted.
2181 *******************************************************************************/
2182 static void eth_port_reset (ETH_PORT eth_port_num)
2184 unsigned int reg_data;
2186 /* Stop Tx port activity. Check port Tx activity. */
2188 MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2191 if (reg_data & 0xFF) {
2192 /* Issue stop command for active channels only */
2193 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2194 (eth_port_num), (reg_data << 8));
2196 /* Wait for all Tx activity to terminate. */
2198 /* Check port cause register that all Tx queues are stopped */
2201 (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2204 while (reg_data & 0xFF);
2207 /* Stop Rx port activity. Check port Rx activity. */
2209 MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2212 if (reg_data & 0xFF) {
2213 /* Issue stop command for active channels only */
2214 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2215 (eth_port_num), (reg_data << 8));
2217 /* Wait for all Rx activity to terminate. */
2219 /* Check port cause register that all Rx queues are stopped */
2222 (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2225 while (reg_data & 0xFF);
2229 /* Clear all MIB counters */
2230 eth_clear_mib_counters (eth_port_num);
2232 /* Reset the Enable bit in the Configuration Register */
2234 MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
2236 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2237 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2243 #if 0 /* Not needed here */
2244 /*******************************************************************************
2245 * ethernet_set_config_reg - Set specified bits in configuration register.
2248 * This function sets specified bits in the given ethernet
2249 * configuration register.
2252 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2253 * unsigned int value 32 bit value.
2256 * The set bits in the value parameter are set in the configuration
2262 *******************************************************************************/
2263 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2266 unsigned int eth_config_reg;
2269 MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
2270 eth_config_reg |= value;
2271 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
2279 /*******************************************************************************
2280 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2283 * This function resets specified bits in the given Ethernet
2284 * configuration register.
2287 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2288 * unsigned int value 32 bit value.
2291 * The set bits in the value parameter are reset in the configuration
2297 *******************************************************************************/
2298 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2301 unsigned int eth_config_reg;
2303 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2305 eth_config_reg &= ~value;
2306 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2313 #if 0 /* Not needed here */
2314 /*******************************************************************************
2315 * ethernet_get_config_reg - Get the port configuration register
2318 * This function returns the configuration register value of the given
2322 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2328 * Port configuration register value.
2330 *******************************************************************************/
2331 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2333 unsigned int eth_config_reg;
2335 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2337 return eth_config_reg;
2342 /*******************************************************************************
2343 * eth_port_read_smi_reg - Read PHY registers
2346 * This routine utilize the SMI interface to interact with the PHY in
2347 * order to perform PHY register read.
2350 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2351 * unsigned int phy_reg PHY register address offset.
2352 * unsigned int *value Register value buffer.
2355 * Write the value of a specified PHY register into given buffer.
2358 * false if the PHY is busy or read data is not in valid state.
2361 *******************************************************************************/
2362 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2363 unsigned int phy_reg, unsigned int *value)
2365 unsigned int reg_value;
2366 unsigned int time_out = PHY_BUSY_TIMEOUT;
2369 phy_addr = ethernet_phy_get (eth_port_num);
2370 /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
2372 /* first check that it is not busy */
2374 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2375 if (time_out-- == 0) {
2379 while (reg_value & ETH_SMI_BUSY);
2383 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2384 (phy_addr << 16) | (phy_reg << 21) |
2385 ETH_SMI_OPCODE_READ);
2387 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2390 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2391 if (time_out-- == 0) {
2395 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2397 /* Wait for the data to update in the SMI register */
2398 #define PHY_UPDATE_TIMEOUT 10000
2399 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2401 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2403 *value = reg_value & 0xffff;
2408 /*******************************************************************************
2409 * eth_port_write_smi_reg - Write to PHY registers
2412 * This routine utilize the SMI interface to interact with the PHY in
2413 * order to perform writes to PHY registers.
2416 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2417 * unsigned int phy_reg PHY register address offset.
2418 * unsigned int value Register value.
2421 * Write the given value to the specified PHY register.
2424 * false if the PHY is busy.
2427 *******************************************************************************/
2428 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2429 unsigned int phy_reg, unsigned int value)
2431 unsigned int reg_value;
2432 unsigned int time_out = PHY_BUSY_TIMEOUT;
2435 phy_addr = ethernet_phy_get (eth_port_num);
2437 /* first check that it is not busy */
2439 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2440 if (time_out-- == 0) {
2444 while (reg_value & ETH_SMI_BUSY);
2447 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2448 (phy_addr << 16) | (phy_reg << 21) |
2449 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2453 /*******************************************************************************
2454 * eth_set_access_control - Config address decode parameters for Ethernet unit
2457 * This function configures the address decode parameters for the Gigabit
2458 * Ethernet Controller according the given parameters struct.
2461 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2462 * ETH_WIN_PARAM *param Address decode parameter struct.
2465 * An access window is opened using the given access parameters.
2470 *******************************************************************************/
2471 static void eth_set_access_control (ETH_PORT eth_port_num,
2472 ETH_WIN_PARAM * param)
2474 unsigned int access_prot_reg;
2476 /* Set access control register */
2477 access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
2479 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2480 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2481 MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2484 /* Set window Size reg (SR) */
2485 MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
2486 (ETH_SIZE_REG_GAP * param->win)),
2487 (((param->size / 0x10000) - 1) << 16));
2489 /* Set window Base address reg (BA) */
2490 MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2491 (param->target | param->attributes | param->base_addr));
2492 /* High address remap reg (HARR) */
2494 MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
2495 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2498 /* Base address enable reg (BARER) */
2499 if (param->enable == 1)
2500 MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2503 MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2507 /*******************************************************************************
2508 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2511 * This function prepares a Rx chained list of descriptors and packet
2512 * buffers in a form of a ring. The routine must be called after port
2513 * initialization routine and before port start routine.
2514 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2515 * devices in the system (i.e. DRAM). This function uses the ethernet
2516 * struct 'virtual to physical' routine (set by the user) to set the ring
2517 * with physical addresses.
2520 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2521 * ETH_QUEUE rx_queue Number of Rx queue.
2522 * int rx_desc_num Number of Rx descriptors
2523 * int rx_buff_size Size of Rx buffer
2524 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2525 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2528 * The routine updates the Ethernet port control struct with information
2529 * regarding the Rx descriptors and buffers.
2532 * false if the given descriptors memory area is not aligned according to
2533 * Ethernet SDMA specifications.
2536 *******************************************************************************/
2537 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2541 unsigned int rx_desc_base_addr,
2542 unsigned int rx_buff_base_addr)
2544 ETH_RX_DESC *p_rx_desc;
2545 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2546 unsigned int buffer_addr;
2547 int ix; /* a counter */
2550 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2551 p_rx_prev_desc = p_rx_desc;
2552 buffer_addr = rx_buff_base_addr;
2554 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2555 if (rx_buff_base_addr & 0xF)
2558 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2559 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2562 /* Rx buffers must be 64-bit aligned. */
2563 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2566 /* initialize the Rx descriptors ring */
2567 for (ix = 0; ix < rx_desc_num; ix++) {
2568 p_rx_desc->buf_size = rx_buff_size;
2569 p_rx_desc->byte_cnt = 0x0000;
2570 p_rx_desc->cmd_sts =
2571 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2572 p_rx_desc->next_desc_ptr =
2573 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2574 p_rx_desc->buf_ptr = buffer_addr;
2575 p_rx_desc->return_info = 0x00000000;
2576 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2577 buffer_addr += rx_buff_size;
2578 p_rx_prev_desc = p_rx_desc;
2579 p_rx_desc = (ETH_RX_DESC *)
2580 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2583 /* Closing Rx descriptors ring */
2584 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2585 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2587 /* Save Rx desc pointer to driver struct. */
2588 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2589 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2591 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2592 (ETH_RX_DESC *) rx_desc_base_addr;
2593 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2594 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2596 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2601 /*******************************************************************************
2602 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2605 * This function prepares a Tx chained list of descriptors and packet
2606 * buffers in a form of a ring. The routine must be called after port
2607 * initialization routine and before port start routine.
2608 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2609 * devices in the system (i.e. DRAM). This function uses the ethernet
2610 * struct 'virtual to physical' routine (set by the user) to set the ring
2611 * with physical addresses.
2614 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2615 * ETH_QUEUE tx_queue Number of Tx queue.
2616 * int tx_desc_num Number of Tx descriptors
2617 * int tx_buff_size Size of Tx buffer
2618 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2619 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2622 * The routine updates the Ethernet port control struct with information
2623 * regarding the Tx descriptors and buffers.
2626 * false if the given descriptors memory area is not aligned according to
2627 * Ethernet SDMA specifications.
2630 *******************************************************************************/
2631 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2635 unsigned int tx_desc_base_addr,
2636 unsigned int tx_buff_base_addr)
2639 ETH_TX_DESC *p_tx_desc;
2640 ETH_TX_DESC *p_tx_prev_desc;
2641 unsigned int buffer_addr;
2642 int ix; /* a counter */
2645 /* save the first desc pointer to link with the last descriptor */
2646 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2647 p_tx_prev_desc = p_tx_desc;
2648 buffer_addr = tx_buff_base_addr;
2650 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2651 if (tx_buff_base_addr & 0xF)
2654 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2655 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2656 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2659 /* Initialize the Tx descriptors ring */
2660 for (ix = 0; ix < tx_desc_num; ix++) {
2661 p_tx_desc->byte_cnt = 0x0000;
2662 p_tx_desc->l4i_chk = 0x0000;
2663 p_tx_desc->cmd_sts = 0x00000000;
2664 p_tx_desc->next_desc_ptr =
2665 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2667 p_tx_desc->buf_ptr = buffer_addr;
2668 p_tx_desc->return_info = 0x00000000;
2669 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2670 buffer_addr += tx_buff_size;
2671 p_tx_prev_desc = p_tx_desc;
2672 p_tx_desc = (ETH_TX_DESC *)
2673 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2676 /* Closing Tx descriptors ring */
2677 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2678 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2679 /* Set Tx desc pointer in driver struct. */
2680 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2681 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2683 /* Init Tx ring base and size parameters */
2684 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2685 (ETH_TX_DESC *) tx_desc_base_addr;
2686 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2687 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2689 /* Add the queue to the list of Tx queues of this port */
2690 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2695 /*******************************************************************************
2696 * eth_port_send - Send an Ethernet packet
2699 * This routine send a given packet described by p_pktinfo parameter. It
2700 * supports transmitting of a packet spaned over multiple buffers. The
2701 * routine updates 'curr' and 'first' indexes according to the packet
2702 * segment passed to the routine. In case the packet segment is first,
2703 * the 'first' index is update. In any case, the 'curr' index is updated.
2704 * If the routine get into Tx resource error it assigns 'curr' index as
2705 * 'first'. This way the function can abort Tx process of multiple
2706 * descriptors per packet.
2709 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2710 * ETH_QUEUE tx_queue Number of Tx queue.
2711 * PKT_INFO *p_pkt_info User packet buffer.
2714 * Tx ring 'curr' and 'first' indexes are updated.
2717 * ETH_QUEUE_FULL in case of Tx resource error.
2718 * ETH_ERROR in case the routine can not access Tx desc ring.
2719 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2722 *******************************************************************************/
2723 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2725 PKT_INFO * p_pkt_info)
2727 volatile ETH_TX_DESC *p_tx_desc_first;
2728 volatile ETH_TX_DESC *p_tx_desc_curr;
2729 volatile ETH_TX_DESC *p_tx_next_desc_curr;
2730 volatile ETH_TX_DESC *p_tx_desc_used;
2731 unsigned int command_status;
2733 /* Do not process Tx ring in case of Tx ring resource error */
2734 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2735 return ETH_QUEUE_FULL;
2737 /* Get the Tx Desc ring indexes */
2738 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
2739 USED_TFD_GET (p_tx_desc_used, tx_queue);
2741 if (p_tx_desc_curr == NULL)
2744 /* The following parameters are used to save readings from memory */
2745 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
2746 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2748 if (command_status & (ETH_TX_FIRST_DESC)) {
2749 /* Update first desc */
2750 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
2751 p_tx_desc_first = p_tx_desc_curr;
2753 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2754 command_status |= ETH_BUFFER_OWNED_BY_DMA;
2757 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
2758 /* boundary. We use the memory allocated for Tx descriptor. This memory */
2759 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
2760 if (p_pkt_info->byte_cnt <= 8) {
2761 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
2764 p_tx_desc_curr->buf_ptr =
2765 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
2766 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
2767 p_pkt_info->byte_cnt);
2769 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
2771 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
2772 p_tx_desc_curr->return_info = p_pkt_info->return_info;
2774 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
2775 /* Set last desc with DMA ownership and interrupt enable. */
2776 p_tx_desc_curr->cmd_sts = command_status |
2777 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2779 if (p_tx_desc_curr != p_tx_desc_first)
2780 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
2782 /* Flush CPU pipe */
2784 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2785 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
2788 /* Apply send command */
2789 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
2791 /* Finish Tx packet. Update first desc in case of Tx resource error */
2792 p_tx_desc_first = p_tx_next_desc_curr;
2793 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
2796 p_tx_desc_curr->cmd_sts = command_status;
2797 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2800 /* Check for ring index overlap in the Tx desc ring */
2801 if (p_tx_next_desc_curr == p_tx_desc_used) {
2802 /* Update the current descriptor */
2803 CURR_TFD_SET (p_tx_desc_first, tx_queue);
2805 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
2806 return ETH_QUEUE_LAST_RESOURCE;
2808 /* Update the current descriptor */
2809 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
2814 /*******************************************************************************
2815 * eth_tx_return_desc - Free all used Tx descriptors
2818 * This routine returns the transmitted packet information to the caller.
2819 * It uses the 'first' index to support Tx desc return in case a transmit
2820 * of a packet spanned over multiple buffer still in process.
2821 * In case the Tx queue was in "resource error" condition, where there are
2822 * no available Tx resources, the function resets the resource error flag.
2825 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2826 * ETH_QUEUE tx_queue Number of Tx queue.
2827 * PKT_INFO *p_pkt_info User packet buffer.
2830 * Tx ring 'first' and 'used' indexes are updated.
2833 * ETH_ERROR in case the routine can not access Tx desc ring.
2834 * ETH_RETRY in case there is transmission in process.
2835 * ETH_END_OF_JOB if the routine has nothing to release.
2838 *******************************************************************************/
2839 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
2842 PKT_INFO * p_pkt_info)
2844 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
2845 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
2846 unsigned int command_status;
2849 /* Get the Tx Desc ring indexes */
2850 USED_TFD_GET (p_tx_desc_used, tx_queue);
2851 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2855 if (p_tx_desc_used == NULL)
2858 command_status = p_tx_desc_used->cmd_sts;
2860 /* Still transmitting... */
2861 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2862 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2866 /* Stop release. About to overlap the current available Tx descriptor */
2867 if ((p_tx_desc_used == p_tx_desc_first) &&
2868 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
2869 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2870 return ETH_END_OF_JOB;
2873 /* Pass the packet information to the caller */
2874 p_pkt_info->cmd_sts = command_status;
2875 p_pkt_info->return_info = p_tx_desc_used->return_info;
2876 p_tx_desc_used->return_info = 0;
2878 /* Update the next descriptor to release. */
2879 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
2881 /* Any Tx return cancels the Tx resource error status */
2882 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2883 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
2885 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2891 /*******************************************************************************
2892 * eth_port_receive - Get received information from Rx ring.
2895 * This routine returns the received data to the caller. There is no
2896 * data copying during routine operation. All information is returned
2897 * using pointer to packet information struct passed from the caller.
2898 * If the routine exhausts Rx ring resources then the resource error flag
2902 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2903 * ETH_QUEUE rx_queue Number of Rx queue.
2904 * PKT_INFO *p_pkt_info User packet buffer.
2907 * Rx ring current and used indexes are updated.
2910 * ETH_ERROR in case the routine can not access Rx desc ring.
2911 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2912 * ETH_END_OF_JOB if there is no received data.
2915 *******************************************************************************/
2916 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
2918 PKT_INFO * p_pkt_info)
2920 volatile ETH_RX_DESC *p_rx_curr_desc;
2921 volatile ETH_RX_DESC *p_rx_next_curr_desc;
2922 volatile ETH_RX_DESC *p_rx_used_desc;
2923 unsigned int command_status;
2925 /* Do not process Rx ring in case of Rx ring resource error */
2926 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
2927 printf ("\nRx Queue is full ...\n");
2928 return ETH_QUEUE_FULL;
2931 /* Get the Rx Desc ring 'curr and 'used' indexes */
2932 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
2933 USED_RFD_GET (p_rx_used_desc, rx_queue);
2936 if (p_rx_curr_desc == NULL)
2939 /* The following parameters are used to save readings from memory */
2940 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
2941 command_status = p_rx_curr_desc->cmd_sts;
2943 /* Nothing to receive... */
2944 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2945 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
2946 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2947 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
2948 return ETH_END_OF_JOB;
2951 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
2952 p_pkt_info->cmd_sts = command_status;
2953 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
2954 p_pkt_info->return_info = p_rx_curr_desc->return_info;
2955 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
2957 /* Clean the return info field to indicate that the packet has been */
2958 /* moved to the upper layers */
2959 p_rx_curr_desc->return_info = 0;
2961 /* Update 'curr' in data structure */
2962 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
2964 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
2965 if (p_rx_next_curr_desc == p_rx_used_desc)
2966 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
2968 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2973 /*******************************************************************************
2974 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2977 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2978 * next 'used' descriptor and attached the returned buffer to it.
2979 * In case the Rx ring was in "resource error" condition, where there are
2980 * no available Rx resources, the function resets the resource error flag.
2983 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2984 * ETH_QUEUE rx_queue Number of Rx queue.
2985 * PKT_INFO *p_pkt_info Information on the returned buffer.
2988 * New available Rx resource in Rx descriptor ring.
2991 * ETH_ERROR in case the routine can not access Rx desc ring.
2994 *******************************************************************************/
2995 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
2998 PKT_INFO * p_pkt_info)
3000 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
3002 /* Get 'used' Rx descriptor */
3003 USED_RFD_GET (p_used_rx_desc, rx_queue);
3006 if (p_used_rx_desc == NULL)
3009 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3010 p_used_rx_desc->return_info = p_pkt_info->return_info;
3011 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
3012 p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
3014 /* Flush the write pipe */
3017 /* Return the descriptor to DMA ownership */
3018 p_used_rx_desc->cmd_sts =
3019 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3021 /* Flush descriptor and CPU pipe */
3022 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3025 /* Move the used descriptor pointer to the next descriptor */
3026 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3028 /* Any Rx return cancels the Rx resource error status */
3029 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3030 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3035 /*******************************************************************************
3036 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3039 * This routine sets the RX coalescing interrupt mechanism parameter.
3040 * This parameter is a timeout counter, that counts in 64 t_clk
3041 * chunks ; that when timeout event occurs a maskable interrupt
3043 * The parameter is calculated using the tClk of the MV-643xx chip
3044 * , and the required delay of the interrupt in usec.
3047 * ETH_PORT eth_port_num Ethernet port number
3048 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3049 * unsigned int delay Delay in usec
3052 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3055 * The interrupt coalescing value set in the gigE port.
3057 *******************************************************************************/
3059 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3065 coal = ((t_clk / 1000000) * delay) / 64;
3066 /* Set RX Coalescing mechanism */
3067 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
3068 ((coal & 0x3fff) << 8) |
3070 (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
3076 /*******************************************************************************
3077 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3080 * This routine sets the TX coalescing interrupt mechanism parameter.
3081 * This parameter is a timeout counter, that counts in 64 t_clk
3082 * chunks ; that when timeout event occurs a maskable interrupt
3084 * The parameter is calculated using the t_cLK frequency of the
3085 * MV-643xx chip and the required delay in the interrupt in uSec
3088 * ETH_PORT eth_port_num Ethernet port number
3089 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3090 * unsigned int delay Delay in uSeconds
3093 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3096 * The interrupt coalescing value set in the gigE port.
3098 *******************************************************************************/
3100 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3106 coal = ((t_clk / 1000000) * delay) / 64;
3107 /* Set TX Coalescing mechanism */
3108 MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3114 /*******************************************************************************
3115 * eth_b_copy - Copy bytes from source to destination
3118 * This function supports the eight bytes limitation on Tx buffer size.
3119 * The routine will zero eight bytes starting from the destination address
3120 * followed by copying bytes from the source address to the destination.
3123 * unsigned int src_addr 32 bit source address.
3124 * unsigned int dst_addr 32 bit destination address.
3125 * int byte_count Number of bytes to copy.
3133 *******************************************************************************/
3134 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3137 /* Zero the dst_addr area */
3138 *(unsigned int *) dst_addr = 0x0;
3140 while (byte_count != 0) {
3141 *(char *) dst_addr = *(char *) src_addr;