3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* PCI.c - PCI functions */
32 void pciauto_config_init(struct pci_controller *hose);
33 int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
36 #include "../../Marvell/include/pci.h"
39 #undef IDE_SET_NATIVE_MODE
40 static unsigned int local_buses[] = { 0, 0 };
42 static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
43 {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
44 {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
49 static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
50 static void gt_pci_bus_mode_display (PCI_HOST host)
55 mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
58 printf ("PCI %d bus mode: Conventional PCI\n", host);
61 printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
64 printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
67 printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
70 printf ("Unknown BUS %d\n", mode);
75 static const unsigned int pci_p2p_configuration_reg[] = {
76 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
79 static const unsigned int pci_configuration_address[] = {
80 PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
83 static const unsigned int pci_configuration_data[] = {
84 PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
85 PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
88 static const unsigned int pci_error_cause_reg[] = {
89 PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
92 static const unsigned int pci_arbiter_control[] = {
93 PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
96 static const unsigned int pci_address_space_en[] = {
97 PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
100 static const unsigned int pci_snoop_control_base_0_low[] = {
101 PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
103 static const unsigned int pci_snoop_control_top_0[] = {
104 PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
107 static const unsigned int pci_access_control_base_0_low[] = {
108 PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
110 static const unsigned int pci_access_control_top_0[] = {
111 PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
114 static const unsigned int pci_scs_bank_size[2][4] = {
115 {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
116 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
117 {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
118 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
121 static const unsigned int pci_p2p_configuration[] = {
122 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
126 /********************************************************************
127 * pciWriteConfigReg - Write to a PCI configuration register
128 * - Make sure the GT is configured as a master before writing
129 * to another device on the PCI.
130 * - The function takes care of Big/Little endian conversion.
133 * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
134 * (or any other PCI device spec)
135 * pciDevNum: The device number needs to be addressed.
137 * Configuration Address 0xCF8:
139 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
140 * |congif|Reserved| Bus |Device|Function|Register|00|
141 * |Enable| |Number|Number| Number | Number | | <=field Name
143 *********************************************************************/
144 void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
145 unsigned int pciDevNum, unsigned int data)
147 volatile unsigned int DataForAddrReg;
148 unsigned int functionNum;
149 unsigned int busNum = 0;
152 if (pciDevNum > 32) /* illegal device Number */
154 if (pciDevNum == SELF) { /* configure our configuration space. */
156 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
158 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
161 functionNum = regOffset & 0x00000700;
162 pciDevNum = pciDevNum << 11;
163 regOffset = regOffset & 0xfc;
165 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
166 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
167 GT_REG_READ (pci_configuration_address[host], &addr);
168 if (addr != DataForAddrReg)
170 GT_REG_WRITE (pci_configuration_data[host], data);
173 /********************************************************************
174 * pciReadConfigReg - Read from a PCI0 configuration register
175 * - Make sure the GT is configured as a master before reading
176 * from another device on the PCI.
177 * - The function takes care of Big/Little endian conversion.
178 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
180 * pciDevNum: The device number needs to be addressed.
181 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
182 * cause register to make sure the data is valid
184 * Configuration Address 0xCF8:
186 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
187 * |congif|Reserved| Bus |Device|Function|Register|00|
188 * |Enable| |Number|Number| Number | Number | | <=field Name
190 *********************************************************************/
191 unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
192 unsigned int pciDevNum)
194 volatile unsigned int DataForAddrReg;
196 unsigned int functionNum;
197 unsigned int busNum = 0;
199 if (pciDevNum > 32) /* illegal device Number */
201 if (pciDevNum == SELF) { /* configure our configuration space. */
203 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
205 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
208 functionNum = regOffset & 0x00000700;
209 pciDevNum = pciDevNum << 11;
210 regOffset = regOffset & 0xfc;
212 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
213 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
214 GT_REG_READ (pci_configuration_address[host], &data);
215 if (data != DataForAddrReg)
217 GT_REG_READ (pci_configuration_data[host], &data);
221 /********************************************************************
222 * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
223 * the agent is placed on another Bus. For more
224 * information read P2P in the PCI spec.
226 * Inputs: unsigned int regOffset - The register offset as it apears in the
227 * GT spec (or any other PCI device spec).
228 * unsigned int pciDevNum - The device number needs to be addressed.
229 * unsigned int busNum - On which bus does the Target agent connect
231 * unsigned int data - data to be written.
233 * Configuration Address 0xCF8:
235 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
236 * |congif|Reserved| Bus |Device|Function|Register|01|
237 * |Enable| |Number|Number| Number | Number | | <=field Name
239 * The configuration Address is configure as type-I (bits[1:0] = '01') due to
240 * PCI spec referring to P2P.
242 *********************************************************************/
243 void pciOverBridgeWriteConfigReg (PCI_HOST host,
244 unsigned int regOffset,
245 unsigned int pciDevNum,
246 unsigned int busNum, unsigned int data)
248 unsigned int DataForReg;
249 unsigned int functionNum;
251 functionNum = regOffset & 0x00000700;
252 pciDevNum = pciDevNum << 11;
253 regOffset = regOffset & 0xff;
254 busNum = busNum << 16;
255 if (pciDevNum == SELF) { /* This board */
256 DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
258 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
261 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
262 GT_REG_WRITE (pci_configuration_data[host], data);
266 /********************************************************************
267 * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
268 * the agent target locate on another PCI bus.
269 * - Make sure the GT is configured as a master
270 * before reading from another device on the PCI.
271 * - The function takes care of Big/Little endian
273 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
274 * spec). (configuration register offset.)
275 * pciDevNum: The device number needs to be addressed.
276 * busNum: the Bus number where the agent is place.
277 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
278 * cause register to make sure the data is valid
280 * Configuration Address 0xCF8:
282 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
283 * |congif|Reserved| Bus |Device|Function|Register|01|
284 * |Enable| |Number|Number| Number | Number | | <=field Name
286 *********************************************************************/
287 unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
288 unsigned int regOffset,
289 unsigned int pciDevNum,
292 unsigned int DataForReg;
294 unsigned int functionNum;
296 functionNum = regOffset & 0x00000700;
297 pciDevNum = pciDevNum << 11;
298 regOffset = regOffset & 0xff;
299 busNum = busNum << 16;
300 if (pciDevNum == SELF) { /* This board */
301 DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
302 } else { /* agent on another bus */
304 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
307 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
308 GT_REG_READ (pci_configuration_data[host], &data);
313 /********************************************************************
314 * pciGetRegOffset - Gets the register offset for this region config.
316 * INPUT: Bus, Region - The bus and region we ask for its base address.
318 * RETURNS: PCI register base address
319 *********************************************************************/
320 static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
326 return PCI_0I_O_LOW_DECODE_ADDRESS;
328 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
330 return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
332 return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
334 return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
339 return PCI_1I_O_LOW_DECODE_ADDRESS;
341 return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
343 return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
345 return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
347 return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
350 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
353 static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
359 return PCI_0I_O_ADDRESS_REMAP;
361 return PCI_0MEMORY0_ADDRESS_REMAP;
363 return PCI_0MEMORY1_ADDRESS_REMAP;
365 return PCI_0MEMORY2_ADDRESS_REMAP;
367 return PCI_0MEMORY3_ADDRESS_REMAP;
372 return PCI_1I_O_ADDRESS_REMAP;
374 return PCI_1MEMORY0_ADDRESS_REMAP;
376 return PCI_1MEMORY1_ADDRESS_REMAP;
378 return PCI_1MEMORY2_ADDRESS_REMAP;
380 return PCI_1MEMORY3_ADDRESS_REMAP;
383 return PCI_0MEMORY0_ADDRESS_REMAP;
386 /********************************************************************
387 * pciGetBaseAddress - Gets the base address of a PCI.
388 * - If the PCI size is 0 then this base address has no meaning!!!
391 * INPUT: Bus, Region - The bus and region we ask for its base address.
393 * RETURNS: PCI base address.
394 *********************************************************************/
395 unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
397 unsigned int regBase;
399 unsigned int regOffset = pciGetRegOffset (host, region);
401 GT_REG_READ (regOffset, ®Base);
402 GT_REG_READ (regOffset + 8, ®End);
404 if (regEnd <= regBase)
405 return 0xffffffff; /* ERROR !!! */
407 regBase = regBase << 16;
411 bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
412 unsigned int bankBase, unsigned int bankLength)
414 unsigned int low = 0xfff;
415 unsigned int high = 0x0;
416 unsigned int regOffset = pciGetRegOffset (host, region);
417 unsigned int remapOffset = pciGetRemapOffset (host, region);
419 if (bankLength != 0) {
420 low = (bankBase >> 16) & 0xffff;
421 high = ((bankBase + bankLength) >> 16) - 1;
424 GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
425 GT_REG_WRITE (regOffset + 8, high);
427 if (bankLength != 0) { /* must do AFTER writing maps */
428 GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
429 dont support upper 32
435 unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
438 unsigned int regOffset = pciGetRegOffset (host, region);
440 GT_REG_READ (regOffset, &low);
441 return (low & 0xffff) << 16;
444 unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
446 unsigned int low, high;
447 unsigned int regOffset = pciGetRegOffset (host, region);
449 GT_REG_READ (regOffset, &low);
450 GT_REG_READ (regOffset + 8, &high);
451 return ((high & 0xffff) + 1) << 16;
455 /* ronen - 7/Dec/03*/
456 /********************************************************************
457 * gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
458 * Inputs: one of the PCI BAR
459 *********************************************************************/
460 void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
462 RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
465 void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
467 SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
470 /********************************************************************
471 * pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
473 * Inputs: base and size of PCI SCS
474 *********************************************************************/
475 void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
476 unsigned int pciDramBase, unsigned int pciDramSize)
478 /*ronen different function for 3rd bank. */
479 unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
481 pciDramBase = pciDramBase & 0xfffff000;
482 pciDramBase = pciDramBase | (pciReadConfigReg (host,
483 PCI_SCS_0_BASE_ADDRESS
486 pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
488 if (pciDramSize == 0)
490 GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
491 gtPciEnableInternalBAR (host, bank);
494 /********************************************************************
495 * pciSetRegionFeatures - This function modifys one of the 8 regions with
496 * feature bits given as an input.
497 * - Be advised to check the spec before modifying them.
498 * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
499 * unsigned int features - See file: pci.h there are defintion for those
501 * unsigned int baseAddress - The region base Address.
502 * unsigned int topAddress - The region top Address.
503 * Returns: false if one of the parameters is erroneous true otherwise.
504 *********************************************************************/
505 bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
506 unsigned int features, unsigned int baseAddress,
507 unsigned int regionLength)
509 unsigned int accessLow;
510 unsigned int accessHigh;
511 unsigned int accessTop = baseAddress + regionLength;
513 if (regionLength == 0) { /* close the region. */
514 pciDisableAccessRegion (host, region);
517 /* base Address is store is bits [11:0] */
518 accessLow = (baseAddress & 0xfff00000) >> 20;
519 /* All the features are update according to the defines in pci.h (to be on
520 the safe side we disable bits: [11:0] */
521 accessLow = accessLow | (features & 0xfffff000);
522 /* write to the Low Access Region register */
523 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
526 accessHigh = (accessTop & 0xfff00000) >> 20;
528 /* write to the High Access Region register */
529 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
534 /********************************************************************
535 * pciDisableAccessRegion - Disable The given Region by writing MAX size
536 * to its low Address and MIN size to its high Address.
538 * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
540 *********************************************************************/
541 void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
543 /* writing back the registers default values. */
544 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
546 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
549 /********************************************************************
550 * pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
554 *********************************************************************/
555 bool pciArbiterEnable (PCI_HOST host)
557 unsigned int regData;
559 GT_REG_READ (pci_arbiter_control[host], ®Data);
560 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
564 /********************************************************************
565 * pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
569 *********************************************************************/
570 bool pciArbiterDisable (PCI_HOST host)
572 unsigned int regData;
574 GT_REG_READ (pci_arbiter_control[host], ®Data);
575 GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
579 /********************************************************************
580 * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
582 * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
583 * PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
584 * PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
585 * PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
586 * PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
587 * PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
588 * PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
590 *********************************************************************/
591 bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
592 PCI_AGENT_PRIO externalAgent0,
593 PCI_AGENT_PRIO externalAgent1,
594 PCI_AGENT_PRIO externalAgent2,
595 PCI_AGENT_PRIO externalAgent3,
596 PCI_AGENT_PRIO externalAgent4,
597 PCI_AGENT_PRIO externalAgent5)
599 unsigned int regData;
600 unsigned int writeData;
602 GT_REG_READ (pci_arbiter_control[host], ®Data);
603 writeData = (internalAgent << 7) + (externalAgent0 << 8) +
604 (externalAgent1 << 9) + (externalAgent2 << 10) +
605 (externalAgent3 << 11) + (externalAgent4 << 12) +
606 (externalAgent5 << 13);
607 regData = (regData & 0xffffc07f) | writeData;
608 GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
612 /********************************************************************
613 * pciParkingDisable - Park on last option disable, with this function you can
614 * disable the park on last mechanism for each agent.
615 * disabling this option for all agents results parking
616 * on the internal master.
618 * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
619 * PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
620 * PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
621 * PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
622 * PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
623 * PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
624 * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
626 *********************************************************************/
627 bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
628 PCI_AGENT_PARK externalAgent0,
629 PCI_AGENT_PARK externalAgent1,
630 PCI_AGENT_PARK externalAgent2,
631 PCI_AGENT_PARK externalAgent3,
632 PCI_AGENT_PARK externalAgent4,
633 PCI_AGENT_PARK externalAgent5)
635 unsigned int regData;
636 unsigned int writeData;
638 GT_REG_READ (pci_arbiter_control[host], ®Data);
639 writeData = (internalAgent << 14) + (externalAgent0 << 15) +
640 (externalAgent1 << 16) + (externalAgent2 << 17) +
641 (externalAgent3 << 18) + (externalAgent4 << 19) +
642 (externalAgent5 << 20);
643 regData = (regData & ~(0x7f << 14)) | writeData;
644 GT_REG_WRITE (pci_arbiter_control[host], regData);
648 /********************************************************************
649 * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
650 * respond to grant assertion within a window specified in
651 * the input value: 'brokenValue'.
653 * Inputs: unsigned char brokenValue - A value which limits the Master to hold the
654 * grant without asserting frame.
655 * Returns: Error for illegal broken value otherwise true.
656 *********************************************************************/
657 bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
660 unsigned int regData;
662 if (brokenValue > 0xf)
663 return false; /* brokenValue must be 4 bit */
664 data = brokenValue << 3;
665 GT_REG_READ (pci_arbiter_control[host], ®Data);
666 regData = (regData & 0xffffff87) | data;
667 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
671 /********************************************************************
672 * pciDisableBrokenAgentDetection - This function disable the Broken agent
673 * Detection mechanism.
674 * NOTE: This operation may cause a dead lock on the
679 *********************************************************************/
680 bool pciDisableBrokenAgentDetection (PCI_HOST host)
682 unsigned int regData;
684 GT_REG_READ (pci_arbiter_control[host], ®Data);
685 regData = regData & 0xfffffffd;
686 GT_REG_WRITE (pci_arbiter_control[host], regData);
690 /********************************************************************
691 * pciP2PConfig - This function set the PCI_n P2P configurate.
692 * For more information on the P2P read PCI spec.
694 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
696 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
698 * unsigned int busNum - The CPI bus number to which the PCI interface
700 * unsigned int devNum - The PCI interface's device number.
703 *********************************************************************/
704 bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
705 unsigned int SecondBusHigh,
706 unsigned int busNum, unsigned int devNum)
708 unsigned int regData;
710 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
711 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
712 GT_REG_WRITE (pci_p2p_configuration[host], regData);
716 /********************************************************************
717 * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
718 * supports Cache Coherency in the PCI_n interface.
719 * Inputs: region - One of the four regions.
720 * snoopType - There is four optional Types:
722 * 2. Snoop to WT region.
723 * 3. Snoop to WB region.
724 * 4. Snoop & Invalidate to WB region.
725 * baseAddress - Base Address of this region.
726 * regionLength - Region length.
727 * Returns: false if one of the parameters is wrong otherwise return true.
728 *********************************************************************/
729 bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
730 PCI_SNOOP_TYPE snoopType,
731 unsigned int baseAddress,
732 unsigned int regionLength)
734 unsigned int snoopXbaseAddress;
735 unsigned int snoopXtopAddress;
737 unsigned int snoopHigh = baseAddress + regionLength;
739 if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
742 pci_snoop_control_base_0_low[host] + 0x10 * region;
743 snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
744 if (regionLength == 0) { /* closing the region */
745 GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
746 GT_REG_WRITE (snoopXtopAddress, 0);
749 baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
750 data = (baseAddress >> 20) | snoopType << 12;
751 GT_REG_WRITE (snoopXbaseAddress, data);
752 snoopHigh = (snoopHigh & 0xfff00000) >> 20;
753 GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
757 static int gt_read_config_dword (struct pci_controller *hose,
758 pci_dev_t dev, int offset, u32 * value)
760 int bus = PCI_BUS (dev);
762 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
763 *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
766 *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
774 static int gt_write_config_dword (struct pci_controller *hose,
775 pci_dev_t dev, int offset, u32 value)
777 int bus = PCI_BUS (dev);
779 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
780 pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
781 PCI_DEV (dev), value);
783 pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
784 offset, PCI_DEV (dev), bus,
791 static void gt_setup_ide (struct pci_controller *hose,
792 pci_dev_t dev, struct pci_config_table *entry)
794 static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
795 u32 bar_response, bar_value;
798 for (bar = 0; bar < 6; bar++) {
799 /*ronen different function for 3rd bank. */
800 unsigned int offset =
801 (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
803 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
805 pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
808 pciauto_region_allocate (bar_response &
809 PCI_BASE_ADDRESS_SPACE_IO ? hose->
810 pci_io : hose->pci_mem, ide_bar[bar],
813 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
819 /* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
820 /* and is curently not called *. */
822 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
824 unsigned char pin, irq;
826 pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
828 if (pin == 1) { /* only allow INT A */
829 irq = pci_irq_swizzle[(PCI_HOST) hose->
830 cfg_addr][PCI_DEV (dev)];
832 pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
837 struct pci_config_table gt_config_table[] = {
838 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
839 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
844 struct pci_controller pci0_hose = {
845 /* fixup_irq: gt_fixup_irq, */
846 config_table:gt_config_table,
849 struct pci_controller pci1_hose = {
850 /* fixup_irq: gt_fixup_irq, */
851 config_table:gt_config_table,
854 void pci_init_board (void)
856 unsigned int command;
857 #ifdef CONFIG_PCI_PNP
862 gt_pci_bus_mode_display (PCI_HOST0);
865 pci0_hose.first_busno = 0;
866 pci0_hose.last_busno = 0xff;
867 local_buses[0] = pci0_hose.first_busno;
869 /* PCI memory space */
870 pci_set_region (pci0_hose.regions + 0,
871 CFG_PCI0_0_MEM_SPACE,
872 CFG_PCI0_0_MEM_SPACE,
873 CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
876 pci_set_region (pci0_hose.regions + 1,
877 CFG_PCI0_IO_SPACE_PCI,
878 CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
880 pci_set_ops (&pci0_hose,
881 pci_hose_read_config_byte_via_dword,
882 pci_hose_read_config_word_via_dword,
883 gt_read_config_dword,
884 pci_hose_write_config_byte_via_dword,
885 pci_hose_write_config_word_via_dword,
886 gt_write_config_dword);
887 pci0_hose.region_count = 2;
889 pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
891 pci_register_hose (&pci0_hose);
892 pciArbiterEnable (PCI_HOST0);
893 pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
894 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
895 command |= PCI_COMMAND_MASTER;
896 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
897 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
898 command |= PCI_COMMAND_MEMORY;
899 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
901 #ifdef CONFIG_PCI_PNP
902 pciauto_config_init(&pci0_hose);
903 pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
905 #ifdef CONFIG_PCI_SCAN_SHOW
906 printf("PCI: Bus Dev VenId DevId Class Int\n");
908 pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
911 gt_pci_bus_mode_display (PCI_HOST1);
913 pci1_hose.first_busno = pci0_hose.last_busno + 1;
914 pci1_hose.last_busno = 0xff;
915 pci1_hose.current_busno = pci1_hose.first_busno;
916 local_buses[1] = pci1_hose.first_busno;
918 /* PCI memory space */
919 pci_set_region (pci1_hose.regions + 0,
920 CFG_PCI1_0_MEM_SPACE,
921 CFG_PCI1_0_MEM_SPACE,
922 CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
925 pci_set_region (pci1_hose.regions + 1,
926 CFG_PCI1_IO_SPACE_PCI,
927 CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
929 pci_set_ops (&pci1_hose,
930 pci_hose_read_config_byte_via_dword,
931 pci_hose_read_config_word_via_dword,
932 gt_read_config_dword,
933 pci_hose_write_config_byte_via_dword,
934 pci_hose_write_config_word_via_dword,
935 gt_write_config_dword);
937 pci1_hose.region_count = 2;
939 pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
941 pci_register_hose (&pci1_hose);
943 pciArbiterEnable (PCI_HOST1);
944 pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
946 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
947 command |= PCI_COMMAND_MASTER;
948 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
950 #ifdef CONFIG_PCI_PNP
951 pciauto_config_init(&pci1_hose);
952 pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
954 pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
956 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
957 command |= PCI_COMMAND_MEMORY;
958 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
961 #endif /* of CONFIG_PCI */