3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* PCI.c - PCI functions */
31 #include "../../Marvell/include/pci.h"
34 #undef IDE_SET_NATIVE_MODE
35 static unsigned int local_buses[] = { 0, 0 };
37 static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
38 {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
39 {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
42 #ifdef CONFIG_USE_CPCIDVI
48 static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
52 static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
53 static void gt_pci_bus_mode_display (PCI_HOST host)
58 mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
61 printf ("PCI %d bus mode: Conventional PCI\n", host);
64 printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
67 printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
70 printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
73 printf ("Unknown BUS %d\n", mode);
78 static const unsigned int pci_p2p_configuration_reg[] = {
79 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
82 static const unsigned int pci_configuration_address[] = {
83 PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
86 static const unsigned int pci_configuration_data[] = {
87 PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
88 PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
91 static const unsigned int pci_error_cause_reg[] = {
92 PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
95 static const unsigned int pci_arbiter_control[] = {
96 PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
99 static const unsigned int pci_address_space_en[] = {
100 PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
103 static const unsigned int pci_snoop_control_base_0_low[] = {
104 PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
106 static const unsigned int pci_snoop_control_top_0[] = {
107 PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
110 static const unsigned int pci_access_control_base_0_low[] = {
111 PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
113 static const unsigned int pci_access_control_top_0[] = {
114 PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
117 static const unsigned int pci_scs_bank_size[2][4] = {
118 {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
119 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
120 {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
121 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
124 static const unsigned int pci_p2p_configuration[] = {
125 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
129 /********************************************************************
130 * pciWriteConfigReg - Write to a PCI configuration register
131 * - Make sure the GT is configured as a master before writing
132 * to another device on the PCI.
133 * - The function takes care of Big/Little endian conversion.
136 * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
137 * (or any other PCI device spec)
138 * pciDevNum: The device number needs to be addressed.
140 * Configuration Address 0xCF8:
142 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
143 * |congif|Reserved| Bus |Device|Function|Register|00|
144 * |Enable| |Number|Number| Number | Number | | <=field Name
146 *********************************************************************/
147 void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
148 unsigned int pciDevNum, unsigned int data)
150 volatile unsigned int DataForAddrReg;
151 unsigned int functionNum;
152 unsigned int busNum = 0;
155 if (pciDevNum > 32) /* illegal device Number */
157 if (pciDevNum == SELF) { /* configure our configuration space. */
159 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
161 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
164 functionNum = regOffset & 0x00000700;
165 pciDevNum = pciDevNum << 11;
166 regOffset = regOffset & 0xfc;
168 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
169 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
170 GT_REG_READ (pci_configuration_address[host], &addr);
171 if (addr != DataForAddrReg)
173 GT_REG_WRITE (pci_configuration_data[host], data);
176 /********************************************************************
177 * pciReadConfigReg - Read from a PCI0 configuration register
178 * - Make sure the GT is configured as a master before reading
179 * from another device on the PCI.
180 * - The function takes care of Big/Little endian conversion.
181 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
183 * pciDevNum: The device number needs to be addressed.
184 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
185 * cause register to make sure the data is valid
187 * Configuration Address 0xCF8:
189 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
190 * |congif|Reserved| Bus |Device|Function|Register|00|
191 * |Enable| |Number|Number| Number | Number | | <=field Name
193 *********************************************************************/
194 unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
195 unsigned int pciDevNum)
197 volatile unsigned int DataForAddrReg;
199 unsigned int functionNum;
200 unsigned int busNum = 0;
202 if (pciDevNum > 32) /* illegal device Number */
204 if (pciDevNum == SELF) { /* configure our configuration space. */
206 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
208 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
211 functionNum = regOffset & 0x00000700;
212 pciDevNum = pciDevNum << 11;
213 regOffset = regOffset & 0xfc;
215 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
216 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
217 GT_REG_READ (pci_configuration_address[host], &data);
218 if (data != DataForAddrReg)
220 GT_REG_READ (pci_configuration_data[host], &data);
224 /********************************************************************
225 * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
226 * the agent is placed on another Bus. For more
227 * information read P2P in the PCI spec.
229 * Inputs: unsigned int regOffset - The register offset as it apears in the
230 * GT spec (or any other PCI device spec).
231 * unsigned int pciDevNum - The device number needs to be addressed.
232 * unsigned int busNum - On which bus does the Target agent connect
234 * unsigned int data - data to be written.
236 * Configuration Address 0xCF8:
238 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
239 * |congif|Reserved| Bus |Device|Function|Register|01|
240 * |Enable| |Number|Number| Number | Number | | <=field Name
242 * The configuration Address is configure as type-I (bits[1:0] = '01') due to
243 * PCI spec referring to P2P.
245 *********************************************************************/
246 void pciOverBridgeWriteConfigReg (PCI_HOST host,
247 unsigned int regOffset,
248 unsigned int pciDevNum,
249 unsigned int busNum, unsigned int data)
251 unsigned int DataForReg;
252 unsigned int functionNum;
254 functionNum = regOffset & 0x00000700;
255 pciDevNum = pciDevNum << 11;
256 regOffset = regOffset & 0xff;
257 busNum = busNum << 16;
258 if (pciDevNum == SELF) { /* This board */
259 DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
261 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
264 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
265 GT_REG_WRITE (pci_configuration_data[host], data);
269 /********************************************************************
270 * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
271 * the agent target locate on another PCI bus.
272 * - Make sure the GT is configured as a master
273 * before reading from another device on the PCI.
274 * - The function takes care of Big/Little endian
276 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
277 * spec). (configuration register offset.)
278 * pciDevNum: The device number needs to be addressed.
279 * busNum: the Bus number where the agent is place.
280 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
281 * cause register to make sure the data is valid
283 * Configuration Address 0xCF8:
285 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
286 * |congif|Reserved| Bus |Device|Function|Register|01|
287 * |Enable| |Number|Number| Number | Number | | <=field Name
289 *********************************************************************/
290 unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
291 unsigned int regOffset,
292 unsigned int pciDevNum,
295 unsigned int DataForReg;
297 unsigned int functionNum;
299 functionNum = regOffset & 0x00000700;
300 pciDevNum = pciDevNum << 11;
301 regOffset = regOffset & 0xff;
302 busNum = busNum << 16;
303 if (pciDevNum == SELF) { /* This board */
304 DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
305 } else { /* agent on another bus */
307 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
310 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
311 GT_REG_READ (pci_configuration_data[host], &data);
316 /********************************************************************
317 * pciGetRegOffset - Gets the register offset for this region config.
319 * INPUT: Bus, Region - The bus and region we ask for its base address.
321 * RETURNS: PCI register base address
322 *********************************************************************/
323 static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
329 return PCI_0I_O_LOW_DECODE_ADDRESS;
331 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
333 return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
335 return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
337 return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
342 return PCI_1I_O_LOW_DECODE_ADDRESS;
344 return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
346 return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
348 return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
350 return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
353 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
356 static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
362 return PCI_0I_O_ADDRESS_REMAP;
364 return PCI_0MEMORY0_ADDRESS_REMAP;
366 return PCI_0MEMORY1_ADDRESS_REMAP;
368 return PCI_0MEMORY2_ADDRESS_REMAP;
370 return PCI_0MEMORY3_ADDRESS_REMAP;
375 return PCI_1I_O_ADDRESS_REMAP;
377 return PCI_1MEMORY0_ADDRESS_REMAP;
379 return PCI_1MEMORY1_ADDRESS_REMAP;
381 return PCI_1MEMORY2_ADDRESS_REMAP;
383 return PCI_1MEMORY3_ADDRESS_REMAP;
386 return PCI_0MEMORY0_ADDRESS_REMAP;
389 /********************************************************************
390 * pciGetBaseAddress - Gets the base address of a PCI.
391 * - If the PCI size is 0 then this base address has no meaning!!!
394 * INPUT: Bus, Region - The bus and region we ask for its base address.
396 * RETURNS: PCI base address.
397 *********************************************************************/
398 unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
400 unsigned int regBase;
402 unsigned int regOffset = pciGetRegOffset (host, region);
404 GT_REG_READ (regOffset, ®Base);
405 GT_REG_READ (regOffset + 8, ®End);
407 if (regEnd <= regBase)
408 return 0xffffffff; /* ERROR !!! */
410 regBase = regBase << 16;
414 bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
415 unsigned int bankBase, unsigned int bankLength)
417 unsigned int low = 0xfff;
418 unsigned int high = 0x0;
419 unsigned int regOffset = pciGetRegOffset (host, region);
420 unsigned int remapOffset = pciGetRemapOffset (host, region);
422 if (bankLength != 0) {
423 low = (bankBase >> 16) & 0xffff;
424 high = ((bankBase + bankLength) >> 16) - 1;
427 GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
428 GT_REG_WRITE (regOffset + 8, high);
430 if (bankLength != 0) { /* must do AFTER writing maps */
431 GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
432 dont support upper 32
438 unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
441 unsigned int regOffset = pciGetRegOffset (host, region);
443 GT_REG_READ (regOffset, &low);
444 return (low & 0xffff) << 16;
447 unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
449 unsigned int low, high;
450 unsigned int regOffset = pciGetRegOffset (host, region);
452 GT_REG_READ (regOffset, &low);
453 GT_REG_READ (regOffset + 8, &high);
454 return ((high & 0xffff) + 1) << 16;
458 /* ronen - 7/Dec/03*/
459 /********************************************************************
460 * gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
461 * Inputs: one of the PCI BAR
462 *********************************************************************/
463 void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
465 RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
468 void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
470 SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
473 /********************************************************************
474 * pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
476 * Inputs: base and size of PCI SCS
477 *********************************************************************/
478 void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
479 unsigned int pciDramBase, unsigned int pciDramSize)
481 /*ronen different function for 3rd bank. */
482 unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
484 pciDramBase = pciDramBase & 0xfffff000;
485 pciDramBase = pciDramBase | (pciReadConfigReg (host,
486 PCI_SCS_0_BASE_ADDRESS
489 pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
491 if (pciDramSize == 0)
493 GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
494 gtPciEnableInternalBAR (host, bank);
497 /********************************************************************
498 * pciSetRegionFeatures - This function modifys one of the 8 regions with
499 * feature bits given as an input.
500 * - Be advised to check the spec before modifying them.
501 * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
502 * unsigned int features - See file: pci.h there are defintion for those
504 * unsigned int baseAddress - The region base Address.
505 * unsigned int topAddress - The region top Address.
506 * Returns: false if one of the parameters is erroneous true otherwise.
507 *********************************************************************/
508 bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
509 unsigned int features, unsigned int baseAddress,
510 unsigned int regionLength)
512 unsigned int accessLow;
513 unsigned int accessHigh;
514 unsigned int accessTop = baseAddress + regionLength;
516 if (regionLength == 0) { /* close the region. */
517 pciDisableAccessRegion (host, region);
520 /* base Address is store is bits [11:0] */
521 accessLow = (baseAddress & 0xfff00000) >> 20;
522 /* All the features are update according to the defines in pci.h (to be on
523 the safe side we disable bits: [11:0] */
524 accessLow = accessLow | (features & 0xfffff000);
525 /* write to the Low Access Region register */
526 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
529 accessHigh = (accessTop & 0xfff00000) >> 20;
531 /* write to the High Access Region register */
532 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
537 /********************************************************************
538 * pciDisableAccessRegion - Disable The given Region by writing MAX size
539 * to its low Address and MIN size to its high Address.
541 * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
543 *********************************************************************/
544 void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
546 /* writing back the registers default values. */
547 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
549 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
552 /********************************************************************
553 * pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
557 *********************************************************************/
558 bool pciArbiterEnable (PCI_HOST host)
560 unsigned int regData;
562 GT_REG_READ (pci_arbiter_control[host], ®Data);
563 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
567 /********************************************************************
568 * pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
572 *********************************************************************/
573 bool pciArbiterDisable (PCI_HOST host)
575 unsigned int regData;
577 GT_REG_READ (pci_arbiter_control[host], ®Data);
578 GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
582 /********************************************************************
583 * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
585 * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
586 * PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
587 * PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
588 * PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
589 * PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
590 * PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
591 * PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
593 *********************************************************************/
594 bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
595 PCI_AGENT_PRIO externalAgent0,
596 PCI_AGENT_PRIO externalAgent1,
597 PCI_AGENT_PRIO externalAgent2,
598 PCI_AGENT_PRIO externalAgent3,
599 PCI_AGENT_PRIO externalAgent4,
600 PCI_AGENT_PRIO externalAgent5)
602 unsigned int regData;
603 unsigned int writeData;
605 GT_REG_READ (pci_arbiter_control[host], ®Data);
606 writeData = (internalAgent << 7) + (externalAgent0 << 8) +
607 (externalAgent1 << 9) + (externalAgent2 << 10) +
608 (externalAgent3 << 11) + (externalAgent4 << 12) +
609 (externalAgent5 << 13);
610 regData = (regData & 0xffffc07f) | writeData;
611 GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
615 /********************************************************************
616 * pciParkingDisable - Park on last option disable, with this function you can
617 * disable the park on last mechanism for each agent.
618 * disabling this option for all agents results parking
619 * on the internal master.
621 * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
622 * PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
623 * PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
624 * PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
625 * PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
626 * PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
627 * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
629 *********************************************************************/
630 bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
631 PCI_AGENT_PARK externalAgent0,
632 PCI_AGENT_PARK externalAgent1,
633 PCI_AGENT_PARK externalAgent2,
634 PCI_AGENT_PARK externalAgent3,
635 PCI_AGENT_PARK externalAgent4,
636 PCI_AGENT_PARK externalAgent5)
638 unsigned int regData;
639 unsigned int writeData;
641 GT_REG_READ (pci_arbiter_control[host], ®Data);
642 writeData = (internalAgent << 14) + (externalAgent0 << 15) +
643 (externalAgent1 << 16) + (externalAgent2 << 17) +
644 (externalAgent3 << 18) + (externalAgent4 << 19) +
645 (externalAgent5 << 20);
646 regData = (regData & ~(0x7f << 14)) | writeData;
647 GT_REG_WRITE (pci_arbiter_control[host], regData);
651 /********************************************************************
652 * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
653 * respond to grant assertion within a window specified in
654 * the input value: 'brokenValue'.
656 * Inputs: unsigned char brokenValue - A value which limits the Master to hold the
657 * grant without asserting frame.
658 * Returns: Error for illegal broken value otherwise true.
659 *********************************************************************/
660 bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
663 unsigned int regData;
665 if (brokenValue > 0xf)
666 return false; /* brokenValue must be 4 bit */
667 data = brokenValue << 3;
668 GT_REG_READ (pci_arbiter_control[host], ®Data);
669 regData = (regData & 0xffffff87) | data;
670 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
674 /********************************************************************
675 * pciDisableBrokenAgentDetection - This function disable the Broken agent
676 * Detection mechanism.
677 * NOTE: This operation may cause a dead lock on the
682 *********************************************************************/
683 bool pciDisableBrokenAgentDetection (PCI_HOST host)
685 unsigned int regData;
687 GT_REG_READ (pci_arbiter_control[host], ®Data);
688 regData = regData & 0xfffffffd;
689 GT_REG_WRITE (pci_arbiter_control[host], regData);
693 /********************************************************************
694 * pciP2PConfig - This function set the PCI_n P2P configurate.
695 * For more information on the P2P read PCI spec.
697 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
699 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
701 * unsigned int busNum - The CPI bus number to which the PCI interface
703 * unsigned int devNum - The PCI interface's device number.
706 *********************************************************************/
707 bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
708 unsigned int SecondBusHigh,
709 unsigned int busNum, unsigned int devNum)
711 unsigned int regData;
713 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
714 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
715 GT_REG_WRITE (pci_p2p_configuration[host], regData);
719 /********************************************************************
720 * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
721 * supports Cache Coherency in the PCI_n interface.
722 * Inputs: region - One of the four regions.
723 * snoopType - There is four optional Types:
725 * 2. Snoop to WT region.
726 * 3. Snoop to WB region.
727 * 4. Snoop & Invalidate to WB region.
728 * baseAddress - Base Address of this region.
729 * regionLength - Region length.
730 * Returns: false if one of the parameters is wrong otherwise return true.
731 *********************************************************************/
732 bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
733 PCI_SNOOP_TYPE snoopType,
734 unsigned int baseAddress,
735 unsigned int regionLength)
737 unsigned int snoopXbaseAddress;
738 unsigned int snoopXtopAddress;
740 unsigned int snoopHigh = baseAddress + regionLength;
742 if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
745 pci_snoop_control_base_0_low[host] + 0x10 * region;
746 snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
747 if (regionLength == 0) { /* closing the region */
748 GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
749 GT_REG_WRITE (snoopXtopAddress, 0);
752 baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
753 data = (baseAddress >> 20) | snoopType << 12;
754 GT_REG_WRITE (snoopXbaseAddress, data);
755 snoopHigh = (snoopHigh & 0xfff00000) >> 20;
756 GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
760 static int gt_read_config_dword (struct pci_controller *hose,
761 pci_dev_t dev, int offset, u32 * value)
763 int bus = PCI_BUS (dev);
765 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
766 *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
767 offset | (PCI_FUNC(dev) << 8),
770 *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr,
771 offset | (PCI_FUNC(dev) << 8),
778 static int gt_write_config_dword (struct pci_controller *hose,
779 pci_dev_t dev, int offset, u32 value)
781 int bus = PCI_BUS (dev);
783 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
784 pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
785 offset | (PCI_FUNC(dev) << 8),
786 PCI_DEV (dev), value);
788 pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
789 offset | (PCI_FUNC(dev) << 8),
797 static void gt_setup_ide (struct pci_controller *hose,
798 pci_dev_t dev, struct pci_config_table *entry)
800 static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
801 u32 bar_response, bar_value;
804 if (CPCI750_SLAVE_TEST != 0)
807 for (bar = 0; bar < 6; bar++) {
808 /*ronen different function for 3rd bank. */
809 unsigned int offset =
810 (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
812 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
814 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
817 pciauto_region_allocate (bar_response &
818 PCI_BASE_ADDRESS_SPACE_IO ? hose->
819 pci_io : hose->pci_mem, ide_bar[bar],
822 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
827 #ifdef CONFIG_USE_CPCIDVI
828 static void gt_setup_cpcidvi (struct pci_controller *hose,
829 pci_dev_t dev, struct pci_config_table *entry)
831 u32 bar_value, pci_response;
833 if (CPCI750_SLAVE_TEST != 0)
836 pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
837 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
838 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
839 pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
840 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
841 pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
842 pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
843 pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
844 gt_cpcidvi_rom.base = bar_value & 0xffffff00;
845 gt_cpcidvi_rom.init = 1;
848 unsigned char gt_cpcidvi_in8(unsigned int offset)
852 if (gt_cpcidvi_rom.init == 0) {
855 data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
859 void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
863 if (gt_cpcidvi_rom.init == 0) {
867 off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
873 /* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
874 /* and is curently not called *. */
876 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
878 unsigned char pin, irq;
880 pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
882 if (pin == 1) { /* only allow INT A */
883 irq = pci_irq_swizzle[(PCI_HOST) hose->
884 cfg_addr][PCI_DEV (dev)];
886 pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
891 struct pci_config_table gt_config_table[] = {
892 #ifdef CONFIG_USE_CPCIDVI
893 {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
894 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
896 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
897 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
901 struct pci_controller pci0_hose = {
902 /* fixup_irq: gt_fixup_irq, */
903 config_table:gt_config_table,
906 struct pci_controller pci1_hose = {
907 /* fixup_irq: gt_fixup_irq, */
908 config_table:gt_config_table,
911 void pci_init_board (void)
913 unsigned int command;
915 #ifdef CONFIG_PCI_PNP
919 gt_pci_bus_mode_display (PCI_HOST0);
921 #ifdef CONFIG_USE_CPCIDVI
922 gt_cpcidvi_rom.init = 0;
923 gt_cpcidvi_rom.base = 0;
926 slave = CPCI750_SLAVE_TEST;
928 pci0_hose.config_table = gt_config_table;
929 pci1_hose.config_table = gt_config_table;
931 #ifdef CONFIG_USE_CPCIDVI
932 gt_config_table[0].config_device = gt_setup_cpcidvi;
934 gt_config_table[1].config_device = gt_setup_ide;
936 pci0_hose.first_busno = 0;
937 pci0_hose.last_busno = 0xff;
938 local_buses[0] = pci0_hose.first_busno;
940 /* PCI memory space */
941 pci_set_region (pci0_hose.regions + 0,
942 CONFIG_SYS_PCI0_0_MEM_SPACE,
943 CONFIG_SYS_PCI0_0_MEM_SPACE,
944 CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
947 pci_set_region (pci0_hose.regions + 1,
948 CONFIG_SYS_PCI0_IO_SPACE_PCI,
949 CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
951 pci_set_ops (&pci0_hose,
952 pci_hose_read_config_byte_via_dword,
953 pci_hose_read_config_word_via_dword,
954 gt_read_config_dword,
955 pci_hose_write_config_byte_via_dword,
956 pci_hose_write_config_word_via_dword,
957 gt_write_config_dword);
958 pci0_hose.region_count = 2;
960 pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
962 pci_register_hose (&pci0_hose);
964 pciArbiterEnable (PCI_HOST0);
965 pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
966 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
967 command |= PCI_COMMAND_MASTER;
968 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
969 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
970 command |= PCI_COMMAND_MEMORY;
971 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
973 #ifdef CONFIG_PCI_PNP
974 pciauto_config_init(&pci0_hose);
975 pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
977 #ifdef CONFIG_PCI_SCAN_SHOW
978 printf("PCI: Bus Dev VenId DevId Class Int\n");
980 pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
981 pci0_hose.first_busno);
984 gt_pci_bus_mode_display (PCI_HOST1);
987 pciArbiterDisable (PCI_HOST0);
988 pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
989 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
990 command |= PCI_COMMAND_MASTER;
991 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
992 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
993 command |= PCI_COMMAND_MEMORY;
994 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
995 pci0_hose.last_busno = pci0_hose.first_busno;
997 pci1_hose.first_busno = pci0_hose.last_busno + 1;
998 pci1_hose.last_busno = 0xff;
999 pci1_hose.current_busno = pci1_hose.first_busno;
1000 local_buses[1] = pci1_hose.first_busno;
1002 /* PCI memory space */
1003 pci_set_region (pci1_hose.regions + 0,
1004 CONFIG_SYS_PCI1_0_MEM_SPACE,
1005 CONFIG_SYS_PCI1_0_MEM_SPACE,
1006 CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
1009 pci_set_region (pci1_hose.regions + 1,
1010 CONFIG_SYS_PCI1_IO_SPACE_PCI,
1011 CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
1013 pci_set_ops (&pci1_hose,
1014 pci_hose_read_config_byte_via_dword,
1015 pci_hose_read_config_word_via_dword,
1016 gt_read_config_dword,
1017 pci_hose_write_config_byte_via_dword,
1018 pci_hose_write_config_word_via_dword,
1019 gt_write_config_dword);
1021 pci1_hose.region_count = 2;
1023 pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
1025 pci_register_hose (&pci1_hose);
1027 pciArbiterEnable (PCI_HOST1);
1028 pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
1030 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
1031 command |= PCI_COMMAND_MASTER;
1032 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
1034 #ifdef CONFIG_PCI_PNP
1035 pciauto_config_init(&pci1_hose);
1036 pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
1038 pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
1040 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
1041 command |= PCI_COMMAND_MEMORY;
1042 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
1045 #endif /* of CONFIG_PCI */