3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /*************************************************************************
9 * adaption for the Marvell DB64360 Board
10 * Ingo Assmus (ingo.assmus@keymile.com)
12 * adaption for the cpci750 Board
13 * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
14 *************************************************************************/
17 /* sdram_init.c - automatic memory sizing */
21 #include "../../Marvell/include/memory.h"
22 #include "../../Marvell/include/pci.h"
23 #include "../../Marvell/include/mv_gen_reg.h"
28 #include "../../Marvell/common/i2c.h"
32 DECLARE_GLOBAL_DATA_PTR;
34 int set_dfcdlInit(void); /* setup delay line of Mv64360 */
36 /* ------------------------------------------------------------------------- */
39 memory_map_bank(unsigned int bankNo,
40 unsigned int bankBase,
41 unsigned int bankLength)
50 printf("mapping bank %d at %08x - %08x\n",
51 bankNo, bankBase, bankBase + bankLength - 1);
53 printf("unmapping bank %d\n", bankNo);
57 memoryMapBank(bankNo, bankBase, bankLength);
60 for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
65 READ_LINE_AGGRESSIVE_PREFETCH |
66 READ_MULTI_AGGRESSIVE_PREFETCH |
70 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
72 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
75 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
83 /* much of this code is based on (or is) the code in the pip405 port */
84 /* thanks go to the authors of said port - Josh */
86 /* structure to store the relevant information about an sdram bank */
87 typedef struct sdram_info {
89 uchar registered, ecc;
96 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
98 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
100 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
101 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
104 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
105 typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
108 /* SDRAM/DDR information struct */
109 typedef struct _gtMemoryDimmInfo {
110 MEMORY_TYPE memoryType;
111 unsigned int numOfRowAddresses;
112 unsigned int numOfColAddresses;
113 unsigned int numOfModuleBanks;
114 unsigned int dataWidth;
115 VOLTAGE_INTERFACE voltageInterface;
116 unsigned int errorCheckType; /* ECC , PARITY.. */
117 unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
118 unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
119 unsigned int minClkDelay;
120 unsigned int burstLengthSupported;
121 unsigned int numOfBanksOnEachDevice;
122 unsigned int suportedCasLatencies;
123 unsigned int RefreshInterval;
124 unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
125 unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
126 MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
127 MAX_CL_SUPPORTED_SD maxClSupported_SD;
128 unsigned int moduleBankDensity;
129 /* module attributes (true for yes) */
130 bool bufferedAddrAndControlInputs;
131 bool registeredAddrAndControlInputs;
133 bool bufferedDQMBinputs;
134 bool registeredDQMBinputs;
135 bool differentialClockInput;
136 bool redundantRowAddressing;
138 /* module general attributes */
139 bool suportedAutoPreCharge;
140 bool suportedPreChargeAll;
141 bool suportedEarlyRasPreCharge;
142 bool suportedWrite1ReadBurst;
143 bool suported5PercentLowVCC;
144 bool suported5PercentUpperVCC;
145 /* module timing parameters */
146 unsigned int minRasToCasDelay;
147 unsigned int minRowActiveRowActiveDelay;
148 unsigned int minRasPulseWidth;
149 unsigned int minRowPrechargeTime; /* measured in ns */
151 int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
152 int addrAndCommandSetupTime; /* (measured in ns/100) */
153 int dataInputSetupTime; /* LoP left of point (measured in ns) */
154 int dataInputHoldTime; /* LoP left of point (measured in ns) */
155 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
156 unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
157 unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
158 unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
159 unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
160 unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
161 unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
163 unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
164 unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
166 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
167 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
169 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
170 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
172 /* Parameters calculated from
173 the extracted DIMM information */
175 unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
176 unsigned int numberOfDevices;
177 uchar drb_size; /* DRAM size in n*64Mbit */
178 uchar slot; /* Slot Number this module is inserted in */
179 uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
181 uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
182 uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
183 uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
184 unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
185 unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
186 unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
187 uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
194 * translate ns.ns/10 coding of SPD timing values
195 * into 10 ps unit values
197 static inline unsigned short
198 NS10to10PS(unsigned char spd_byte)
200 unsigned short ns, ns10;
202 /* isolate upper nibble */
203 ns = (spd_byte >> 4) & 0x0F;
204 /* isolate lower nibble */
205 ns10 = (spd_byte & 0x0F);
207 return(ns*100 + ns10*10);
211 * translate ns coding of SPD timing values
212 * into 10 ps unit values
214 static inline unsigned short
215 NSto10PS(unsigned char spd_byte)
217 return(spd_byte*100);
220 /* This code reads the SPD chip on the sdram and populates
221 * the array which is passed in with the relevant information */
222 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
223 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
225 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
227 unsigned int i, j, density = 1, devicesForErrCheck = 0;
232 unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
233 int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
234 uchar supp_cal, cal_val;
235 ulong memclk, tmemclk;
237 uchar trp_clocks = 0, tras_clocks;
240 memclk = gd->bus_clk;
241 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
243 memset (data, 0, sizeof (data));
248 debug("before i2c read\n");
250 ret = i2c_read (addr, 0, 2, data, 128);
252 debug("after i2c read\n");
254 if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
255 || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
256 || (data[70] != 'b') || (data[71] != 'h')) {
260 if ((ret != 0) && (slot == 0)) {
261 memset (data, 0, sizeof (data));
309 /* zero all the values */
310 memset (dimmInfo, 0, sizeof (*dimmInfo));
312 /* copy the SPD content 1:1 into the dimmInfo structure */
313 for (i = 0; i <= 127; i++) {
314 dimmInfo->spd_raw_data[i] = data[i];
318 debug("No DIMM in slot %d [err = %x]\n", slot, ret);
321 dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
323 #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
325 for (i = 0; i <= 127; i++) {
326 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
332 /* find Manufacturer of Dimm Module */
333 for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
334 dimmInfo->manufactura[i] = data[64 + i];
336 printf ("\nThis RAM-Module is produced by: %s\n",
337 dimmInfo->manufactura);
339 /* find Manul-ID of Dimm Module */
340 for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
341 dimmInfo->modul_id[i] = data[73 + i];
343 printf ("The Module-ID of this RAM-Module is: %s\n",
346 /* find Vendor-Data of Dimm Module */
347 for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
348 dimmInfo->vendor_data[i] = data[99 + i];
350 printf ("Vendor Data of this RAM-Module is: %s\n",
351 dimmInfo->vendor_data);
353 /* find modul_serial_no of Dimm Module */
354 dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
355 printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
356 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
358 /* find Manufac-Data of Dimm Module */
359 dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
360 printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
362 /* find modul_revision of Dimm Module */
363 dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
364 printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
366 /* find manufac_place of Dimm Module */
367 dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
368 printf ("manufac_place of this RAM-Module is: %d\n",
369 dimmInfo->manufac_place);
372 /*------------------------------------------------------------------------------------------------------------------------------*/
373 /* calculate SPD checksum */
374 /*------------------------------------------------------------------------------------------------------------------------------*/
375 #if 0 /* test-only */
378 for (i = 0; i <= 62; i++) {
379 spd_checksum += data[i];
382 if ((spd_checksum & 0xff) != data[63]) {
383 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
388 printf ("SPD Checksum ok!\n");
389 #endif /* test-only */
391 /*------------------------------------------------------------------------------------------------------------------------------*/
392 for (i = 2; i <= 35; i++) {
394 case 2: /* Memory type (DDR / SDRAM) */
395 dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
397 if (dimmInfo->memoryType == 0)
398 debug("Dram_type in slot %d is: SDRAM\n",
400 if (dimmInfo->memoryType == 1)
401 debug("Dram_type in slot %d is: DDRAM\n",
405 /*------------------------------------------------------------------------------------------------------------------------------*/
407 case 3: /* Number Of Row Addresses */
408 dimmInfo->numOfRowAddresses = data[i];
409 debug("Module Number of row addresses: %d\n",
410 dimmInfo->numOfRowAddresses);
412 /*------------------------------------------------------------------------------------------------------------------------------*/
414 case 4: /* Number Of Column Addresses */
415 dimmInfo->numOfColAddresses = data[i];
416 debug("Module Number of col addresses: %d\n",
417 dimmInfo->numOfColAddresses);
419 /*------------------------------------------------------------------------------------------------------------------------------*/
421 case 5: /* Number Of Module Banks */
422 dimmInfo->numOfModuleBanks = data[i];
423 debug("Number of Banks on Mod. : %d\n",
424 dimmInfo->numOfModuleBanks);
426 /*------------------------------------------------------------------------------------------------------------------------------*/
428 case 6: /* Data Width */
429 dimmInfo->dataWidth = data[i];
430 debug("Module Data Width: %d\n",
431 dimmInfo->dataWidth);
433 /*------------------------------------------------------------------------------------------------------------------------------*/
435 case 8: /* Voltage Interface */
438 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
439 debug("Module is TTL_5V_TOLERANT\n");
442 dimmInfo->voltageInterface = LVTTL;
443 debug("Module is LVTTL\n");
446 dimmInfo->voltageInterface = HSTL_1_5V;
447 debug("Module is TTL_5V_TOLERANT\n");
450 dimmInfo->voltageInterface = SSTL_3_3V;
451 debug("Module is HSTL_1_5V\n");
454 dimmInfo->voltageInterface = SSTL_2_5V;
455 debug("Module is SSTL_2_5V\n");
458 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
459 debug("Module is VOLTAGE_UNKNOWN\n");
463 /*------------------------------------------------------------------------------------------------------------------------------*/
465 case 9: /* Minimum Cycle Time At Max CasLatancy */
466 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
467 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
469 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
471 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
472 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
473 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
474 dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
476 dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
478 debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
479 leftOfPoint, rightOfPoint);
481 /*------------------------------------------------------------------------------------------------------------------------------*/
483 case 10: /* Clock To Data Out */
484 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
486 (((data[i] & 0xf0) >> 4) * 10) +
488 leftOfPoint = time_tmp / div;
489 rightOfPoint = time_tmp % div;
490 dimmInfo->clockToDataOut_LoP = leftOfPoint;
491 dimmInfo->clockToDataOut_RoP = rightOfPoint;
492 debug("Clock To Data Out: %d.%2d [ns]\n",
493 leftOfPoint, rightOfPoint);
494 /*dimmInfo->clockToDataOut */
496 /*------------------------------------------------------------------------------------------------------------------------------*/
498 #ifdef CONFIG_MV64360_ECC
499 case 11: /* Error Check Type */
500 dimmInfo->errorCheckType = data[i];
501 debug("Error Check Type (0=NONE): %d\n",
502 dimmInfo->errorCheckType);
504 #endif /* of ifdef CONFIG_MV64360_ECC */
505 /*------------------------------------------------------------------------------------------------------------------------------*/
507 case 12: /* Refresh Interval */
508 dimmInfo->RefreshInterval = data[i];
509 debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
510 dimmInfo->RefreshInterval);
512 /*------------------------------------------------------------------------------------------------------------------------------*/
514 case 13: /* Sdram Width */
515 dimmInfo->sdramWidth = data[i];
516 debug("Sdram Width: %d\n",
517 dimmInfo->sdramWidth);
519 /*------------------------------------------------------------------------------------------------------------------------------*/
521 case 14: /* Error Check Data Width */
522 dimmInfo->errorCheckDataWidth = data[i];
523 debug("Error Check Data Width: %d\n",
524 dimmInfo->errorCheckDataWidth);
526 /*------------------------------------------------------------------------------------------------------------------------------*/
528 case 15: /* Minimum Clock Delay */
529 dimmInfo->minClkDelay = data[i];
530 debug("Minimum Clock Delay: %d\n",
531 dimmInfo->minClkDelay);
533 /*------------------------------------------------------------------------------------------------------------------------------*/
535 case 16: /* Burst Length Supported */
536 /******-******-******-*******
537 * bit3 | bit2 | bit1 | bit0 *
538 *******-******-******-*******
539 burst length = * 8 | 4 | 2 | 1 *
540 *****************************
542 If for example bit0 and bit2 are set, the burst
543 length supported are 1 and 4. */
545 dimmInfo->burstLengthSupported = data[i];
547 debug("Burst Length Supported: ");
548 if (dimmInfo->burstLengthSupported & 0x01)
550 if (dimmInfo->burstLengthSupported & 0x02)
552 if (dimmInfo->burstLengthSupported & 0x04)
554 if (dimmInfo->burstLengthSupported & 0x08)
559 /*------------------------------------------------------------------------------------------------------------------------------*/
561 case 17: /* Number Of Banks On Each Device */
562 dimmInfo->numOfBanksOnEachDevice = data[i];
563 debug("Number Of Banks On Each Chip: %d\n",
564 dimmInfo->numOfBanksOnEachDevice);
566 /*------------------------------------------------------------------------------------------------------------------------------*/
568 case 18: /* Suported Cas Latencies */
571 *******-******-******-******-******-******-******-*******
572 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
573 *******-******-******-******-******-******-******-*******
574 CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
575 *********************************************************
577 *******-******-******-******-******-******-******-*******
578 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
579 *******-******-******-******-******-******-******-*******
580 CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
581 ********************************************************/
582 dimmInfo->suportedCasLatencies = data[i];
584 debug("Suported Cas Latencies: (CL) ");
585 if (dimmInfo->memoryType == 0) { /* SDRAM */
586 for (k = 0; k <= 7; k++) {
588 suportedCasLatencies & (1 << k))
593 } else { /* DDR-RAM */
595 if (dimmInfo->suportedCasLatencies & 1)
597 if (dimmInfo->suportedCasLatencies & 2)
599 if (dimmInfo->suportedCasLatencies & 4)
601 if (dimmInfo->suportedCasLatencies & 8)
603 if (dimmInfo->suportedCasLatencies & 16)
605 if (dimmInfo->suportedCasLatencies & 32)
611 /* Calculating MAX CAS latency */
612 for (j = 7; j > 0; j--) {
614 suportedCasLatencies >> j) & 0x1) ==
616 switch (dimmInfo->memoryType) {
618 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
621 debug("Max. Cas Latencies (DDR): ERROR !!!\n");
629 debug("Max. Cas Latencies (DDR): ERROR !!!\n");
637 debug("Max. Cas Latencies (DDR): 3.5 clk's\n");
643 debug("Max. Cas Latencies (DDR): 3 clk's \n");
649 debug("Max. Cas Latencies (DDR): 2.5 clk's \n");
655 debug("Max. Cas Latencies (DDR): 2 clk's \n");
661 debug("Max. Cas Latencies (DDR): 1.5 clk's \n");
668 maxCASlatencySupported_LoP
672 if (((5 * j) % 10) != 0)
674 maxCASlatencySupported_RoP
678 maxCASlatencySupported_RoP
680 debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
682 maxCASlatencySupported_LoP,
684 maxCASlatencySupported_RoP);
687 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
688 dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
689 debug("Max. Cas Latencies (SD): %d\n",
693 maxCASlatencySupported_LoP
696 maxCASlatencySupported_RoP
698 debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
700 maxCASlatencySupported_LoP,
702 maxCASlatencySupported_RoP);
709 /*------------------------------------------------------------------------------------------------------------------------------*/
711 case 21: /* Buffered Address And Control Inputs */
712 debug("\nModul Attributes (SPD Byte 21): \n");
713 dimmInfo->bufferedAddrAndControlInputs =
715 dimmInfo->registeredAddrAndControlInputs =
716 (data[i] & BIT1) >> 1;
717 dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
718 dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
719 dimmInfo->registeredDQMBinputs =
720 (data[i] & BIT4) >> 4;
721 dimmInfo->differentialClockInput =
722 (data[i] & BIT5) >> 5;
723 dimmInfo->redundantRowAddressing =
724 (data[i] & BIT6) >> 6;
726 if (dimmInfo->bufferedAddrAndControlInputs == 1)
727 debug(" - Buffered Address/Control Input: Yes \n");
729 debug(" - Buffered Address/Control Input: No \n");
731 if (dimmInfo->registeredAddrAndControlInputs == 1)
732 debug(" - Registered Address/Control Input: Yes \n");
734 debug(" - Registered Address/Control Input: No \n");
736 if (dimmInfo->onCardPLL == 1)
737 debug(" - On-Card PLL (clock): Yes \n");
739 debug(" - On-Card PLL (clock): No \n");
741 if (dimmInfo->bufferedDQMBinputs == 1)
742 debug(" - Bufferd DQMB Inputs: Yes \n");
744 debug(" - Bufferd DQMB Inputs: No \n");
746 if (dimmInfo->registeredDQMBinputs == 1)
747 debug(" - Registered DQMB Inputs: Yes \n");
749 debug(" - Registered DQMB Inputs: No \n");
751 if (dimmInfo->differentialClockInput == 1)
752 debug(" - Differential Clock Input: Yes \n");
754 debug(" - Differential Clock Input: No \n");
756 if (dimmInfo->redundantRowAddressing == 1)
757 debug(" - redundant Row Addressing: Yes \n");
759 debug(" - redundant Row Addressing: No \n");
762 /*------------------------------------------------------------------------------------------------------------------------------*/
764 case 22: /* Suported AutoPreCharge */
765 debug("\nModul Attributes (SPD Byte 22): \n");
766 dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
767 dimmInfo->suportedAutoPreCharge =
768 (data[i] & BIT1) >> 1;
769 dimmInfo->suportedPreChargeAll =
770 (data[i] & BIT2) >> 2;
771 dimmInfo->suportedWrite1ReadBurst =
772 (data[i] & BIT3) >> 3;
773 dimmInfo->suported5PercentLowVCC =
774 (data[i] & BIT4) >> 4;
775 dimmInfo->suported5PercentUpperVCC =
776 (data[i] & BIT5) >> 5;
778 if (dimmInfo->suportedEarlyRasPreCharge == 1)
779 debug(" - Early Ras Precharge: Yes \n");
781 debug(" - Early Ras Precharge: No \n");
783 if (dimmInfo->suportedAutoPreCharge == 1)
784 debug(" - AutoPreCharge: Yes \n");
786 debug(" - AutoPreCharge: No \n");
788 if (dimmInfo->suportedPreChargeAll == 1)
789 debug(" - Precharge All: Yes \n");
791 debug(" - Precharge All: No \n");
793 if (dimmInfo->suportedWrite1ReadBurst == 1)
794 debug(" - Write 1/ReadBurst: Yes \n");
796 debug(" - Write 1/ReadBurst: No \n");
798 if (dimmInfo->suported5PercentLowVCC == 1)
799 debug(" - lower VCC tolerance: 5 Percent \n");
801 debug(" - lower VCC tolerance: 10 Percent \n");
803 if (dimmInfo->suported5PercentUpperVCC == 1)
804 debug(" - upper VCC tolerance: 5 Percent \n");
806 debug(" - upper VCC tolerance: 10 Percent \n");
809 /*------------------------------------------------------------------------------------------------------------------------------*/
811 case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
812 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
813 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
815 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
817 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
818 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
819 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
820 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
822 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
824 debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
825 leftOfPoint, rightOfPoint);
826 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
828 /*------------------------------------------------------------------------------------------------------------------------------*/
830 case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
831 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
833 (((data[i] & 0xf0) >> 4) * 10) +
835 leftOfPoint = time_tmp / div;
836 rightOfPoint = time_tmp % div;
837 dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
838 dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
839 debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
840 leftOfPoint, rightOfPoint);
842 /*------------------------------------------------------------------------------------------------------------------------------*/
844 case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
845 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
846 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
848 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
850 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
851 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
852 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
853 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
855 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
857 debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
858 leftOfPoint, rightOfPoint);
859 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
861 /*------------------------------------------------------------------------------------------------------------------------------*/
863 case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
864 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
866 (((data[i] & 0xf0) >> 4) * 10) +
868 leftOfPoint = time_tmp / div;
869 rightOfPoint = time_tmp % div;
870 dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
871 dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
872 debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
873 leftOfPoint, rightOfPoint);
875 /*------------------------------------------------------------------------------------------------------------------------------*/
877 case 27: /* Minimum Row Precharge Time */
878 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
880 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
882 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
883 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
884 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
886 dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
888 (dimmInfo->minRowPrechargeTime +
889 (tmemclk - 1)) / tmemclk;
890 debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
891 tmemclk, tmemclk / 100, tmemclk % 100);
892 debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
893 leftOfPoint, rightOfPoint, trp_clocks);
895 /*------------------------------------------------------------------------------------------------------------------------------*/
897 case 28: /* Minimum Row Active to Row Active Time */
898 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
900 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
902 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
903 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
904 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
906 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
907 debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
908 leftOfPoint, rightOfPoint, trp_clocks);
910 /*------------------------------------------------------------------------------------------------------------------------------*/
912 case 29: /* Minimum Ras-To-Cas Delay */
913 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
915 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
917 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
918 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
919 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
921 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
922 debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
923 leftOfPoint, rightOfPoint, trp_clocks);
925 /*------------------------------------------------------------------------------------------------------------------------------*/
927 case 30: /* Minimum Ras Pulse Width */
928 dimmInfo->minRasPulseWidth = data[i];
930 (NSto10PS (data[i]) +
931 (tmemclk - 1)) / tmemclk;
932 debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
933 dimmInfo->minRasPulseWidth, tras_clocks);
936 /*------------------------------------------------------------------------------------------------------------------------------*/
938 case 31: /* Module Bank Density */
939 dimmInfo->moduleBankDensity = data[i];
940 debug("Module Bank Density: %d\n",
941 dimmInfo->moduleBankDensity);
943 debug("*** Offered Densities (more than 1 = Multisize-Module): ");
945 if (dimmInfo->moduleBankDensity & 1)
947 if (dimmInfo->moduleBankDensity & 2)
949 if (dimmInfo->moduleBankDensity & 4)
951 if (dimmInfo->moduleBankDensity & 8)
953 if (dimmInfo->moduleBankDensity & 16)
955 if (dimmInfo->moduleBankDensity & 32)
957 if ((dimmInfo->moduleBankDensity & 64)
958 || (dimmInfo->moduleBankDensity & 128)) {
966 /*------------------------------------------------------------------------------------------------------------------------------*/
968 case 32: /* Address And Command Setup Time (measured in ns/1000) */
970 switch (dimmInfo->memoryType) {
973 (((data[i] & 0xf0) >> 4) * 10) +
975 leftOfPoint = time_tmp / 100;
976 rightOfPoint = time_tmp % 100;
979 leftOfPoint = (data[i] & 0xf0) >> 4;
980 if (leftOfPoint > 7) {
981 leftOfPoint = data[i] & 0x70 >> 4;
984 rightOfPoint = (data[i] & 0x0f);
987 dimmInfo->addrAndCommandSetupTime =
988 (leftOfPoint * 100 + rightOfPoint) * sign;
989 debug("Address And Command Setup Time [ns]: %d.%d\n",
990 sign * leftOfPoint, rightOfPoint);
992 /*------------------------------------------------------------------------------------------------------------------------------*/
994 case 33: /* Address And Command Hold Time */
996 switch (dimmInfo->memoryType) {
999 (((data[i] & 0xf0) >> 4) * 10) +
1001 leftOfPoint = time_tmp / 100;
1002 rightOfPoint = time_tmp % 100;
1005 leftOfPoint = (data[i] & 0xf0) >> 4;
1006 if (leftOfPoint > 7) {
1007 leftOfPoint = data[i] & 0x70 >> 4;
1010 rightOfPoint = (data[i] & 0x0f);
1013 dimmInfo->addrAndCommandHoldTime =
1014 (leftOfPoint * 100 + rightOfPoint) * sign;
1015 debug("Address And Command Hold Time [ns]: %d.%d\n",
1016 sign * leftOfPoint, rightOfPoint);
1018 /*------------------------------------------------------------------------------------------------------------------------------*/
1020 case 34: /* Data Input Setup Time */
1022 switch (dimmInfo->memoryType) {
1025 (((data[i] & 0xf0) >> 4) * 10) +
1027 leftOfPoint = time_tmp / 100;
1028 rightOfPoint = time_tmp % 100;
1031 leftOfPoint = (data[i] & 0xf0) >> 4;
1032 if (leftOfPoint > 7) {
1033 leftOfPoint = data[i] & 0x70 >> 4;
1036 rightOfPoint = (data[i] & 0x0f);
1039 dimmInfo->dataInputSetupTime =
1040 (leftOfPoint * 100 + rightOfPoint) * sign;
1041 debug("Data Input Setup Time [ns]: %d.%d\n",
1042 sign * leftOfPoint, rightOfPoint);
1044 /*------------------------------------------------------------------------------------------------------------------------------*/
1046 case 35: /* Data Input Hold Time */
1048 switch (dimmInfo->memoryType) {
1051 (((data[i] & 0xf0) >> 4) * 10) +
1053 leftOfPoint = time_tmp / 100;
1054 rightOfPoint = time_tmp % 100;
1057 leftOfPoint = (data[i] & 0xf0) >> 4;
1058 if (leftOfPoint > 7) {
1059 leftOfPoint = data[i] & 0x70 >> 4;
1062 rightOfPoint = (data[i] & 0x0f);
1065 dimmInfo->dataInputHoldTime =
1066 (leftOfPoint * 100 + rightOfPoint) * sign;
1067 debug("Data Input Hold Time [ns]: %d.%d\n\n",
1068 sign * leftOfPoint, rightOfPoint);
1070 /*------------------------------------------------------------------------------------------------------------------------------*/
1073 /* calculating the sdram density */
1075 i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1077 density = density * 2;
1079 dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1080 dimmInfo->sdramWidth;
1081 dimmInfo->numberOfDevices =
1082 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1083 dimmInfo->numOfModuleBanks;
1084 devicesForErrCheck =
1085 (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1086 if ((dimmInfo->errorCheckType == 0x1)
1087 || (dimmInfo->errorCheckType == 0x2)
1088 || (dimmInfo->errorCheckType == 0x3)) {
1090 (dimmInfo->deviceDensity / 8) *
1091 (dimmInfo->numberOfDevices - devicesForErrCheck);
1094 (dimmInfo->deviceDensity / 8) *
1095 dimmInfo->numberOfDevices;
1098 /* compute the module DRB size */
1100 (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1101 tmp *= dimmInfo->numOfModuleBanks;
1102 tmp *= dimmInfo->sdramWidth;
1103 tmp = tmp >> 24; /* div by 0x4000000 (64M) */
1104 dimmInfo->drb_size = (uchar) tmp;
1105 debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
1107 /* try a CAS latency of 3 first... */
1109 /* bit 1 is CL2, bit 2 is CL3 */
1110 supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1114 if (NS10to10PS (data[9]) <= tmemclk)
1118 if (NS10to10PS (data[9]) <= tmemclk)
1124 if (NS10to10PS (data[23]) <= tmemclk)
1128 debug("cal_val = %d\n", cal_val * 5);
1130 /* bummer, did't work... */
1132 debug("Couldn't find a good CAS latency\n");
1140 /* sets up the GT properly with information passed in */
1141 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1144 ulong tmp_sdram_mode = 0; /* 0x141c */
1145 ulong tmp_dunit_control_low = 0; /* 0x1404 */
1146 uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
1149 /* sanity checking */
1150 if (!info->numOfModuleBanks) {
1151 printf ("setup_sdram called with 0 banks\n");
1157 /* Program the GT with the discovered data */
1158 if (info->registeredAddrAndControlInputs == true)
1159 debug("Module is registered, but we do not support registered Modules !!!\n");
1162 set_dfcdlInit (); /* may be its not needed */
1163 debug("Delay line set done\n");
1165 /* set SDRAM mode NOP */ /* To_do check it */
1166 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1167 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1168 debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
1171 #ifdef CONFIG_MV64360_ECC
1172 if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
1173 /* DRAM has ECC, so turn it on */
1174 sdram_config_reg |= BIT18;
1175 debug("Enabling ECC\n");
1177 #endif /* of ifdef CONFIG_MV64360_ECC */
1179 /* SDRAM configuration */
1180 GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
1181 debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
1183 /* SDRAM open pages controll keep open as much as I can */
1184 GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1185 debug("sdram_open_pages_controll 0x1414: %08x\n",
1186 GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
1189 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1190 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1192 debug("Core Signals are sync (by HW-Setting)!!!\n");
1194 debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
1196 /* SDRAM set CAS Lentency according to SPD information */
1197 switch (info->memoryType) {
1199 debug("### SD-RAM not supported yet !!!\n");
1201 /* ToDo fill SD-RAM if needed !!!!! */
1205 debug("### SET-CL for DDR-RAM\n");
1207 switch (info->maxClSupported_DDR) {
1209 tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */
1210 tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
1211 debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1212 tmp_sdram_mode, tmp_dunit_control_low);
1216 if (tmp == 1) { /* clocks sync */
1217 tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */
1218 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1219 debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1220 tmp_sdram_mode, tmp_dunit_control_low);
1221 } else { /* clk sync. bypassed */
1223 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1224 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1225 debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1226 tmp_sdram_mode, tmp_dunit_control_low);
1231 if (tmp == 1) { /* Sync */
1232 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1233 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1234 debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1235 tmp_sdram_mode, tmp_dunit_control_low);
1236 } else { /* Not sync. */
1238 tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */
1239 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1240 debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1241 tmp_sdram_mode, tmp_dunit_control_low);
1246 if (tmp == 1) { /* Sync */
1247 tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */
1248 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1249 debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1250 tmp_sdram_mode, tmp_dunit_control_low);
1251 } else { /* not sync */
1253 tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */
1254 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1255 debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1256 tmp_sdram_mode, tmp_dunit_control_low);
1261 printf ("Max. CL is out of range %d\n",
1262 info->maxClSupported_DDR);
1269 /* Write results of CL detection procedure */
1270 GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1271 /* set SDRAM mode SetCommand 0x1418 */
1272 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1273 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1274 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1278 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1279 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1280 if (tmp != 1) { /*clocks are not sync */
1282 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1283 (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1284 0x18110780 | tmp_dunit_control_low);
1287 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1288 (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1289 0x00110000 | tmp_dunit_control_low);
1292 /* set SDRAM mode SetCommand 0x1418 */
1293 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1294 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1295 debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
1298 /*------------------------------------------------------------------------------ */
1301 /* bank parameters */
1302 /* SDRAM address decode register */
1303 /* program this with the default value */
1307 debug("drb_size (n*64Mbit): %d\n", info->drb_size);
1308 switch (info->drb_size) {
1309 case 1: /* 64 Mbit */
1310 case 2: /* 128 Mbit */
1311 debug("RAM-Device_size 64Mbit or 128Mbit)\n");
1314 case 4: /* 256 Mbit */
1315 case 8: /* 512 Mbit */
1316 debug("RAM-Device_size 256Mbit or 512Mbit)\n");
1319 case 16: /* 1 Gbit */
1320 case 32: /* 2 Gbit */
1321 debug("RAM-Device_size 1Gbit or 2Gbit)\n");
1325 printf ("Error in dram size calculation\n");
1326 debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
1331 /* SDRAM bank parameters */
1332 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1333 debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
1334 GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1336 /* ------------------------------------------------------------------------------ */
1338 debug("setting up sdram_timing_control_low with: %08x \n",
1340 GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1343 /* ------------------------------------------------------------------------------ */
1345 /* SDRAM configuration */
1346 tmp = GTREGREAD (SDRAM_CONFIG);
1348 if (info->registeredAddrAndControlInputs
1349 || info->registeredDQMBinputs) {
1351 debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1352 info->registeredAddrAndControlInputs,
1353 info->registeredDQMBinputs);
1356 /* Use buffer 1 to return read data to the CPU
1357 * Page 426 MV64360 */
1359 debug("Before Buffer assignment - sdram_conf: %08x\n",
1360 GTREGREAD (SDRAM_CONFIG));
1361 debug("After Buffer assignment - sdram_conf: %08x\n",
1362 GTREGREAD (SDRAM_CONFIG));
1364 /* SDRAM timing To_do: */
1367 tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1368 debug("# sdram_timing_control_high is : %08lx \n", tmp);
1370 /* SDRAM address decode register */
1371 /* program this with the default value */
1372 tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1373 debug("SDRAM address control (before: decode): %08x ",
1374 GTREGREAD (SDRAM_ADDR_CONTROL));
1375 GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1376 debug("SDRAM address control (after: decode): %08x\n",
1377 GTREGREAD (SDRAM_ADDR_CONTROL));
1379 /* set the SDRAM configuration for each bank */
1381 /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1386 debug("\n*** Running a MRS cycle for bank %d ***\n", i);
1389 memory_map_bank (i, 0, GB / 4);
1390 #if 1 /* test only */
1392 tmp = GTREGREAD (SDRAM_MODE);
1393 GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
1394 GT_REG_WRITE (SDRAM_OPERATION, 0x4);
1395 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1396 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1399 GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
1400 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1401 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1402 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1406 l1 += GTREGREAD (SDRAM_OPERATION);
1408 GT_REG_WRITE (SDRAM_MODE, tmp);
1409 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1410 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1411 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1414 /* switch back to normal operation mode */
1415 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1416 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1417 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1420 #endif /* test only */
1421 /* unmap the bank */
1422 memory_map_bank (i, 0, 0);
1429 * Check memory range for valid RAM. A simple memory test determines
1430 * the actually available RAM size between addresses `base' and
1431 * `base + maxsize'. Some (not all) hardware errors are detected:
1432 * - short between address lines
1433 * - short between data lines
1436 dram_size(long int *base, long int maxsize)
1438 volatile long int *addr, *b=base;
1439 long int cnt, val, save1, save2;
1441 #define STARTVAL (1<<20) /* start test at 1M */
1442 for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1443 addr = base + cnt; /* pointer arith! */
1445 save1 = *addr; /* save contents of addr */
1446 save2 = *b; /* save contents of base */
1448 *addr=cnt; /* write cnt to addr */
1449 *b=0; /* put null at base */
1451 /* check at base address */
1453 *addr=save1; /* restore *addr */
1454 *b=save2; /* restore *b */
1457 val = *addr; /* read *addr */
1458 val = *addr; /* read *addr */
1464 debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
1465 /* fix boundary condition.. STARTVAL means zero */
1466 if(cnt==STARTVAL/sizeof(long)) cnt=0;
1467 return (cnt * sizeof(long));
1473 #ifdef CONFIG_MV64360_ECC
1475 * mv_dma_is_channel_active:
1476 * Checks if a engine is busy.
1478 int mv_dma_is_channel_active(int engine)
1482 data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
1483 if (data & BIT14) /* activity status */
1490 * mv_dma_set_memory_space:
1491 * Set a DMA memory window for the DMA's address decoding map.
1493 int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
1494 ulong mem_space_attr, ulong base_address,
1499 /* The base address must be aligned to the size. */
1500 if (base_address % size != 0)
1503 if (size >= 0x10000) {
1505 base_address = (base_address & 0xffff0000);
1506 /* Set the new attributes */
1507 GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
1508 (base_address | mem_space_target |
1510 GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
1511 (size - 1) & 0xffff0000);
1512 temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
1513 GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
1514 (temp & ~(BIT0 << mem_space)));
1524 * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
1526 int mv_dma_transfer(int engine, ulong source_addr,
1527 ulong dest_addr, ulong bytes, ulong command)
1529 ulong eng_off_reg; /* Engine Offset Register */
1532 command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
1534 command = command | ((command >> 6) & 0x7);
1535 eng_off_reg = engine * 4;
1536 GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
1538 GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
1540 GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
1542 command |= BIT12 /* DMA_CHANNEL_ENABLE */
1543 | BIT9; /* DMA_NON_CHAIN_MODE */
1545 /* Activate DMA engine By writting to mv_dma_control_register */
1546 GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
1550 #endif /* of ifdef CONFIG_MV64360_ECC */
1552 /* ppcboot interface function to SDRAM init - this is where all the
1553 * controlling logic happens */
1555 initdram(int board_type)
1557 int checkbank[4] = { [0 ... 3] = 0 };
1558 ulong realsize, total, check;
1559 AUX_MEM_DIMM_INFO dimmInfo1;
1560 AUX_MEM_DIMM_INFO dimmInfo2;
1562 #ifdef CONFIG_MV64360_ECC
1563 ulong dest, mem_space_attr;
1564 #endif /* of ifdef CONFIG_MV64360_ECC */
1566 /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1568 /* check the NHR bit and skip mem init if it's already done */
1569 nhr = get_hid0() & (1 << 16);
1572 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1575 (void)check_dimm(0, &dimmInfo1);
1578 (void)check_dimm(1, &dimmInfo2);
1580 memory_map_bank(0, 0, 0);
1581 memory_map_bank(1, 0, 0);
1582 memory_map_bank(2, 0, 0);
1583 memory_map_bank(3, 0, 0);
1585 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1586 printf("Setup for DIMM1 failed.\n");
1589 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1590 printf("Setup for DIMM2 failed.\n");
1593 /* set the NHR bit */
1594 set_hid0(get_hid0() | (1 << 16));
1596 /* next, size the SDRAM banks */
1598 realsize = total = 0;
1600 if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1601 if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1602 if (dimmInfo1.numOfModuleBanks > 2)
1603 printf("Error, SPD claims DIMM1 has >2 banks\n");
1605 if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1606 if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1607 if (dimmInfo2.numOfModuleBanks > 2)
1608 printf("Error, SPD claims DIMM2 has >2 banks\n");
1610 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1611 /* skip over banks that are not populated */
1612 if (! checkbank[bank_no])
1615 if ((total + check) > CONFIG_SYS_GT_REGS)
1616 check = CONFIG_SYS_GT_REGS - total;
1618 memory_map_bank(bank_no, total, check);
1619 realsize = dram_size((long int *)total, check);
1620 memory_map_bank(bank_no, total, realsize);
1622 #ifdef CONFIG_MV64360_ECC
1623 if (((dimmInfo1.errorCheckType != 0) &&
1624 ((dimmInfo2.errorCheckType != 0) ||
1625 (dimmInfo2.numOfModuleBanks == 0))) &&
1626 (CPCI750_ECC_TEST)) {
1627 printf("ECC Initialization of Bank %d:", bank_no);
1628 mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1629 mv_dma_set_memory_space(0, 0, mem_space_attr, total,
1631 for (dest = total; dest < total + realsize;
1633 mv_dma_transfer(0, total, dest, _8M,
1634 BIT8 | /* DMA_DTL_128BYTES */
1635 BIT3 | /* DMA_HOLD_SOURCE_ADDR */
1636 BIT11); /* DMA_BLOCK_TRANSFER_MODE */
1637 while (mv_dma_is_channel_active(0))
1642 #endif /* of ifdef CONFIG_MV64360_ECC */
1647 /* Setup Ethernet DMA Adress window to DRAM Area */
1651 /* ***************************************************************************************
1653 ! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
1654 ! * This procedure fits only the Atlantis *
1656 ! *************************************************************************************** */
1659 /* ***************************************************************************************
1660 ! * DFCDL initialize MV643xx Design Considerations *
1662 ! *************************************************************************************** */
1663 int set_dfcdlInit (void)
1666 unsigned int dfcdl_word = 0x0000014f;
1668 for (i = 0; i < 64; i++) {
1669 GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1671 GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
1677 int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1679 unsigned int ecc_counter;
1680 unsigned int ecc_addr;
1682 GT_REG_READ(0x1458, &ecc_counter);
1683 GT_REG_READ(0x1450, &ecc_addr);
1684 GT_REG_WRITE(0x1450, 0);
1686 printf("Error Counter since Reset: %8d\n", ecc_counter);
1687 printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8);
1688 if (ecc_addr & 0x01)
1692 printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
1699 show_ecc, 1, 1, do_show_ecc,
1700 "Show Marvell MV64360 ECC Info",
1701 "Show Marvell MV64360 ECC Counter and last error."