3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /*************************************************************************
25 * adaption for the Marvell DB64360 Board
26 * Ingo Assmus (ingo.assmus@keymile.com)
28 * adaption for the cpci750 Board
29 * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
30 *************************************************************************/
33 /* sdram_init.c - automatic memory sizing */
37 #include "../../Marvell/include/memory.h"
38 #include "../../Marvell/include/pci.h"
39 #include "../../Marvell/include/mv_gen_reg.h"
44 #include "../../Marvell/common/i2c.h"
48 DECLARE_GLOBAL_DATA_PTR;
50 int set_dfcdlInit(void); /* setup delay line of Mv64360 */
52 /* ------------------------------------------------------------------------- */
55 memory_map_bank(unsigned int bankNo,
56 unsigned int bankBase,
57 unsigned int bankLength)
66 printf("mapping bank %d at %08x - %08x\n",
67 bankNo, bankBase, bankBase + bankLength - 1);
69 printf("unmapping bank %d\n", bankNo);
73 memoryMapBank(bankNo, bankBase, bankLength);
76 for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
81 READ_LINE_AGGRESSIVE_PREFETCH |
82 READ_MULTI_AGGRESSIVE_PREFETCH |
86 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
88 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
91 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
99 /* much of this code is based on (or is) the code in the pip405 port */
100 /* thanks go to the authors of said port - Josh */
102 /* structure to store the relevant information about an sdram bank */
103 typedef struct sdram_info {
105 uchar registered, ecc;
112 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
114 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
116 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
117 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
120 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
121 typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
124 /* SDRAM/DDR information struct */
125 typedef struct _gtMemoryDimmInfo {
126 MEMORY_TYPE memoryType;
127 unsigned int numOfRowAddresses;
128 unsigned int numOfColAddresses;
129 unsigned int numOfModuleBanks;
130 unsigned int dataWidth;
131 VOLTAGE_INTERFACE voltageInterface;
132 unsigned int errorCheckType; /* ECC , PARITY.. */
133 unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
134 unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
135 unsigned int minClkDelay;
136 unsigned int burstLengthSupported;
137 unsigned int numOfBanksOnEachDevice;
138 unsigned int suportedCasLatencies;
139 unsigned int RefreshInterval;
140 unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
141 unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
142 MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
143 MAX_CL_SUPPORTED_SD maxClSupported_SD;
144 unsigned int moduleBankDensity;
145 /* module attributes (true for yes) */
146 bool bufferedAddrAndControlInputs;
147 bool registeredAddrAndControlInputs;
149 bool bufferedDQMBinputs;
150 bool registeredDQMBinputs;
151 bool differentialClockInput;
152 bool redundantRowAddressing;
154 /* module general attributes */
155 bool suportedAutoPreCharge;
156 bool suportedPreChargeAll;
157 bool suportedEarlyRasPreCharge;
158 bool suportedWrite1ReadBurst;
159 bool suported5PercentLowVCC;
160 bool suported5PercentUpperVCC;
161 /* module timing parameters */
162 unsigned int minRasToCasDelay;
163 unsigned int minRowActiveRowActiveDelay;
164 unsigned int minRasPulseWidth;
165 unsigned int minRowPrechargeTime; /* measured in ns */
167 int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
168 int addrAndCommandSetupTime; /* (measured in ns/100) */
169 int dataInputSetupTime; /* LoP left of point (measured in ns) */
170 int dataInputHoldTime; /* LoP left of point (measured in ns) */
171 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
172 unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
173 unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
174 unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
175 unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
176 unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
177 unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
179 unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
180 unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
182 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
183 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
185 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
186 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
188 /* Parameters calculated from
189 the extracted DIMM information */
191 unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
192 unsigned int numberOfDevices;
193 uchar drb_size; /* DRAM size in n*64Mbit */
194 uchar slot; /* Slot Number this module is inserted in */
195 uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
197 uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
198 uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
199 uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
200 unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
201 unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
202 unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
203 uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
210 * translate ns.ns/10 coding of SPD timing values
211 * into 10 ps unit values
213 static inline unsigned short
214 NS10to10PS(unsigned char spd_byte)
216 unsigned short ns, ns10;
218 /* isolate upper nibble */
219 ns = (spd_byte >> 4) & 0x0F;
220 /* isolate lower nibble */
221 ns10 = (spd_byte & 0x0F);
223 return(ns*100 + ns10*10);
227 * translate ns coding of SPD timing values
228 * into 10 ps unit values
230 static inline unsigned short
231 NSto10PS(unsigned char spd_byte)
233 return(spd_byte*100);
236 /* This code reads the SPD chip on the sdram and populates
237 * the array which is passed in with the relevant information */
238 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
239 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
241 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
243 unsigned int i, j, density = 1, devicesForErrCheck = 0;
248 unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
249 int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
250 uchar supp_cal, cal_val;
251 ulong memclk, tmemclk;
253 uchar trp_clocks = 0, tras_clocks;
256 memclk = gd->bus_clk;
257 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
259 memset (data, 0, sizeof (data));
264 debug("before i2c read\n");
266 ret = i2c_read (addr, 0, 2, data, 128);
268 debug("after i2c read\n");
270 if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
271 || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
272 || (data[70] != 'b') || (data[71] != 'h')) {
276 if ((ret != 0) && (slot == 0)) {
277 memset (data, 0, sizeof (data));
325 /* zero all the values */
326 memset (dimmInfo, 0, sizeof (*dimmInfo));
328 /* copy the SPD content 1:1 into the dimmInfo structure */
329 for (i = 0; i <= 127; i++) {
330 dimmInfo->spd_raw_data[i] = data[i];
334 debug("No DIMM in slot %d [err = %x]\n", slot, ret);
337 dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
339 #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
341 for (i = 0; i <= 127; i++) {
342 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
348 /* find Manufacturer of Dimm Module */
349 for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
350 dimmInfo->manufactura[i] = data[64 + i];
352 printf ("\nThis RAM-Module is produced by: %s\n",
353 dimmInfo->manufactura);
355 /* find Manul-ID of Dimm Module */
356 for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
357 dimmInfo->modul_id[i] = data[73 + i];
359 printf ("The Module-ID of this RAM-Module is: %s\n",
362 /* find Vendor-Data of Dimm Module */
363 for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
364 dimmInfo->vendor_data[i] = data[99 + i];
366 printf ("Vendor Data of this RAM-Module is: %s\n",
367 dimmInfo->vendor_data);
369 /* find modul_serial_no of Dimm Module */
370 dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
371 printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
372 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
374 /* find Manufac-Data of Dimm Module */
375 dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
376 printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
378 /* find modul_revision of Dimm Module */
379 dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
380 printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
382 /* find manufac_place of Dimm Module */
383 dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
384 printf ("manufac_place of this RAM-Module is: %d\n",
385 dimmInfo->manufac_place);
388 /*------------------------------------------------------------------------------------------------------------------------------*/
389 /* calculate SPD checksum */
390 /*------------------------------------------------------------------------------------------------------------------------------*/
391 #if 0 /* test-only */
394 for (i = 0; i <= 62; i++) {
395 spd_checksum += data[i];
398 if ((spd_checksum & 0xff) != data[63]) {
399 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
404 printf ("SPD Checksum ok!\n");
405 #endif /* test-only */
407 /*------------------------------------------------------------------------------------------------------------------------------*/
408 for (i = 2; i <= 35; i++) {
410 case 2: /* Memory type (DDR / SDRAM) */
411 dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
413 if (dimmInfo->memoryType == 0)
414 debug("Dram_type in slot %d is: SDRAM\n",
416 if (dimmInfo->memoryType == 1)
417 debug("Dram_type in slot %d is: DDRAM\n",
421 /*------------------------------------------------------------------------------------------------------------------------------*/
423 case 3: /* Number Of Row Addresses */
424 dimmInfo->numOfRowAddresses = data[i];
425 debug("Module Number of row addresses: %d\n",
426 dimmInfo->numOfRowAddresses);
428 /*------------------------------------------------------------------------------------------------------------------------------*/
430 case 4: /* Number Of Column Addresses */
431 dimmInfo->numOfColAddresses = data[i];
432 debug("Module Number of col addresses: %d\n",
433 dimmInfo->numOfColAddresses);
435 /*------------------------------------------------------------------------------------------------------------------------------*/
437 case 5: /* Number Of Module Banks */
438 dimmInfo->numOfModuleBanks = data[i];
439 debug("Number of Banks on Mod. : %d\n",
440 dimmInfo->numOfModuleBanks);
442 /*------------------------------------------------------------------------------------------------------------------------------*/
444 case 6: /* Data Width */
445 dimmInfo->dataWidth = data[i];
446 debug("Module Data Width: %d\n",
447 dimmInfo->dataWidth);
449 /*------------------------------------------------------------------------------------------------------------------------------*/
451 case 8: /* Voltage Interface */
454 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
455 debug("Module is TTL_5V_TOLERANT\n");
458 dimmInfo->voltageInterface = LVTTL;
459 debug("Module is LVTTL\n");
462 dimmInfo->voltageInterface = HSTL_1_5V;
463 debug("Module is TTL_5V_TOLERANT\n");
466 dimmInfo->voltageInterface = SSTL_3_3V;
467 debug("Module is HSTL_1_5V\n");
470 dimmInfo->voltageInterface = SSTL_2_5V;
471 debug("Module is SSTL_2_5V\n");
474 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
475 debug("Module is VOLTAGE_UNKNOWN\n");
479 /*------------------------------------------------------------------------------------------------------------------------------*/
481 case 9: /* Minimum Cycle Time At Max CasLatancy */
482 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
483 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
485 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
487 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
488 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
489 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
490 dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
492 dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
494 debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
495 leftOfPoint, rightOfPoint);
497 /*------------------------------------------------------------------------------------------------------------------------------*/
499 case 10: /* Clock To Data Out */
500 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
502 (((data[i] & 0xf0) >> 4) * 10) +
504 leftOfPoint = time_tmp / div;
505 rightOfPoint = time_tmp % div;
506 dimmInfo->clockToDataOut_LoP = leftOfPoint;
507 dimmInfo->clockToDataOut_RoP = rightOfPoint;
508 debug("Clock To Data Out: %d.%2d [ns]\n",
509 leftOfPoint, rightOfPoint);
510 /*dimmInfo->clockToDataOut */
512 /*------------------------------------------------------------------------------------------------------------------------------*/
514 #ifdef CONFIG_MV64360_ECC
515 case 11: /* Error Check Type */
516 dimmInfo->errorCheckType = data[i];
517 debug("Error Check Type (0=NONE): %d\n",
518 dimmInfo->errorCheckType);
520 #endif /* of ifdef CONFIG_MV64360_ECC */
521 /*------------------------------------------------------------------------------------------------------------------------------*/
523 case 12: /* Refresh Interval */
524 dimmInfo->RefreshInterval = data[i];
525 debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
526 dimmInfo->RefreshInterval);
528 /*------------------------------------------------------------------------------------------------------------------------------*/
530 case 13: /* Sdram Width */
531 dimmInfo->sdramWidth = data[i];
532 debug("Sdram Width: %d\n",
533 dimmInfo->sdramWidth);
535 /*------------------------------------------------------------------------------------------------------------------------------*/
537 case 14: /* Error Check Data Width */
538 dimmInfo->errorCheckDataWidth = data[i];
539 debug("Error Check Data Width: %d\n",
540 dimmInfo->errorCheckDataWidth);
542 /*------------------------------------------------------------------------------------------------------------------------------*/
544 case 15: /* Minimum Clock Delay */
545 dimmInfo->minClkDelay = data[i];
546 debug("Minimum Clock Delay: %d\n",
547 dimmInfo->minClkDelay);
549 /*------------------------------------------------------------------------------------------------------------------------------*/
551 case 16: /* Burst Length Supported */
552 /******-******-******-*******
553 * bit3 | bit2 | bit1 | bit0 *
554 *******-******-******-*******
555 burst length = * 8 | 4 | 2 | 1 *
556 *****************************
558 If for example bit0 and bit2 are set, the burst
559 length supported are 1 and 4. */
561 dimmInfo->burstLengthSupported = data[i];
563 debug("Burst Length Supported: ");
564 if (dimmInfo->burstLengthSupported & 0x01)
566 if (dimmInfo->burstLengthSupported & 0x02)
568 if (dimmInfo->burstLengthSupported & 0x04)
570 if (dimmInfo->burstLengthSupported & 0x08)
575 /*------------------------------------------------------------------------------------------------------------------------------*/
577 case 17: /* Number Of Banks On Each Device */
578 dimmInfo->numOfBanksOnEachDevice = data[i];
579 debug("Number Of Banks On Each Chip: %d\n",
580 dimmInfo->numOfBanksOnEachDevice);
582 /*------------------------------------------------------------------------------------------------------------------------------*/
584 case 18: /* Suported Cas Latencies */
587 *******-******-******-******-******-******-******-*******
588 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
589 *******-******-******-******-******-******-******-*******
590 CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
591 *********************************************************
593 *******-******-******-******-******-******-******-*******
594 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
595 *******-******-******-******-******-******-******-*******
596 CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
597 ********************************************************/
598 dimmInfo->suportedCasLatencies = data[i];
600 debug("Suported Cas Latencies: (CL) ");
601 if (dimmInfo->memoryType == 0) { /* SDRAM */
602 for (k = 0; k <= 7; k++) {
604 suportedCasLatencies & (1 << k))
609 } else { /* DDR-RAM */
611 if (dimmInfo->suportedCasLatencies & 1)
613 if (dimmInfo->suportedCasLatencies & 2)
615 if (dimmInfo->suportedCasLatencies & 4)
617 if (dimmInfo->suportedCasLatencies & 8)
619 if (dimmInfo->suportedCasLatencies & 16)
621 if (dimmInfo->suportedCasLatencies & 32)
627 /* Calculating MAX CAS latency */
628 for (j = 7; j > 0; j--) {
630 suportedCasLatencies >> j) & 0x1) ==
632 switch (dimmInfo->memoryType) {
634 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
637 debug("Max. Cas Latencies (DDR): ERROR !!!\n");
645 debug("Max. Cas Latencies (DDR): ERROR !!!\n");
653 debug("Max. Cas Latencies (DDR): 3.5 clk's\n");
659 debug("Max. Cas Latencies (DDR): 3 clk's \n");
665 debug("Max. Cas Latencies (DDR): 2.5 clk's \n");
671 debug("Max. Cas Latencies (DDR): 2 clk's \n");
677 debug("Max. Cas Latencies (DDR): 1.5 clk's \n");
684 maxCASlatencySupported_LoP
688 if (((5 * j) % 10) != 0)
690 maxCASlatencySupported_RoP
694 maxCASlatencySupported_RoP
696 debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
698 maxCASlatencySupported_LoP,
700 maxCASlatencySupported_RoP);
703 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
704 dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
705 debug("Max. Cas Latencies (SD): %d\n",
709 maxCASlatencySupported_LoP
712 maxCASlatencySupported_RoP
714 debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
716 maxCASlatencySupported_LoP,
718 maxCASlatencySupported_RoP);
725 /*------------------------------------------------------------------------------------------------------------------------------*/
727 case 21: /* Buffered Address And Control Inputs */
728 debug("\nModul Attributes (SPD Byte 21): \n");
729 dimmInfo->bufferedAddrAndControlInputs =
731 dimmInfo->registeredAddrAndControlInputs =
732 (data[i] & BIT1) >> 1;
733 dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
734 dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
735 dimmInfo->registeredDQMBinputs =
736 (data[i] & BIT4) >> 4;
737 dimmInfo->differentialClockInput =
738 (data[i] & BIT5) >> 5;
739 dimmInfo->redundantRowAddressing =
740 (data[i] & BIT6) >> 6;
742 if (dimmInfo->bufferedAddrAndControlInputs == 1)
743 debug(" - Buffered Address/Control Input: Yes \n");
745 debug(" - Buffered Address/Control Input: No \n");
747 if (dimmInfo->registeredAddrAndControlInputs == 1)
748 debug(" - Registered Address/Control Input: Yes \n");
750 debug(" - Registered Address/Control Input: No \n");
752 if (dimmInfo->onCardPLL == 1)
753 debug(" - On-Card PLL (clock): Yes \n");
755 debug(" - On-Card PLL (clock): No \n");
757 if (dimmInfo->bufferedDQMBinputs == 1)
758 debug(" - Bufferd DQMB Inputs: Yes \n");
760 debug(" - Bufferd DQMB Inputs: No \n");
762 if (dimmInfo->registeredDQMBinputs == 1)
763 debug(" - Registered DQMB Inputs: Yes \n");
765 debug(" - Registered DQMB Inputs: No \n");
767 if (dimmInfo->differentialClockInput == 1)
768 debug(" - Differential Clock Input: Yes \n");
770 debug(" - Differential Clock Input: No \n");
772 if (dimmInfo->redundantRowAddressing == 1)
773 debug(" - redundant Row Addressing: Yes \n");
775 debug(" - redundant Row Addressing: No \n");
778 /*------------------------------------------------------------------------------------------------------------------------------*/
780 case 22: /* Suported AutoPreCharge */
781 debug("\nModul Attributes (SPD Byte 22): \n");
782 dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
783 dimmInfo->suportedAutoPreCharge =
784 (data[i] & BIT1) >> 1;
785 dimmInfo->suportedPreChargeAll =
786 (data[i] & BIT2) >> 2;
787 dimmInfo->suportedWrite1ReadBurst =
788 (data[i] & BIT3) >> 3;
789 dimmInfo->suported5PercentLowVCC =
790 (data[i] & BIT4) >> 4;
791 dimmInfo->suported5PercentUpperVCC =
792 (data[i] & BIT5) >> 5;
794 if (dimmInfo->suportedEarlyRasPreCharge == 1)
795 debug(" - Early Ras Precharge: Yes \n");
797 debug(" - Early Ras Precharge: No \n");
799 if (dimmInfo->suportedAutoPreCharge == 1)
800 debug(" - AutoPreCharge: Yes \n");
802 debug(" - AutoPreCharge: No \n");
804 if (dimmInfo->suportedPreChargeAll == 1)
805 debug(" - Precharge All: Yes \n");
807 debug(" - Precharge All: No \n");
809 if (dimmInfo->suportedWrite1ReadBurst == 1)
810 debug(" - Write 1/ReadBurst: Yes \n");
812 debug(" - Write 1/ReadBurst: No \n");
814 if (dimmInfo->suported5PercentLowVCC == 1)
815 debug(" - lower VCC tolerance: 5 Percent \n");
817 debug(" - lower VCC tolerance: 10 Percent \n");
819 if (dimmInfo->suported5PercentUpperVCC == 1)
820 debug(" - upper VCC tolerance: 5 Percent \n");
822 debug(" - upper VCC tolerance: 10 Percent \n");
825 /*------------------------------------------------------------------------------------------------------------------------------*/
827 case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
828 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
829 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
831 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
833 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
834 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
835 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
836 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
838 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
840 debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
841 leftOfPoint, rightOfPoint);
842 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
844 /*------------------------------------------------------------------------------------------------------------------------------*/
846 case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
847 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
849 (((data[i] & 0xf0) >> 4) * 10) +
851 leftOfPoint = time_tmp / div;
852 rightOfPoint = time_tmp % div;
853 dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
854 dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
855 debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
856 leftOfPoint, rightOfPoint);
858 /*------------------------------------------------------------------------------------------------------------------------------*/
860 case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
861 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
862 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
864 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
866 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
867 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
868 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
869 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
871 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
873 debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
874 leftOfPoint, rightOfPoint);
875 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
877 /*------------------------------------------------------------------------------------------------------------------------------*/
879 case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
880 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
882 (((data[i] & 0xf0) >> 4) * 10) +
884 leftOfPoint = time_tmp / div;
885 rightOfPoint = time_tmp % div;
886 dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
887 dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
888 debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
889 leftOfPoint, rightOfPoint);
891 /*------------------------------------------------------------------------------------------------------------------------------*/
893 case 27: /* Minimum Row Precharge Time */
894 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
896 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
898 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
899 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
900 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
902 dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
904 (dimmInfo->minRowPrechargeTime +
905 (tmemclk - 1)) / tmemclk;
906 debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
907 tmemclk, tmemclk / 100, tmemclk % 100);
908 debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
909 leftOfPoint, rightOfPoint, trp_clocks);
911 /*------------------------------------------------------------------------------------------------------------------------------*/
913 case 28: /* Minimum Row Active to Row Active Time */
914 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
916 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
918 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
919 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
920 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
922 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
923 debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
924 leftOfPoint, rightOfPoint, trp_clocks);
926 /*------------------------------------------------------------------------------------------------------------------------------*/
928 case 29: /* Minimum Ras-To-Cas Delay */
929 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
931 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
933 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
934 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
935 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
937 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
938 debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
939 leftOfPoint, rightOfPoint, trp_clocks);
941 /*------------------------------------------------------------------------------------------------------------------------------*/
943 case 30: /* Minimum Ras Pulse Width */
944 dimmInfo->minRasPulseWidth = data[i];
946 (NSto10PS (data[i]) +
947 (tmemclk - 1)) / tmemclk;
948 debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
949 dimmInfo->minRasPulseWidth, tras_clocks);
952 /*------------------------------------------------------------------------------------------------------------------------------*/
954 case 31: /* Module Bank Density */
955 dimmInfo->moduleBankDensity = data[i];
956 debug("Module Bank Density: %d\n",
957 dimmInfo->moduleBankDensity);
959 debug("*** Offered Densities (more than 1 = Multisize-Module): ");
961 if (dimmInfo->moduleBankDensity & 1)
963 if (dimmInfo->moduleBankDensity & 2)
965 if (dimmInfo->moduleBankDensity & 4)
967 if (dimmInfo->moduleBankDensity & 8)
969 if (dimmInfo->moduleBankDensity & 16)
971 if (dimmInfo->moduleBankDensity & 32)
973 if ((dimmInfo->moduleBankDensity & 64)
974 || (dimmInfo->moduleBankDensity & 128)) {
982 /*------------------------------------------------------------------------------------------------------------------------------*/
984 case 32: /* Address And Command Setup Time (measured in ns/1000) */
986 switch (dimmInfo->memoryType) {
989 (((data[i] & 0xf0) >> 4) * 10) +
991 leftOfPoint = time_tmp / 100;
992 rightOfPoint = time_tmp % 100;
995 leftOfPoint = (data[i] & 0xf0) >> 4;
996 if (leftOfPoint > 7) {
997 leftOfPoint = data[i] & 0x70 >> 4;
1000 rightOfPoint = (data[i] & 0x0f);
1003 dimmInfo->addrAndCommandSetupTime =
1004 (leftOfPoint * 100 + rightOfPoint) * sign;
1005 debug("Address And Command Setup Time [ns]: %d.%d\n",
1006 sign * leftOfPoint, rightOfPoint);
1008 /*------------------------------------------------------------------------------------------------------------------------------*/
1010 case 33: /* Address And Command Hold Time */
1012 switch (dimmInfo->memoryType) {
1015 (((data[i] & 0xf0) >> 4) * 10) +
1017 leftOfPoint = time_tmp / 100;
1018 rightOfPoint = time_tmp % 100;
1021 leftOfPoint = (data[i] & 0xf0) >> 4;
1022 if (leftOfPoint > 7) {
1023 leftOfPoint = data[i] & 0x70 >> 4;
1026 rightOfPoint = (data[i] & 0x0f);
1029 dimmInfo->addrAndCommandHoldTime =
1030 (leftOfPoint * 100 + rightOfPoint) * sign;
1031 debug("Address And Command Hold Time [ns]: %d.%d\n",
1032 sign * leftOfPoint, rightOfPoint);
1034 /*------------------------------------------------------------------------------------------------------------------------------*/
1036 case 34: /* Data Input Setup Time */
1038 switch (dimmInfo->memoryType) {
1041 (((data[i] & 0xf0) >> 4) * 10) +
1043 leftOfPoint = time_tmp / 100;
1044 rightOfPoint = time_tmp % 100;
1047 leftOfPoint = (data[i] & 0xf0) >> 4;
1048 if (leftOfPoint > 7) {
1049 leftOfPoint = data[i] & 0x70 >> 4;
1052 rightOfPoint = (data[i] & 0x0f);
1055 dimmInfo->dataInputSetupTime =
1056 (leftOfPoint * 100 + rightOfPoint) * sign;
1057 debug("Data Input Setup Time [ns]: %d.%d\n",
1058 sign * leftOfPoint, rightOfPoint);
1060 /*------------------------------------------------------------------------------------------------------------------------------*/
1062 case 35: /* Data Input Hold Time */
1064 switch (dimmInfo->memoryType) {
1067 (((data[i] & 0xf0) >> 4) * 10) +
1069 leftOfPoint = time_tmp / 100;
1070 rightOfPoint = time_tmp % 100;
1073 leftOfPoint = (data[i] & 0xf0) >> 4;
1074 if (leftOfPoint > 7) {
1075 leftOfPoint = data[i] & 0x70 >> 4;
1078 rightOfPoint = (data[i] & 0x0f);
1081 dimmInfo->dataInputHoldTime =
1082 (leftOfPoint * 100 + rightOfPoint) * sign;
1083 debug("Data Input Hold Time [ns]: %d.%d\n\n",
1084 sign * leftOfPoint, rightOfPoint);
1086 /*------------------------------------------------------------------------------------------------------------------------------*/
1089 /* calculating the sdram density */
1091 i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1093 density = density * 2;
1095 dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1096 dimmInfo->sdramWidth;
1097 dimmInfo->numberOfDevices =
1098 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1099 dimmInfo->numOfModuleBanks;
1100 devicesForErrCheck =
1101 (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1102 if ((dimmInfo->errorCheckType == 0x1)
1103 || (dimmInfo->errorCheckType == 0x2)
1104 || (dimmInfo->errorCheckType == 0x3)) {
1106 (dimmInfo->deviceDensity / 8) *
1107 (dimmInfo->numberOfDevices - devicesForErrCheck);
1110 (dimmInfo->deviceDensity / 8) *
1111 dimmInfo->numberOfDevices;
1114 /* compute the module DRB size */
1116 (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1117 tmp *= dimmInfo->numOfModuleBanks;
1118 tmp *= dimmInfo->sdramWidth;
1119 tmp = tmp >> 24; /* div by 0x4000000 (64M) */
1120 dimmInfo->drb_size = (uchar) tmp;
1121 debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
1123 /* try a CAS latency of 3 first... */
1125 /* bit 1 is CL2, bit 2 is CL3 */
1126 supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1130 if (NS10to10PS (data[9]) <= tmemclk)
1134 if (NS10to10PS (data[9]) <= tmemclk)
1140 if (NS10to10PS (data[23]) <= tmemclk)
1144 debug("cal_val = %d\n", cal_val * 5);
1146 /* bummer, did't work... */
1148 debug("Couldn't find a good CAS latency\n");
1156 /* sets up the GT properly with information passed in */
1157 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1160 ulong tmp_sdram_mode = 0; /* 0x141c */
1161 ulong tmp_dunit_control_low = 0; /* 0x1404 */
1162 uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
1165 /* sanity checking */
1166 if (!info->numOfModuleBanks) {
1167 printf ("setup_sdram called with 0 banks\n");
1173 /* Program the GT with the discovered data */
1174 if (info->registeredAddrAndControlInputs == true)
1175 debug("Module is registered, but we do not support registered Modules !!!\n");
1178 set_dfcdlInit (); /* may be its not needed */
1179 debug("Delay line set done\n");
1181 /* set SDRAM mode NOP */ /* To_do check it */
1182 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1183 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1184 debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
1187 #ifdef CONFIG_MV64360_ECC
1188 if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
1189 /* DRAM has ECC, so turn it on */
1190 sdram_config_reg |= BIT18;
1191 debug("Enabling ECC\n");
1193 #endif /* of ifdef CONFIG_MV64360_ECC */
1195 /* SDRAM configuration */
1196 GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
1197 debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
1199 /* SDRAM open pages controll keep open as much as I can */
1200 GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1201 debug("sdram_open_pages_controll 0x1414: %08x\n",
1202 GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
1205 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1206 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1208 debug("Core Signals are sync (by HW-Setting)!!!\n");
1210 debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
1212 /* SDRAM set CAS Lentency according to SPD information */
1213 switch (info->memoryType) {
1215 debug("### SD-RAM not supported yet !!!\n");
1217 /* ToDo fill SD-RAM if needed !!!!! */
1221 debug("### SET-CL for DDR-RAM\n");
1223 switch (info->maxClSupported_DDR) {
1225 tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */
1226 tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
1227 debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1228 tmp_sdram_mode, tmp_dunit_control_low);
1232 if (tmp == 1) { /* clocks sync */
1233 tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */
1234 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1235 debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1236 tmp_sdram_mode, tmp_dunit_control_low);
1237 } else { /* clk sync. bypassed */
1239 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1240 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1241 debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1242 tmp_sdram_mode, tmp_dunit_control_low);
1247 if (tmp == 1) { /* Sync */
1248 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1249 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1250 debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1251 tmp_sdram_mode, tmp_dunit_control_low);
1252 } else { /* Not sync. */
1254 tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */
1255 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1256 debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1257 tmp_sdram_mode, tmp_dunit_control_low);
1262 if (tmp == 1) { /* Sync */
1263 tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */
1264 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1265 debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1266 tmp_sdram_mode, tmp_dunit_control_low);
1267 } else { /* not sync */
1269 tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */
1270 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1271 debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1272 tmp_sdram_mode, tmp_dunit_control_low);
1277 printf ("Max. CL is out of range %d\n",
1278 info->maxClSupported_DDR);
1285 /* Write results of CL detection procedure */
1286 GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1287 /* set SDRAM mode SetCommand 0x1418 */
1288 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1289 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1290 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1294 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1295 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1296 if (tmp != 1) { /*clocks are not sync */
1298 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1299 (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1300 0x18110780 | tmp_dunit_control_low);
1303 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1304 (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1305 0x00110000 | tmp_dunit_control_low);
1308 /* set SDRAM mode SetCommand 0x1418 */
1309 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1310 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1311 debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
1314 /*------------------------------------------------------------------------------ */
1317 /* bank parameters */
1318 /* SDRAM address decode register */
1319 /* program this with the default value */
1323 debug("drb_size (n*64Mbit): %d\n", info->drb_size);
1324 switch (info->drb_size) {
1325 case 1: /* 64 Mbit */
1326 case 2: /* 128 Mbit */
1327 debug("RAM-Device_size 64Mbit or 128Mbit)\n");
1330 case 4: /* 256 Mbit */
1331 case 8: /* 512 Mbit */
1332 debug("RAM-Device_size 256Mbit or 512Mbit)\n");
1335 case 16: /* 1 Gbit */
1336 case 32: /* 2 Gbit */
1337 debug("RAM-Device_size 1Gbit or 2Gbit)\n");
1341 printf ("Error in dram size calculation\n");
1342 debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
1347 /* SDRAM bank parameters */
1348 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1349 debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
1350 GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1352 /* ------------------------------------------------------------------------------ */
1354 debug("setting up sdram_timing_control_low with: %08x \n",
1356 GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1359 /* ------------------------------------------------------------------------------ */
1361 /* SDRAM configuration */
1362 tmp = GTREGREAD (SDRAM_CONFIG);
1364 if (info->registeredAddrAndControlInputs
1365 || info->registeredDQMBinputs) {
1367 debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1368 info->registeredAddrAndControlInputs,
1369 info->registeredDQMBinputs);
1372 /* Use buffer 1 to return read data to the CPU
1373 * Page 426 MV64360 */
1375 debug("Before Buffer assignment - sdram_conf: %08x\n",
1376 GTREGREAD (SDRAM_CONFIG));
1377 debug("After Buffer assignment - sdram_conf: %08x\n",
1378 GTREGREAD (SDRAM_CONFIG));
1380 /* SDRAM timing To_do: */
1383 tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1384 debug("# sdram_timing_control_high is : %08lx \n", tmp);
1386 /* SDRAM address decode register */
1387 /* program this with the default value */
1388 tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1389 debug("SDRAM address control (before: decode): %08x ",
1390 GTREGREAD (SDRAM_ADDR_CONTROL));
1391 GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1392 debug("SDRAM address control (after: decode): %08x\n",
1393 GTREGREAD (SDRAM_ADDR_CONTROL));
1395 /* set the SDRAM configuration for each bank */
1397 /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1402 debug("\n*** Running a MRS cycle for bank %d ***\n", i);
1405 memory_map_bank (i, 0, GB / 4);
1406 #if 1 /* test only */
1408 tmp = GTREGREAD (SDRAM_MODE);
1409 GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
1410 GT_REG_WRITE (SDRAM_OPERATION, 0x4);
1411 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1412 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1415 GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
1416 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1417 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1418 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1422 l1 += GTREGREAD (SDRAM_OPERATION);
1424 GT_REG_WRITE (SDRAM_MODE, tmp);
1425 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1426 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1427 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1430 /* switch back to normal operation mode */
1431 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1432 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1433 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1436 #endif /* test only */
1437 /* unmap the bank */
1438 memory_map_bank (i, 0, 0);
1445 * Check memory range for valid RAM. A simple memory test determines
1446 * the actually available RAM size between addresses `base' and
1447 * `base + maxsize'. Some (not all) hardware errors are detected:
1448 * - short between address lines
1449 * - short between data lines
1452 dram_size(long int *base, long int maxsize)
1454 volatile long int *addr, *b=base;
1455 long int cnt, val, save1, save2;
1457 #define STARTVAL (1<<20) /* start test at 1M */
1458 for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1459 addr = base + cnt; /* pointer arith! */
1461 save1 = *addr; /* save contents of addr */
1462 save2 = *b; /* save contents of base */
1464 *addr=cnt; /* write cnt to addr */
1465 *b=0; /* put null at base */
1467 /* check at base address */
1469 *addr=save1; /* restore *addr */
1470 *b=save2; /* restore *b */
1473 val = *addr; /* read *addr */
1474 val = *addr; /* read *addr */
1480 debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
1481 /* fix boundary condition.. STARTVAL means zero */
1482 if(cnt==STARTVAL/sizeof(long)) cnt=0;
1483 return (cnt * sizeof(long));
1489 #ifdef CONFIG_MV64360_ECC
1491 * mv_dma_is_channel_active:
1492 * Checks if a engine is busy.
1494 int mv_dma_is_channel_active(int engine)
1498 data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
1499 if (data & BIT14) /* activity status */
1506 * mv_dma_set_memory_space:
1507 * Set a DMA memory window for the DMA's address decoding map.
1509 int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
1510 ulong mem_space_attr, ulong base_address,
1515 /* The base address must be aligned to the size. */
1516 if (base_address % size != 0)
1519 if (size >= 0x10000) {
1521 base_address = (base_address & 0xffff0000);
1522 /* Set the new attributes */
1523 GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
1524 (base_address | mem_space_target |
1526 GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
1527 (size - 1) & 0xffff0000);
1528 temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
1529 GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
1530 (temp & ~(BIT0 << mem_space)));
1540 * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
1542 int mv_dma_transfer(int engine, ulong source_addr,
1543 ulong dest_addr, ulong bytes, ulong command)
1545 ulong eng_off_reg; /* Engine Offset Register */
1548 command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
1550 command = command | ((command >> 6) & 0x7);
1551 eng_off_reg = engine * 4;
1552 GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
1554 GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
1556 GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
1558 command |= BIT12 /* DMA_CHANNEL_ENABLE */
1559 | BIT9; /* DMA_NON_CHAIN_MODE */
1561 /* Activate DMA engine By writting to mv_dma_control_register */
1562 GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
1566 #endif /* of ifdef CONFIG_MV64360_ECC */
1568 /* ppcboot interface function to SDRAM init - this is where all the
1569 * controlling logic happens */
1571 initdram(int board_type)
1573 int checkbank[4] = { [0 ... 3] = 0 };
1574 ulong realsize, total, check;
1575 AUX_MEM_DIMM_INFO dimmInfo1;
1576 AUX_MEM_DIMM_INFO dimmInfo2;
1578 #ifdef CONFIG_MV64360_ECC
1579 ulong dest, mem_space_attr;
1580 #endif /* of ifdef CONFIG_MV64360_ECC */
1582 /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1584 /* check the NHR bit and skip mem init if it's already done */
1585 nhr = get_hid0() & (1 << 16);
1588 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1591 (void)check_dimm(0, &dimmInfo1);
1594 (void)check_dimm(1, &dimmInfo2);
1596 memory_map_bank(0, 0, 0);
1597 memory_map_bank(1, 0, 0);
1598 memory_map_bank(2, 0, 0);
1599 memory_map_bank(3, 0, 0);
1601 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1602 printf("Setup for DIMM1 failed.\n");
1605 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1606 printf("Setup for DIMM2 failed.\n");
1609 /* set the NHR bit */
1610 set_hid0(get_hid0() | (1 << 16));
1612 /* next, size the SDRAM banks */
1614 realsize = total = 0;
1616 if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1617 if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1618 if (dimmInfo1.numOfModuleBanks > 2)
1619 printf("Error, SPD claims DIMM1 has >2 banks\n");
1621 if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1622 if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1623 if (dimmInfo2.numOfModuleBanks > 2)
1624 printf("Error, SPD claims DIMM2 has >2 banks\n");
1626 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1627 /* skip over banks that are not populated */
1628 if (! checkbank[bank_no])
1631 if ((total + check) > CONFIG_SYS_GT_REGS)
1632 check = CONFIG_SYS_GT_REGS - total;
1634 memory_map_bank(bank_no, total, check);
1635 realsize = dram_size((long int *)total, check);
1636 memory_map_bank(bank_no, total, realsize);
1638 #ifdef CONFIG_MV64360_ECC
1639 if (((dimmInfo1.errorCheckType != 0) &&
1640 ((dimmInfo2.errorCheckType != 0) ||
1641 (dimmInfo2.numOfModuleBanks == 0))) &&
1642 (CPCI750_ECC_TEST)) {
1643 printf("ECC Initialization of Bank %d:", bank_no);
1644 mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1645 mv_dma_set_memory_space(0, 0, mem_space_attr, total,
1647 for (dest = total; dest < total + realsize;
1649 mv_dma_transfer(0, total, dest, _8M,
1650 BIT8 | /* DMA_DTL_128BYTES */
1651 BIT3 | /* DMA_HOLD_SOURCE_ADDR */
1652 BIT11); /* DMA_BLOCK_TRANSFER_MODE */
1653 while (mv_dma_is_channel_active(0))
1658 #endif /* of ifdef CONFIG_MV64360_ECC */
1663 /* Setup Ethernet DMA Adress window to DRAM Area */
1667 /* ***************************************************************************************
1669 ! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
1670 ! * This procedure fits only the Atlantis *
1672 ! *************************************************************************************** */
1675 /* ***************************************************************************************
1676 ! * DFCDL initialize MV643xx Design Considerations *
1678 ! *************************************************************************************** */
1679 int set_dfcdlInit (void)
1682 unsigned int dfcdl_word = 0x0000014f;
1684 for (i = 0; i < 64; i++) {
1685 GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1687 GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
1693 int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1695 unsigned int ecc_counter;
1696 unsigned int ecc_addr;
1698 GT_REG_READ(0x1458, &ecc_counter);
1699 GT_REG_READ(0x1450, &ecc_addr);
1700 GT_REG_WRITE(0x1450, 0);
1702 printf("Error Counter since Reset: %8d\n", ecc_counter);
1703 printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8);
1704 if (ecc_addr & 0x01)
1708 printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
1715 show_ecc, 1, 1, do_show_ecc,
1716 "Show Marvell MV64360 ECC Info",
1717 "Show Marvell MV64360 ECC Counter and last error."