git.sur5r.net Git - u-boot/blob - board/esd/cpci750/sdram_init.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * adaption for the Marvell DB64360 Board
  26  * Ingo Assmus (ingo.assmus@keymile.com)
  27  *
  28  * adaption for the cpci750 Board
  29  * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
  30  *************************************************************************/
  31
  32
  33 /* sdram_init.c - automatic memory sizing */
  34
  35 #include <common.h>
  36 #include <74xx_7xx.h>
  37 #include "../../Marvell/include/memory.h"
  38 #include "../../Marvell/include/pci.h"
  39 #include "../../Marvell/include/mv_gen_reg.h"
  40 #include <net.h>
  41
  42 #include "eth.h"
  43 #include "mpsc.h"
  44 #include "../../Marvell/common/i2c.h"
  45 #include "64360.h"
  46 #include "mv_regs.h"
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 #undef  DEBUG
  51 /* #define DEBUG */
  52 #ifdef CONFIG_PCI
  53 #define MAP_PCI
  54 #endif /* of CONFIG_PCI */
  55
  56 #ifdef DEBUG
  57 #define DP(x) x
  58 #else
  59 #define DP(x)
  60 #endif
  61
  62 int set_dfcdlInit(void);        /* setup delay line of Mv64360 */
  63
  64 /* ------------------------------------------------------------------------- */
  65
  66 int
  67 memory_map_bank(unsigned int bankNo,
  68                 unsigned int bankBase,
  69                 unsigned int bankLength)
  70 {
  71 #ifdef MAP_PCI
  72         PCI_HOST host;
  73 #endif
  74
  75
  76 #ifdef DEBUG
  77         if (bankLength > 0) {
  78                 printf("mapping bank %d at %08x - %08x\n",
  79                        bankNo, bankBase, bankBase + bankLength - 1);
  80         } else {
  81                 printf("unmapping bank %d\n", bankNo);
  82         }
  83 #endif
  84
  85         memoryMapBank(bankNo, bankBase, bankLength);
  86
  87 #ifdef MAP_PCI
  88         for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
  89                 const int features=
  90                         PREFETCH_ENABLE |
  91                         DELAYED_READ_ENABLE |
  92                         AGGRESSIVE_PREFETCH |
  93                         READ_LINE_AGGRESSIVE_PREFETCH |
  94                         READ_MULTI_AGGRESSIVE_PREFETCH |
  95                         MAX_BURST_4 |
  96                         PCI_NO_SWAP;
  97
  98                 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
  99
 100                 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
 101                                 bankLength);
 102
 103                 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
 104         }
 105 #endif
 106         return 0;
 107 }
 108
 109 #define GB         (1 << 30)
 110
 111 /* much of this code is based on (or is) the code in the pip405 port */
 112 /* thanks go to the authors of said port - Josh */
 113
 114 /* structure to store the relevant information about an sdram bank */
 115 typedef struct sdram_info {
 116         uchar drb_size;
 117         uchar registered, ecc;
 118         uchar tpar;
 119         uchar tras_clocks;
 120         uchar burst_len;
 121         uchar banks, slot;
 122 } sdram_info_t;
 123
 124 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
 125
 126 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
 127
 128 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
 129                                 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
 130                                } VOLTAGE_INTERFACE;
 131
 132 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
 133 typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
 134
 135
 136 /* SDRAM/DDR information struct */
 137 typedef struct _gtMemoryDimmInfo
 138 {
 139     MEMORY_TYPE          memoryType;
 140     unsigned int         numOfRowAddresses;
 141     unsigned int         numOfColAddresses;
 142     unsigned int         numOfModuleBanks;
 143     unsigned int         dataWidth;
 144     VOLTAGE_INTERFACE    voltageInterface;
 145     unsigned int         errorCheckType;                                /* ECC , PARITY..*/
 146     unsigned int         sdramWidth;                                    /* 4,8,16 or 32 */;
 147     unsigned int         errorCheckDataWidth;                           /* 0 - no, 1 - Yes */
 148     unsigned int         minClkDelay;
 149     unsigned int         burstLengthSupported;
 150     unsigned int         numOfBanksOnEachDevice;
 151     unsigned int         suportedCasLatencies;
 152     unsigned int         RefreshInterval;
 153     unsigned int         maxCASlatencySupported_LoP;                    /* LoP left of point (measured in ns) */
 154     unsigned int         maxCASlatencySupported_RoP;                    /* RoP right of point (measured in ns)*/
 155     MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
 156     MAX_CL_SUPPORTED_SD  maxClSupported_SD;
 157     unsigned int         moduleBankDensity;
 158     /* module attributes (true for yes) */
 159     bool                 bufferedAddrAndControlInputs;
 160     bool                 registeredAddrAndControlInputs;
 161     bool                 onCardPLL;
 162     bool                 bufferedDQMBinputs;
 163     bool                 registeredDQMBinputs;
 164     bool                 differentialClockInput;
 165     bool                 redundantRowAddressing;
 166
 167     /* module general attributes */
 168     bool                 suportedAutoPreCharge;
 169     bool                 suportedPreChargeAll;
 170     bool                 suportedEarlyRasPreCharge;
 171     bool                 suportedWrite1ReadBurst;
 172     bool                 suported5PercentLowVCC;
 173     bool                 suported5PercentUpperVCC;
 174     /* module timing parameters */
 175     unsigned int         minRasToCasDelay;
 176     unsigned int         minRowActiveRowActiveDelay;
 177     unsigned int         minRasPulseWidth;
 178     unsigned int         minRowPrechargeTime;                           /* measured in ns */
 179
 180     int                  addrAndCommandHoldTime;                        /* LoP left of point (measured in ns) */
 181     int                  addrAndCommandSetupTime;                               /* (measured in ns/100) */
 182     int                  dataInputSetupTime;                            /* LoP left of point (measured in ns) */
 183     int                  dataInputHoldTime;                             /* LoP left of point (measured in ns) */
 184 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
 185     unsigned int         clockToDataOut_LoP;                            /* LoP left of point (measured in ns) */
 186     unsigned int         clockToDataOut_RoP;                            /* RoP right of point (measured in ns)*/
 187     unsigned int         clockToDataOutMinus1_LoP;                              /* LoP left of point (measured in ns) */
 188     unsigned int         clockToDataOutMinus1_RoP;                      /* RoP right of point (measured in ns)*/
 189     unsigned int         clockToDataOutMinus2_LoP;                              /* LoP left of point (measured in ns) */
 190     unsigned int         clockToDataOutMinus2_RoP;                      /* RoP right of point (measured in ns)*/
 191
 192     unsigned int         minimumCycleTimeAtMaxCasLatancy_LoP;           /* LoP left of point (measured in ns) */
 193     unsigned int         minimumCycleTimeAtMaxCasLatancy_RoP;           /* RoP right of point (measured in ns)*/
 194
 195     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus1_LoP;     /* LoP left of point (measured in ns) */
 196     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus1_RoP;     /* RoP right of point (measured in ns)*/
 197
 198     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus2_LoP;     /* LoP left of point (measured in ns) */
 199     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus2_RoP;     /* RoP right of point (measured in ns)*/
 200
 201     /* Parameters calculated from
 202        the extracted DIMM information */
 203     unsigned int         size;
 204     unsigned int         deviceDensity;                                 /* 16,64,128,256 or 512 Mbit */
 205     unsigned int         numberOfDevices;
 206     uchar                drb_size;                                      /* DRAM size in n*64Mbit */
 207     uchar                slot;                                          /* Slot Number this module is inserted in */
 208     uchar                spd_raw_data[128];                             /* Content of SPD-EEPROM copied 1:1 */
 209 #ifdef DEBUG
 210     uchar                manufactura[8];                                /* Content of SPD-EEPROM Byte 64-71 */
 211     uchar                modul_id[18];                                  /* Content of SPD-EEPROM Byte 73-90 */
 212     uchar                vendor_data[27];                               /* Content of SPD-EEPROM Byte 99-125 */
 213     unsigned long        modul_serial_no;                               /* Content of SPD-EEPROM Byte 95-98 */
 214     unsigned int         manufac_date;                                  /* Content of SPD-EEPROM Byte 93-94 */
 215     unsigned int         modul_revision;                                /* Content of SPD-EEPROM Byte 91-92 */
 216     uchar                manufac_place;                                 /* Content of SPD-EEPROM Byte 72 */
 217
 218 #endif
 219 } AUX_MEM_DIMM_INFO;
 220
 221
 222 /*
 223  * translate ns.ns/10 coding of SPD timing values
 224  * into 10 ps unit values
 225  */
 226 static inline unsigned short
 227 NS10to10PS(unsigned char spd_byte)
 228 {
 229         unsigned short ns, ns10;
 230
 231         /* isolate upper nibble */
 232         ns = (spd_byte >> 4) & 0x0F;
 233         /* isolate lower nibble */
 234         ns10 = (spd_byte & 0x0F);
 235
 236         return(ns*100 + ns10*10);
 237 }
 238
 239 /*
 240  * translate ns coding of SPD timing values
 241  * into 10 ps unit values
 242  */
 243 static inline unsigned short
 244 NSto10PS(unsigned char spd_byte)
 245 {
 246         return(spd_byte*100);
 247 }
 248
 249 /* This code reads the SPD chip on the sdram and populates
 250  * the array which is passed in with the relevant information */
 251 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 252 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 253 {
 254         unsigned long spd_checksum;
 255
 256         uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 257         int ret;
 258         unsigned int i, j, density = 1, devicesForErrCheck = 0;
 259
 260 #ifdef DEBUG
 261         unsigned int k;
 262 #endif
 263         unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
 264         int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
 265         uchar supp_cal, cal_val;
 266         ulong memclk, tmemclk;
 267         ulong tmp;
 268         uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
 269         uchar data[128];
 270
 271         memclk = gd->bus_clk;
 272         tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
 273
 274         memset (data, 0, sizeof (data));
 275
 276
 277         ret = 0;
 278
 279         DP (puts ("before i2c read\n"));
 280
 281         ret = i2c_read (addr, 0, 2, data, 128);
 282
 283         DP (puts ("after i2c read\n"));
 284
 285         if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
 286             || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
 287             || (data[70] != 'b') || (data[71] != 'h')) {
 288                 ret = -1;
 289         }
 290
 291         if ((ret != 0) && (slot == 0)) {
 292                 memset (data, 0, sizeof (data));
 293                 data[0] = 0x80;
 294                 data[1] = 0x08;
 295                 data[2] = 0x07;
 296                 data[3] = 0x0c;
 297                 data[4] = 0x09;
 298                 data[5] = 0x01;
 299                 data[6] = 0x48;
 300                 data[7] = 0x00;
 301                 data[8] = 0x04;
 302                 data[9] = 0x75;
 303                 data[10] = 0x80;
 304                 data[11] = 0x02;
 305                 data[12] = 0x80;
 306                 data[13] = 0x10;
 307                 data[14] = 0x08;
 308                 data[15] = 0x01;
 309                 data[16] = 0x0e;
 310                 data[17] = 0x04;
 311                 data[18] = 0x0c;
 312                 data[19] = 0x01;
 313                 data[20] = 0x02;
 314                 data[21] = 0x20;
 315                 data[22] = 0x00;
 316                 data[23] = 0xa0;
 317                 data[24] = 0x80;
 318                 data[25] = 0x00;
 319                 data[26] = 0x00;
 320                 data[27] = 0x50;
 321                 data[28] = 0x3c;
 322                 data[29] = 0x50;
 323                 data[30] = 0x32;
 324                 data[31] = 0x10;
 325                 data[32] = 0xb0;
 326                 data[33] = 0xb0;
 327                 data[34] = 0x60;
 328                 data[35] = 0x60;
 329                 data[64] = 'e';
 330                 data[65] = 's';
 331                 data[66] = 'd';
 332                 data[67] = '-';
 333                 data[68] = 'g';
 334                 data[69] = 'm';
 335                 data[70] = 'b';
 336                 data[71] = 'h';
 337                 ret = 0;
 338         }
 339
 340         /* zero all the values */
 341         memset (dimmInfo, 0, sizeof (*dimmInfo));
 342
 343         /* copy the SPD content 1:1 into the dimmInfo structure */
 344         for (i = 0; i <= 127; i++) {
 345                 dimmInfo->spd_raw_data[i] = data[i];
 346         }
 347
 348         if (ret) {
 349                 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
 350                 return 0;
 351         } else
 352                 dimmInfo->slot = slot;  /* start to fill up dimminfo for this "slot" */
 353
 354 #ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
 355
 356         for (i = 0; i <= 127; i++) {
 357                 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
 358                         data[i]);
 359         }
 360
 361 #endif
 362 #ifdef DEBUG
 363         /* find Manufacturer of Dimm Module */
 364         for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
 365                 dimmInfo->manufactura[i] = data[64 + i];
 366         }
 367         printf ("\nThis RAM-Module is produced by:              %s\n",
 368                 dimmInfo->manufactura);
 369
 370         /* find Manul-ID of Dimm Module */
 371         for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
 372                 dimmInfo->modul_id[i] = data[73 + i];
 373         }
 374         printf ("The Module-ID of this RAM-Module is:           %s\n",
 375                 dimmInfo->modul_id);
 376
 377         /* find Vendor-Data of Dimm Module */
 378         for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
 379                 dimmInfo->vendor_data[i] = data[99 + i];
 380         }
 381         printf ("Vendor Data of this RAM-Module is:             %s\n",
 382                 dimmInfo->vendor_data);
 383
 384         /* find modul_serial_no of Dimm Module */
 385         dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
 386         printf ("Serial No. of this RAM-Module is:              %ld (%lx)\n",
 387                 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 388
 389         /* find Manufac-Data of Dimm Module */
 390         dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
 391         printf ("Manufactoring Date of this RAM-Module is:      %d.%d\n", data[93], data[94]);  /*dimmInfo->manufac_date */
 392
 393         /* find modul_revision of Dimm Module */
 394         dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
 395         printf ("Module Revision of this RAM-Module is:                 %d.%d\n", data[91], data[92]);  /* dimmInfo->modul_revision */
 396
 397         /* find manufac_place of Dimm Module */
 398         dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
 399         printf ("manufac_place of this RAM-Module is:           %d\n",
 400                 dimmInfo->manufac_place);
 401
 402 #endif
 403 /*------------------------------------------------------------------------------------------------------------------------------*/
 404 /* calculate SPD checksum */
 405 /*------------------------------------------------------------------------------------------------------------------------------*/
 406         spd_checksum = 0;
 407 #if 0                           /* test-only */
 408         for (i = 0; i <= 62; i++) {
 409                 spd_checksum += data[i];
 410         }
 411
 412         if ((spd_checksum & 0xff) != data[63]) {
 413                 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
 414                 hang ();
 415         }
 416
 417         else
 418                 printf ("SPD Checksum ok!\n");
 419 #endif /* test-only */
 420
 421 /*------------------------------------------------------------------------------------------------------------------------------*/
 422         for (i = 2; i <= 35; i++) {
 423                 switch (i) {
 424                 case 2: /* Memory type (DDR / SDRAM) */
 425                         dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
 426 #ifdef DEBUG
 427                         if (dimmInfo->memoryType == 0)
 428                                 DP (printf
 429                                     ("Dram_type in slot %d is:                  SDRAM\n",
 430                                      dimmInfo->slot));
 431                         if (dimmInfo->memoryType == 1)
 432                                 DP (printf
 433                                     ("Dram_type in slot %d is:                  DDRAM\n",
 434                                      dimmInfo->slot));
 435 #endif
 436                         break;
 437 /*------------------------------------------------------------------------------------------------------------------------------*/
 438
 439                 case 3: /* Number Of Row Addresses */
 440                         dimmInfo->numOfRowAddresses = data[i];
 441                         DP (printf
 442                             ("Module Number of row addresses:           %d\n",
 443                              dimmInfo->numOfRowAddresses));
 444                         break;
 445 /*------------------------------------------------------------------------------------------------------------------------------*/
 446
 447                 case 4: /* Number Of Column Addresses */
 448                         dimmInfo->numOfColAddresses = data[i];
 449                         DP (printf
 450                             ("Module Number of col addresses:           %d\n",
 451                              dimmInfo->numOfColAddresses));
 452                         break;
 453 /*------------------------------------------------------------------------------------------------------------------------------*/
 454
 455                 case 5: /* Number Of Module Banks */
 456                         dimmInfo->numOfModuleBanks = data[i];
 457                         DP (printf
 458                             ("Number of Banks on Mod. :                                 %d\n",
 459                              dimmInfo->numOfModuleBanks));
 460                         break;
 461 /*------------------------------------------------------------------------------------------------------------------------------*/
 462
 463                 case 6: /* Data Width */
 464                         dimmInfo->dataWidth = data[i];
 465                         DP (printf
 466                             ("Module Data Width:                                %d\n",
 467                              dimmInfo->dataWidth));
 468                         break;
 469 /*------------------------------------------------------------------------------------------------------------------------------*/
 470
 471                 case 8: /* Voltage Interface */
 472                         switch (data[i]) {
 473                         case 0x0:
 474                                 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
 475                                 DP (printf
 476                                     ("Module is                                         TTL_5V_TOLERANT\n"));
 477                                 break;
 478                         case 0x1:
 479                                 dimmInfo->voltageInterface = LVTTL;
 480                                 DP (printf
 481                                     ("Module is                                         LVTTL\n"));
 482                                 break;
 483                         case 0x2:
 484                                 dimmInfo->voltageInterface = HSTL_1_5V;
 485                                 DP (printf
 486                                     ("Module is                                         TTL_5V_TOLERANT\n"));
 487                                 break;
 488                         case 0x3:
 489                                 dimmInfo->voltageInterface = SSTL_3_3V;
 490                                 DP (printf
 491                                     ("Module is                                         HSTL_1_5V\n"));
 492                                 break;
 493                         case 0x4:
 494                                 dimmInfo->voltageInterface = SSTL_2_5V;
 495                                 DP (printf
 496                                     ("Module is                                         SSTL_2_5V\n"));
 497                                 break;
 498                         default:
 499                                 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
 500                                 DP (printf
 501                                     ("Module is                                         VOLTAGE_UNKNOWN\n"));
 502                                 break;
 503                         }
 504                         break;
 505 /*------------------------------------------------------------------------------------------------------------------------------*/
 506
 507                 case 9: /* Minimum Cycle Time At Max CasLatancy */
 508                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 509                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 510                         maskLeftOfPoint =
 511                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 512                         maskRightOfPoint =
 513                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 514                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 515                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 516                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
 517                                 leftOfPoint;
 518                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
 519                                 rightOfPoint;
 520                         DP (printf
 521                             ("Minimum Cycle Time At Max CasLatancy:             %d.%d [ns]\n",
 522                              leftOfPoint, rightOfPoint));
 523                         break;
 524 /*------------------------------------------------------------------------------------------------------------------------------*/
 525
 526                 case 10:        /* Clock To Data Out */
 527                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 528                         time_tmp =
 529                                 (((data[i] & 0xf0) >> 4) * 10) +
 530                                 ((data[i] & 0x0f));
 531                         leftOfPoint = time_tmp / div;
 532                         rightOfPoint = time_tmp % div;
 533                         dimmInfo->clockToDataOut_LoP = leftOfPoint;
 534                         dimmInfo->clockToDataOut_RoP = rightOfPoint;
 535                         DP (printf
 536                             ("Clock To Data Out:                                %d.%2d [ns]\n",
 537                              leftOfPoint, rightOfPoint));
 538                         /*dimmInfo->clockToDataOut */
 539                         break;
 540 /*------------------------------------------------------------------------------------------------------------------------------*/
 541
 542 #ifdef CONFIG_ECC
 543                 case 11:        /* Error Check Type */
 544                         dimmInfo->errorCheckType = data[i];
 545                         DP (printf
 546                             ("Error Check Type (0=NONE):                        %d\n",
 547                              dimmInfo->errorCheckType));
 548                         break;
 549 #endif
 550 /*------------------------------------------------------------------------------------------------------------------------------*/
 551
 552                 case 12:        /* Refresh Interval */
 553                         dimmInfo->RefreshInterval = data[i];
 554                         DP (printf
 555                             ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
 556                              dimmInfo->RefreshInterval));
 557                         break;
 558 /*------------------------------------------------------------------------------------------------------------------------------*/
 559
 560                 case 13:        /* Sdram Width */
 561                         dimmInfo->sdramWidth = data[i];
 562                         DP (printf
 563                             ("Sdram Width:                                      %d\n",
 564                              dimmInfo->sdramWidth));
 565                         break;
 566 /*------------------------------------------------------------------------------------------------------------------------------*/
 567
 568                 case 14:        /* Error Check Data Width */
 569                         dimmInfo->errorCheckDataWidth = data[i];
 570                         DP (printf
 571                             ("Error Check Data Width:                   %d\n",
 572                              dimmInfo->errorCheckDataWidth));
 573                         break;
 574 /*------------------------------------------------------------------------------------------------------------------------------*/
 575
 576                 case 15:        /* Minimum Clock Delay */
 577                         dimmInfo->minClkDelay = data[i];
 578                         DP (printf
 579                             ("Minimum Clock Delay:                              %d\n",
 580                              dimmInfo->minClkDelay));
 581                         break;
 582 /*------------------------------------------------------------------------------------------------------------------------------*/
 583
 584                 case 16:        /* Burst Length Supported */
 585                            /******-******-******-*******
 586                            * bit3 | bit2 | bit1 | bit0 *
 587                            *******-******-******-*******
 588             burst length = *  8   |  4   |   2  |   1  *
 589                            *****************************
 590
 591             If for example bit0 and bit2 are set, the burst
 592             length supported are 1 and 4. */
 593
 594                         dimmInfo->burstLengthSupported = data[i];
 595 #ifdef DEBUG
 596                         DP (printf
 597                             ("Burst Length Supported:                   "));
 598                         if (dimmInfo->burstLengthSupported & 0x01)
 599                                 DP (printf ("1, "));
 600                         if (dimmInfo->burstLengthSupported & 0x02)
 601                                 DP (printf ("2, "));
 602                         if (dimmInfo->burstLengthSupported & 0x04)
 603                                 DP (printf ("4, "));
 604                         if (dimmInfo->burstLengthSupported & 0x08)
 605                                 DP (printf ("8, "));
 606                         DP (printf (" Bit \n"));
 607 #endif
 608                         break;
 609 /*------------------------------------------------------------------------------------------------------------------------------*/
 610
 611                 case 17:        /* Number Of Banks On Each Device */
 612                         dimmInfo->numOfBanksOnEachDevice = data[i];
 613                         DP (printf
 614                             ("Number Of Banks On Each Chip:                     %d\n",
 615                              dimmInfo->numOfBanksOnEachDevice));
 616                         break;
 617 /*------------------------------------------------------------------------------------------------------------------------------*/
 618
 619                 case 18:        /* Suported Cas Latencies */
 620
 621                         /*     DDR:
 622                          *******-******-******-******-******-******-******-*******
 623                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 624                          *******-******-******-******-******-******-******-*******
 625                          CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 626                          *********************************************************
 627                          SDRAM:
 628                          *******-******-******-******-******-******-******-*******
 629                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 630                          *******-******-******-******-******-******-******-*******
 631                          CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
 632                          ********************************************************/
 633                         dimmInfo->suportedCasLatencies = data[i];
 634 #ifdef DEBUG
 635                         DP (printf
 636                             ("Suported Cas Latencies: (CL)                      "));
 637                         if (dimmInfo->memoryType == 0) {        /* SDRAM */
 638                                 for (k = 0; k <= 7; k++) {
 639                                         if (dimmInfo->
 640                                             suportedCasLatencies & (1 << k))
 641                                                 DP (printf
 642                                                     ("%d,                       ",
 643                                                      k + 1));
 644                                 }
 645
 646                         } else {        /* DDR-RAM */
 647
 648                                 if (dimmInfo->suportedCasLatencies & 1)
 649                                         DP (printf ("1, "));
 650                                 if (dimmInfo->suportedCasLatencies & 2)
 651                                         DP (printf ("1.5, "));
 652                                 if (dimmInfo->suportedCasLatencies & 4)
 653                                         DP (printf ("2, "));
 654                                 if (dimmInfo->suportedCasLatencies & 8)
 655                                         DP (printf ("2.5, "));
 656                                 if (dimmInfo->suportedCasLatencies & 16)
 657                                         DP (printf ("3, "));
 658                                 if (dimmInfo->suportedCasLatencies & 32)
 659                                         DP (printf ("3.5, "));
 660
 661                         }
 662                         DP (printf ("\n"));
 663 #endif
 664                         /* Calculating MAX CAS latency */
 665                         for (j = 7; j > 0; j--) {
 666                                 if (((dimmInfo->
 667                                       suportedCasLatencies >> j) & 0x1) ==
 668                                     1) {
 669                                         switch (dimmInfo->memoryType) {
 670                                         case DDR:
 671                                                 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
 672                                                 switch (j) {
 673                                                 case 7:
 674                                                         DP (printf
 675                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n"));
 676                                                         dimmInfo->
 677                                                                 maxClSupported_DDR
 678                                                                 =
 679                                                                 DDR_CL_FAULT;
 680                                                         hang ();
 681                                                         break;
 682                                                 case 6:
 683                                                         DP (printf
 684                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n"));
 685                                                         dimmInfo->
 686                                                                 maxClSupported_DDR
 687                                                                 =
 688                                                                 DDR_CL_FAULT;
 689                                                         hang ();
 690                                                         break;
 691                                                 case 5:
 692                                                         DP (printf
 693                                                             ("Max. Cas Latencies (DDR):                         3.5 clk's\n"));
 694                                                         dimmInfo->
 695                                                                 maxClSupported_DDR
 696                                                                 = DDR_CL_3_5;
 697                                                         break;
 698                                                 case 4:
 699                                                         DP (printf
 700                                                             ("Max. Cas Latencies (DDR):                         3 clk's \n"));
 701                                                         dimmInfo->
 702                                                                 maxClSupported_DDR
 703                                                                 = DDR_CL_3;
 704                                                         break;
 705                                                 case 3:
 706                                                         DP (printf
 707                                                             ("Max. Cas Latencies (DDR):                         2.5 clk's \n"));
 708                                                         dimmInfo->
 709                                                                 maxClSupported_DDR
 710                                                                 = DDR_CL_2_5;
 711                                                         break;
 712                                                 case 2:
 713                                                         DP (printf
 714                                                             ("Max. Cas Latencies (DDR):                         2 clk's \n"));
 715                                                         dimmInfo->
 716                                                                 maxClSupported_DDR
 717                                                                 = DDR_CL_2;
 718                                                         break;
 719                                                 case 1:
 720                                                         DP (printf
 721                                                             ("Max. Cas Latencies (DDR):                         1.5 clk's \n"));
 722                                                         dimmInfo->
 723                                                                 maxClSupported_DDR
 724                                                                 = DDR_CL_1_5;
 725                                                         break;
 726                                                 }
 727                                                 dimmInfo->
 728                                                         maxCASlatencySupported_LoP
 729                                                         =
 730                                                         1 +
 731                                                         (int) (5 * j / 10);
 732                                                 if (((5 * j) % 10) != 0)
 733                                                         dimmInfo->
 734                                                                 maxCASlatencySupported_RoP
 735                                                                 = 5;
 736                                                 else
 737                                                         dimmInfo->
 738                                                                 maxCASlatencySupported_RoP
 739                                                                 = 0;
 740                                                 DP (printf
 741                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation):        %d.%d \n",
 742                                                      dimmInfo->
 743                                                      maxCASlatencySupported_LoP,
 744                                                      dimmInfo->
 745                                                      maxCASlatencySupported_RoP));
 746                                                 break;
 747                                         case SDRAM:
 748                                                 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
 749                                                 dimmInfo->maxClSupported_SD = j;        /*  Cas Latency DDR-RAM Coded                   */
 750                                                 DP (printf
 751                                                     ("Max. Cas Latencies (SD): %d\n",
 752                                                      dimmInfo->
 753                                                      maxClSupported_SD));
 754                                                 dimmInfo->
 755                                                         maxCASlatencySupported_LoP
 756                                                         = j;
 757                                                 dimmInfo->
 758                                                         maxCASlatencySupported_RoP
 759                                                         = 0;
 760                                                 DP (printf
 761                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
 762                                                      dimmInfo->
 763                                                      maxCASlatencySupported_LoP,
 764                                                      dimmInfo->
 765                                                      maxCASlatencySupported_RoP));
 766                                                 break;
 767                                         }
 768                                         break;
 769                                 }
 770                         }
 771                         break;
 772 /*------------------------------------------------------------------------------------------------------------------------------*/
 773
 774                 case 21:        /* Buffered Address And Control Inputs */
 775                         DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
 776                         dimmInfo->bufferedAddrAndControlInputs =
 777                                 data[i] & BIT0;
 778                         dimmInfo->registeredAddrAndControlInputs =
 779                                 (data[i] & BIT1) >> 1;
 780                         dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
 781                         dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
 782                         dimmInfo->registeredDQMBinputs =
 783                                 (data[i] & BIT4) >> 4;
 784                         dimmInfo->differentialClockInput =
 785                                 (data[i] & BIT5) >> 5;
 786                         dimmInfo->redundantRowAddressing =
 787                                 (data[i] & BIT6) >> 6;
 788 #ifdef DEBUG
 789                         if (dimmInfo->bufferedAddrAndControlInputs == 1)
 790                                 DP (printf
 791                                     (" - Buffered Address/Control Input:                Yes \n"));
 792                         else
 793                                 DP (printf
 794                                     (" - Buffered Address/Control Input:                No \n"));
 795
 796                         if (dimmInfo->registeredAddrAndControlInputs == 1)
 797                                 DP (printf
 798                                     (" - Registered Address/Control Input:              Yes \n"));
 799                         else
 800                                 DP (printf
 801                                     (" - Registered Address/Control Input:              No \n"));
 802
 803                         if (dimmInfo->onCardPLL == 1)
 804                                 DP (printf
 805                                     (" - On-Card PLL (clock):                           Yes \n"));
 806                         else
 807                                 DP (printf
 808                                     (" - On-Card PLL (clock):                           No \n"));
 809
 810                         if (dimmInfo->bufferedDQMBinputs == 1)
 811                                 DP (printf
 812                                     (" - Bufferd DQMB Inputs:                           Yes \n"));
 813                         else
 814                                 DP (printf
 815                                     (" - Bufferd DQMB Inputs:                           No \n"));
 816
 817                         if (dimmInfo->registeredDQMBinputs == 1)
 818                                 DP (printf
 819                                     (" - Registered DQMB Inputs:                        Yes \n"));
 820                         else
 821                                 DP (printf
 822                                     (" - Registered DQMB Inputs:                        No \n"));
 823
 824                         if (dimmInfo->differentialClockInput == 1)
 825                                 DP (printf
 826                                     (" - Differential Clock Input:                      Yes \n"));
 827                         else
 828                                 DP (printf
 829                                     (" - Differential Clock Input:                      No \n"));
 830
 831                         if (dimmInfo->redundantRowAddressing == 1)
 832                                 DP (printf
 833                                     (" - redundant Row Addressing:                      Yes \n"));
 834                         else
 835                                 DP (printf
 836                                     (" - redundant Row Addressing:                      No \n"));
 837
 838 #endif
 839                         break;
 840 /*------------------------------------------------------------------------------------------------------------------------------*/
 841
 842                 case 22:        /* Suported AutoPreCharge */
 843                         DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
 844                         dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
 845                         dimmInfo->suportedAutoPreCharge =
 846                                 (data[i] & BIT1) >> 1;
 847                         dimmInfo->suportedPreChargeAll =
 848                                 (data[i] & BIT2) >> 2;
 849                         dimmInfo->suportedWrite1ReadBurst =
 850                                 (data[i] & BIT3) >> 3;
 851                         dimmInfo->suported5PercentLowVCC =
 852                                 (data[i] & BIT4) >> 4;
 853                         dimmInfo->suported5PercentUpperVCC =
 854                                 (data[i] & BIT5) >> 5;
 855 #ifdef DEBUG
 856                         if (dimmInfo->suportedEarlyRasPreCharge == 1)
 857                                 DP (printf
 858                                     (" - Early Ras Precharge:                   Yes \n"));
 859                         else
 860                                 DP (printf
 861                                     (" -  Early Ras Precharge:                  No \n"));
 862
 863                         if (dimmInfo->suportedAutoPreCharge == 1)
 864                                 DP (printf
 865                                     (" - AutoPreCharge:                         Yes \n"));
 866                         else
 867                                 DP (printf
 868                                     (" -  AutoPreCharge:                                No \n"));
 869
 870                         if (dimmInfo->suportedPreChargeAll == 1)
 871                                 DP (printf
 872                                     (" - Precharge All:                         Yes \n"));
 873                         else
 874                                 DP (printf
 875                                     (" -  Precharge All:                                No \n"));
 876
 877                         if (dimmInfo->suportedWrite1ReadBurst == 1)
 878                                 DP (printf
 879                                     (" - Write 1/ReadBurst:                             Yes \n"));
 880                         else
 881                                 DP (printf
 882                                     (" -  Write 1/ReadBurst:                            No \n"));
 883
 884                         if (dimmInfo->suported5PercentLowVCC == 1)
 885                                 DP (printf
 886                                     (" - lower VCC tolerance:                   5 Percent \n"));
 887                         else
 888                                 DP (printf
 889                                     ("  - lower VCC tolerance:                  10 Percent \n"));
 890
 891                         if (dimmInfo->suported5PercentUpperVCC == 1)
 892                                 DP (printf
 893                                     (" - upper VCC tolerance:                   5 Percent \n"));
 894                         else
 895                                 DP (printf
 896                                     (" -  upper VCC tolerance:                  10 Percent \n"));
 897
 898 #endif
 899                         break;
 900 /*------------------------------------------------------------------------------------------------------------------------------*/
 901
 902                 case 23:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
 903                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 904                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 905                         maskLeftOfPoint =
 906                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 907                         maskRightOfPoint =
 908                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 909                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 910                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 911                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
 912                                 leftOfPoint;
 913                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
 914                                 rightOfPoint;
 915                         DP (printf
 916                             ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 917                              leftOfPoint, rightOfPoint));
 918                         /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 919                         break;
 920 /*------------------------------------------------------------------------------------------------------------------------------*/
 921
 922                 case 24:        /* Clock To Data Out 2nd highest Cas Latency Value */
 923                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 924                         time_tmp =
 925                                 (((data[i] & 0xf0) >> 4) * 10) +
 926                                 ((data[i] & 0x0f));
 927                         leftOfPoint = time_tmp / div;
 928                         rightOfPoint = time_tmp % div;
 929                         dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
 930                         dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
 931                         DP (printf
 932                             ("Clock To Data Out (2nd CL value):                 %d.%2d [ns]\n",
 933                              leftOfPoint, rightOfPoint));
 934                         break;
 935 /*------------------------------------------------------------------------------------------------------------------------------*/
 936
 937                 case 25:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
 938                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 939                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 940                         maskLeftOfPoint =
 941                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 942                         maskRightOfPoint =
 943                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 944                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 945                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 946                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
 947                                 leftOfPoint;
 948                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
 949                                 rightOfPoint;
 950                         DP (printf
 951                             ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 952                              leftOfPoint, rightOfPoint));
 953                         /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 954                         break;
 955 /*------------------------------------------------------------------------------------------------------------------------------*/
 956
 957                 case 26:        /* Clock To Data Out 3rd highest Cas Latency Value */
 958                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 959                         time_tmp =
 960                                 (((data[i] & 0xf0) >> 4) * 10) +
 961                                 ((data[i] & 0x0f));
 962                         leftOfPoint = time_tmp / div;
 963                         rightOfPoint = time_tmp % div;
 964                         dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
 965                         dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
 966                         DP (printf
 967                             ("Clock To Data Out (3rd CL value):                 %d.%2d [ns]\n",
 968                              leftOfPoint, rightOfPoint));
 969                         break;
 970 /*------------------------------------------------------------------------------------------------------------------------------*/
 971
 972                 case 27:        /* Minimum Row Precharge Time */
 973                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 974                         maskLeftOfPoint =
 975                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 976                         maskRightOfPoint =
 977                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 978                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 979                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 980
 981                         dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);   /* measured in n times 10ps Intervals */
 982                         trp_clocks =
 983                                 (dimmInfo->minRowPrechargeTime +
 984                                  (tmemclk - 1)) / tmemclk;
 985                         DP (printf
 986                             ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
 987                              tmemclk, tmemclk / 100, tmemclk % 100));
 988                         DP (printf
 989                             ("Minimum Row Precharge Time [ns]:          %d.%2d = in Clk cycles %d\n",
 990                              leftOfPoint, rightOfPoint, trp_clocks));
 991                         break;
 992 /*------------------------------------------------------------------------------------------------------------------------------*/
 993
 994                 case 28:        /* Minimum Row Active to Row Active Time */
 995                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 996                         maskLeftOfPoint =
 997                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 998                         maskRightOfPoint =
 999                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1000                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1001                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1002
1003                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
1004                         trrd_clocks =
1005                                 (dimmInfo->minRowActiveRowActiveDelay +
1006                                  (tmemclk - 1)) / tmemclk;
1007                         DP (printf
1008                             ("Minimum Row Active -To- Row Active Delay [ns]:    %d.%2d = in Clk cycles %d\n",
1009                              leftOfPoint, rightOfPoint, trp_clocks));
1010                         break;
1011 /*------------------------------------------------------------------------------------------------------------------------------*/
1012
1013                 case 29:        /* Minimum Ras-To-Cas Delay */
1014                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
1015                         maskLeftOfPoint =
1016                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1017                         maskRightOfPoint =
1018                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1019                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1020                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1021
1022                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
1023                         trcd_clocks =
1024                                 (dimmInfo->minRowActiveRowActiveDelay +
1025                                  (tmemclk - 1)) / tmemclk;
1026                         DP (printf
1027                             ("Minimum Ras-To-Cas Delay [ns]:                    %d.%2d = in Clk cycles %d\n",
1028                              leftOfPoint, rightOfPoint, trp_clocks));
1029                         break;
1030 /*------------------------------------------------------------------------------------------------------------------------------*/
1031
1032                 case 30:        /* Minimum Ras Pulse Width */
1033                         dimmInfo->minRasPulseWidth = data[i];
1034                         tras_clocks =
1035                                 (NSto10PS (data[i]) +
1036                                  (tmemclk - 1)) / tmemclk;
1037                         DP (printf
1038                             ("Minimum Ras Pulse Width [ns]:                     %d = in Clk cycles %d\n",
1039                              dimmInfo->minRasPulseWidth, tras_clocks));
1040
1041                         break;
1042 /*------------------------------------------------------------------------------------------------------------------------------*/
1043
1044                 case 31:        /* Module Bank Density */
1045                         dimmInfo->moduleBankDensity = data[i];
1046                         DP (printf
1047                             ("Module Bank Density:                              %d\n",
1048                              dimmInfo->moduleBankDensity));
1049 #ifdef DEBUG
1050                         DP (printf
1051                             ("*** Offered Densities (more than 1 = Multisize-Module): "));
1052                         {
1053                                 if (dimmInfo->moduleBankDensity & 1)
1054                                         DP (printf ("4MB, "));
1055                                 if (dimmInfo->moduleBankDensity & 2)
1056                                         DP (printf ("8MB, "));
1057                                 if (dimmInfo->moduleBankDensity & 4)
1058                                         DP (printf ("16MB, "));
1059                                 if (dimmInfo->moduleBankDensity & 8)
1060                                         DP (printf ("32MB, "));
1061                                 if (dimmInfo->moduleBankDensity & 16)
1062                                         DP (printf ("64MB, "));
1063                                 if (dimmInfo->moduleBankDensity & 32)
1064                                         DP (printf ("128MB, "));
1065                                 if ((dimmInfo->moduleBankDensity & 64)
1066                                     || (dimmInfo->moduleBankDensity & 128)) {
1067                                         DP (printf ("ERROR, "));
1068                                         hang ();
1069                                 }
1070                         }
1071                         DP (printf ("\n"));
1072 #endif
1073                         break;
1074 /*------------------------------------------------------------------------------------------------------------------------------*/
1075
1076                 case 32:        /* Address And Command Setup Time (measured in ns/1000) */
1077                         sign = 1;
1078                         switch (dimmInfo->memoryType) {
1079                         case DDR:
1080                                 time_tmp =
1081                                         (((data[i] & 0xf0) >> 4) * 10) +
1082                                         ((data[i] & 0x0f));
1083                                 leftOfPoint = time_tmp / 100;
1084                                 rightOfPoint = time_tmp % 100;
1085                                 break;
1086                         case SDRAM:
1087                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1088                                 if (leftOfPoint > 7) {
1089                                         leftOfPoint = data[i] & 0x70 >> 4;
1090                                         sign = -1;
1091                                 }
1092                                 rightOfPoint = (data[i] & 0x0f);
1093                                 break;
1094                         }
1095                         dimmInfo->addrAndCommandSetupTime =
1096                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1097                         DP (printf
1098                             ("Address And Command Setup Time [ns]:              %d.%d\n",
1099                              sign * leftOfPoint, rightOfPoint));
1100                         break;
1101 /*------------------------------------------------------------------------------------------------------------------------------*/
1102
1103                 case 33:        /* Address And Command Hold Time */
1104                         sign = 1;
1105                         switch (dimmInfo->memoryType) {
1106                         case DDR:
1107                                 time_tmp =
1108                                         (((data[i] & 0xf0) >> 4) * 10) +
1109                                         ((data[i] & 0x0f));
1110                                 leftOfPoint = time_tmp / 100;
1111                                 rightOfPoint = time_tmp % 100;
1112                                 break;
1113                         case SDRAM:
1114                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1115                                 if (leftOfPoint > 7) {
1116                                         leftOfPoint = data[i] & 0x70 >> 4;
1117                                         sign = -1;
1118                                 }
1119                                 rightOfPoint = (data[i] & 0x0f);
1120                                 break;
1121                         }
1122                         dimmInfo->addrAndCommandHoldTime =
1123                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1124                         DP (printf
1125                             ("Address And Command Hold Time [ns]:               %d.%d\n",
1126                              sign * leftOfPoint, rightOfPoint));
1127                         break;
1128 /*------------------------------------------------------------------------------------------------------------------------------*/
1129
1130                 case 34:        /* Data Input Setup Time */
1131                         sign = 1;
1132                         switch (dimmInfo->memoryType) {
1133                         case DDR:
1134                                 time_tmp =
1135                                         (((data[i] & 0xf0) >> 4) * 10) +
1136                                         ((data[i] & 0x0f));
1137                                 leftOfPoint = time_tmp / 100;
1138                                 rightOfPoint = time_tmp % 100;
1139                                 break;
1140                         case SDRAM:
1141                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1142                                 if (leftOfPoint > 7) {
1143                                         leftOfPoint = data[i] & 0x70 >> 4;
1144                                         sign = -1;
1145                                 }
1146                                 rightOfPoint = (data[i] & 0x0f);
1147                                 break;
1148                         }
1149                         dimmInfo->dataInputSetupTime =
1150                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1151                         DP (printf
1152                             ("Data Input Setup Time [ns]:                       %d.%d\n",
1153                              sign * leftOfPoint, rightOfPoint));
1154                         break;
1155 /*------------------------------------------------------------------------------------------------------------------------------*/
1156
1157                 case 35:        /* Data Input Hold Time */
1158                         sign = 1;
1159                         switch (dimmInfo->memoryType) {
1160                         case DDR:
1161                                 time_tmp =
1162                                         (((data[i] & 0xf0) >> 4) * 10) +
1163                                         ((data[i] & 0x0f));
1164                                 leftOfPoint = time_tmp / 100;
1165                                 rightOfPoint = time_tmp % 100;
1166                                 break;
1167                         case SDRAM:
1168                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1169                                 if (leftOfPoint > 7) {
1170                                         leftOfPoint = data[i] & 0x70 >> 4;
1171                                         sign = -1;
1172                                 }
1173                                 rightOfPoint = (data[i] & 0x0f);
1174                                 break;
1175                         }
1176                         dimmInfo->dataInputHoldTime =
1177                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1178                         DP (printf
1179                             ("Data Input Hold Time [ns]:                        %d.%d\n\n",
1180                              sign * leftOfPoint, rightOfPoint));
1181                         break;
1182 /*------------------------------------------------------------------------------------------------------------------------------*/
1183                 }
1184         }
1185         /* calculating the sdram density */
1186         for (i = 0;
1187              i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1188              i++) {
1189                 density = density * 2;
1190         }
1191         dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1192                 dimmInfo->sdramWidth;
1193         dimmInfo->numberOfDevices =
1194                 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1195                 dimmInfo->numOfModuleBanks;
1196         devicesForErrCheck =
1197                 (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1198         if ((dimmInfo->errorCheckType == 0x1)
1199             || (dimmInfo->errorCheckType == 0x2)
1200             || (dimmInfo->errorCheckType == 0x3)) {
1201                 dimmInfo->size =
1202                         (dimmInfo->deviceDensity / 8) *
1203                         (dimmInfo->numberOfDevices - devicesForErrCheck);
1204         } else {
1205                 dimmInfo->size =
1206                         (dimmInfo->deviceDensity / 8) *
1207                         dimmInfo->numberOfDevices;
1208         }
1209
1210         /* compute the module DRB size */
1211         tmp = (1 <<
1212                (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1213         tmp *= dimmInfo->numOfModuleBanks;
1214         tmp *= dimmInfo->sdramWidth;
1215         tmp = tmp >> 24;        /* div by 0x4000000 (64M)       */
1216         dimmInfo->drb_size = (uchar) tmp;
1217         DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
1218
1219         /* try a CAS latency of 3 first... */
1220
1221         /* bit 1 is CL2, bit 2 is CL3 */
1222         supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1223
1224         cal_val = 0;
1225         if (supp_cal & 8) {
1226                 if (NS10to10PS (data[9]) <= tmemclk)
1227                         cal_val = 6;
1228         }
1229         if (supp_cal & 4) {
1230                 if (NS10to10PS (data[9]) <= tmemclk)
1231                         cal_val = 5;
1232         }
1233
1234         /* then 2... */
1235         if (supp_cal & 2) {
1236                 if (NS10to10PS (data[23]) <= tmemclk)
1237                         cal_val = 4;
1238         }
1239
1240         DP (printf ("cal_val = %d\n", cal_val * 5));
1241
1242         /* bummer, did't work... */
1243         if (cal_val == 0) {
1244                 DP (printf ("Couldn't find a good CAS latency\n"));
1245                 hang ();
1246                 return 0;
1247         }
1248
1249         return true;
1250 }
1251
1252 /* sets up the GT properly with information passed in */
1253 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1254 {
1255         ulong tmp, check;
1256         ulong tmp_sdram_mode = 0;       /* 0x141c */
1257         ulong tmp_dunit_control_low = 0;        /* 0x1404 */
1258         int i;
1259
1260         /* sanity checking */
1261         if (!info->numOfModuleBanks) {
1262                 printf ("setup_sdram called with 0 banks\n");
1263                 return 1;
1264         }
1265
1266         /* delay line */
1267
1268         /* Program the GT with the discovered data */
1269         if (info->registeredAddrAndControlInputs == true)
1270                 DP (printf
1271                     ("Module is registered, but we do not support registered Modules !!!\n"));
1272
1273
1274         /* delay line */
1275         set_dfcdlInit ();       /* may be its not needed */
1276         DP (printf ("Delay line set done\n"));
1277
1278         /* set SDRAM mode NOP */ /* To_do check it */
1279         GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1280         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1281                 DP (printf
1282                     ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
1283         }
1284
1285         /* SDRAM configuration */
1286         GT_REG_WRITE (SDRAM_CONFIG, 0x58200400);
1287         DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
1288
1289         /* SDRAM open pages controll keep open as much as I can */
1290         GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1291         DP (printf
1292             ("sdram_open_pages_controll 0x1414: %08x\n",
1293              GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
1294
1295
1296         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1297         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1298         if (tmp == 0)
1299                 DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
1300         else
1301                 DP (printf
1302                     ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
1303
1304         /* SDRAM set CAS Lentency according to SPD information */
1305         switch (info->memoryType) {
1306         case SDRAM:
1307                 DP (printf ("### SD-RAM not supported yet !!!\n"));
1308                 hang ();
1309                 /* ToDo fill SD-RAM if needed !!!!! */
1310                 break;
1311
1312         case DDR:
1313                 DP (printf ("### SET-CL for DDR-RAM\n"));
1314
1315                 switch (info->maxClSupported_DDR) {
1316                 case DDR_CL_3:
1317                         tmp_dunit_control_low = 0x3c000000;     /* Read-Data sampled on falling edge of Clk */
1318                         tmp_sdram_mode = 0x32;  /* CL=3 Burstlength = 4 */
1319                         DP (printf
1320                             ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1321                              tmp_sdram_mode, tmp_dunit_control_low));
1322                         break;
1323
1324                 case DDR_CL_2_5:
1325                         if (tmp == 1) { /* clocks sync */
1326                                 tmp_dunit_control_low = 0x24000000;     /* Read-Data sampled on falling edge of Clk */
1327                                 tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1328                                 DP (printf
1329                                     ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1330                                      tmp_sdram_mode, tmp_dunit_control_low));
1331                         } else {        /* clk sync. bypassed     */
1332
1333                                 tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1334                                 tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1335                                 DP (printf
1336                                     ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1337                                      tmp_sdram_mode, tmp_dunit_control_low));
1338                         }
1339                         break;
1340
1341                 case DDR_CL_2:
1342                         if (tmp == 1) { /* Sync */
1343                                 tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1344                                 tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1345                                 DP (printf
1346                                     ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1347                                      tmp_sdram_mode, tmp_dunit_control_low));
1348                         } else {        /* Not sync.      */
1349
1350                                 tmp_dunit_control_low = 0x3b000000;     /* Read-Data sampled on rising edge of Clk */
1351                                 tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1352                                 DP (printf
1353                                     ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1354                                      tmp_sdram_mode, tmp_dunit_control_low));
1355                         }
1356                         break;
1357
1358                 case DDR_CL_1_5:
1359                         if (tmp == 1) { /* Sync */
1360                                 tmp_dunit_control_low = 0x23000000;     /* Read-Data sampled on falling edge of Clk */
1361                                 tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1362                                 DP (printf
1363                                     ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1364                                      tmp_sdram_mode, tmp_dunit_control_low));
1365                         } else {        /* not sync */
1366
1367                                 tmp_dunit_control_low = 0x1a000000;     /* Read-Data sampled on rising edge of Clk */
1368                                 tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1369                                 DP (printf
1370                                     ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1371                                      tmp_sdram_mode, tmp_dunit_control_low));
1372                         }
1373                         break;
1374
1375                 default:
1376                         printf ("Max. CL is out of range %d\n",
1377                                 info->maxClSupported_DDR);
1378                         hang ();
1379                         break;
1380                 }
1381                 break;
1382         }
1383
1384         /* Write results of CL detection procedure */
1385         GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1386         /* set SDRAM mode SetCommand 0x1418 */
1387         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1388         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1389                 DP (printf
1390                     ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1391         }
1392
1393
1394         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1395         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1396         if (tmp != 1) {         /*clocks are not sync */
1397                 /* asyncmode */
1398                 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1399                               (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1400                               0x18110780 | tmp_dunit_control_low);
1401         } else {
1402                 /* syncmode */
1403                 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1404                               (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1405                               0x00110000 | tmp_dunit_control_low);
1406         }
1407
1408         /* set SDRAM mode SetCommand 0x1418 */
1409         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1410         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1411                 DP (printf
1412                     ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
1413         }
1414
1415 /*------------------------------------------------------------------------------ */
1416
1417
1418         /* bank parameters */
1419         /* SDRAM address decode register */
1420         /* program this with the default value */
1421         tmp = 0x02;
1422
1423
1424         DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
1425         switch (info->drb_size) {
1426         case 1:         /* 64 Mbit */
1427         case 2:         /* 128 Mbit */
1428                 DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
1429                 tmp |= (0x00 << 4);
1430                 break;
1431         case 4:         /* 256 Mbit */
1432         case 8:         /* 512 Mbit */
1433                 DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
1434                 tmp |= (0x01 << 4);
1435                 break;
1436         case 16:                /* 1 Gbit */
1437         case 32:                /* 2 Gbit */
1438                 DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
1439                 tmp |= (0x02 << 4);
1440                 break;
1441         default:
1442                 printf ("Error in dram size calculation\n");
1443                 DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
1444                 tmp |= (0x02 << 4);
1445                 return 1;
1446         }
1447
1448         /* SDRAM bank parameters */
1449         /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1450         DP (printf
1451             ("setting up slot %d config with: %08lx \n", info->slot, tmp));
1452         GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1453
1454 /* ------------------------------------------------------------------------------ */
1455
1456         DP (printf
1457             ("setting up sdram_timing_control_low with: %08x \n",
1458              0x11511220));
1459         GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1460
1461
1462 /* ------------------------------------------------------------------------------ */
1463
1464         /* SDRAM configuration */
1465         tmp = GTREGREAD (SDRAM_CONFIG);
1466
1467         if (info->registeredAddrAndControlInputs
1468             || info->registeredDQMBinputs) {
1469                 tmp |= (1 << 17);
1470                 DP (printf
1471                     ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1472                      info->registeredAddrAndControlInputs,
1473                      info->registeredDQMBinputs));
1474         }
1475
1476         /* Use buffer 1 to return read data to the CPU
1477          * Page 426 MV64360 */
1478         tmp |= (1 << 26);
1479         DP (printf
1480             ("Before Buffer assignment - sdram_conf: %08x\n",
1481              GTREGREAD (SDRAM_CONFIG)));
1482         DP (printf
1483             ("After Buffer assignment - sdram_conf: %08x\n",
1484              GTREGREAD (SDRAM_CONFIG)));
1485
1486         /* SDRAM timing To_do: */
1487
1488
1489         tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1490         DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp));
1491
1492         /* SDRAM address decode register */
1493         /* program this with the default value */
1494         tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1495         DP (printf
1496             ("SDRAM address control (before: decode): %08x  ",
1497              GTREGREAD (SDRAM_ADDR_CONTROL)));
1498         GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1499         DP (printf
1500             ("SDRAM address control (after: decode): %08x\n",
1501              GTREGREAD (SDRAM_ADDR_CONTROL)));
1502
1503         /* set the SDRAM configuration for each bank */
1504
1505 /*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1506         {
1507                 int l, l1;
1508
1509                 i = info->slot;
1510                 DP (printf
1511                     ("\n*** Running a MRS cycle for bank %d ***\n", i));
1512
1513                 /* map the bank */
1514                 memory_map_bank (i, 0, GB / 4);
1515 #if 1                           /* test only */
1516
1517                 tmp = GTREGREAD (SDRAM_MODE);
1518                 GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
1519                 GT_REG_WRITE (SDRAM_OPERATION, 0x4);
1520                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1521                         DP (printf
1522                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1523                 }
1524
1525                 GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
1526                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1527                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1528                         DP (printf
1529                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1530                 }
1531                 l1 = 0;
1532                 for (l=0;l<200;l++)
1533                         l1 += GTREGREAD (SDRAM_OPERATION);
1534
1535                 GT_REG_WRITE (SDRAM_MODE, tmp);
1536                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1537                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1538                         DP (printf
1539                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1540                 }
1541
1542                 /* switch back to normal operation mode */
1543                 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1544                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1545                         DP (printf
1546                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1547                 }
1548
1549 #endif /* test only */
1550                 /* unmap the bank */
1551                 memory_map_bank (i, 0, 0);
1552         }
1553
1554         return 0;
1555 }
1556
1557 /*
1558  * Check memory range for valid RAM. A simple memory test determines
1559  * the actually available RAM size between addresses `base' and
1560  * `base + maxsize'. Some (not all) hardware errors are detected:
1561  * - short between address lines
1562  * - short between data lines
1563  */
1564 long int
1565 dram_size(long int *base, long int maxsize)
1566 {
1567     volatile long int    *addr, *b=base;
1568     long int     cnt, val, save1, save2;
1569
1570 #define STARTVAL (1<<20)        /* start test at 1M */
1571     for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1572             addr = base + cnt;  /* pointer arith! */
1573
1574             save1=*addr;                /* save contents of addr */
1575             save2=*b;           /* save contents of base */
1576
1577             *addr=cnt;          /* write cnt to addr */
1578             *b=0;                       /* put null at base */
1579
1580             /* check at base address */
1581             if ((*b) != 0) {
1582                 *addr=save1;    /* restore *addr */
1583                 *b=save2;       /* restore *b */
1584                 return (0);
1585             }
1586             val = *addr;                /* read *addr */
1587             val = *addr;                /* read *addr */
1588
1589             *addr=save1;
1590             *b=save2;
1591
1592             if (val != cnt) {
1593                     DP(printf("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
1594                     /* fix boundary condition.. STARTVAL means zero */
1595                     if(cnt==STARTVAL/sizeof(long)) cnt=0;
1596                     return (cnt * sizeof(long));
1597             }
1598     }
1599     return maxsize;
1600 }
1601
1602 /* ------------------------------------------------------------------------- */
1603
1604 /* ppcboot interface function to SDRAM init - this is where all the
1605  * controlling logic happens */
1606 long int
1607 initdram(int board_type)
1608 {
1609         int s0 = 0, s1 = 0;
1610         int checkbank[4] = { [0 ... 3] = 0 };
1611                 ulong bank_no, realsize, total, check;
1612         AUX_MEM_DIMM_INFO dimmInfo1;
1613         AUX_MEM_DIMM_INFO dimmInfo2;
1614         int nhr;
1615
1616         /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1617
1618         /* check the NHR bit and skip mem init if it's already done */
1619         nhr = get_hid0() & (1 << 16);
1620
1621         if (nhr) {
1622                 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1623         } else {
1624                 /* DIMM0 */
1625                 s0 = check_dimm(0, &dimmInfo1);
1626
1627                 /* DIMM1 */
1628                 s1 = check_dimm(1, &dimmInfo2);
1629
1630                 memory_map_bank(0, 0, 0);
1631                 memory_map_bank(1, 0, 0);
1632                 memory_map_bank(2, 0, 0);
1633                 memory_map_bank(3, 0, 0);
1634
1635                 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1636                         printf("Setup for DIMM1 failed.\n");
1637                 }
1638
1639                 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1640                         printf("Setup for DIMM2 failed.\n");
1641                 }
1642
1643                 /* set the NHR bit */
1644                 set_hid0(get_hid0() | (1 << 16));
1645         }
1646         /* next, size the SDRAM banks */
1647
1648         realsize = total = 0;
1649         check = GB/4;
1650         if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1651         if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1652         if (dimmInfo1.numOfModuleBanks > 2)
1653                 printf("Error, SPD claims DIMM1 has >2 banks\n");
1654
1655         if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1656         if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1657         if (dimmInfo2.numOfModuleBanks > 2)
1658                 printf("Error, SPD claims DIMM2 has >2 banks\n");
1659
1660         for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
1661                 /* skip over banks that are not populated */
1662                 if (! checkbank[bank_no])
1663                         continue;
1664
1665                 if ((total + check) > CFG_GT_REGS)
1666                         check = CFG_GT_REGS - total;
1667
1668                 memory_map_bank(bank_no, total, check);
1669                 realsize = dram_size((long int *)total, check);
1670                 memory_map_bank(bank_no, total, realsize);
1671
1672                 total += realsize;
1673         }
1674
1675 /*      Setup Ethernet DMA Adress window to DRAM Area */
1676         return(total);
1677 }
1678
1679 /* ***************************************************************************************
1680 ! *                             SDRAM INIT                                              *
1681 ! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb       *
1682 ! *               This procedure fits only the Atlantis                                *
1683 ! *                                                                                     *
1684 ! *************************************************************************************** */
1685
1686
1687 /* ***************************************************************************************
1688 ! *                             DFCDL initialize MV643xx Design Considerations             *
1689 ! *                                                                                     *
1690 ! *************************************************************************************** */
1691 int set_dfcdlInit (void)
1692 {
1693         int i;
1694         unsigned int dfcdl_word = 0x0000014f;
1695
1696         for (i = 0; i < 64; i++) {
1697                 GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1698         }
1699         GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);       /* enable dynamic delay line updating */
1700
1701
1702         return (0);
1703 }