3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /*************************************************************************
25 * adaption for the Marvell DB64360 Board
26 * Ingo Assmus (ingo.assmus@keymile.com)
28 * adaption for the cpci750 Board
29 * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
30 *************************************************************************/
33 /* sdram_init.c - automatic memory sizing */
37 #include "../../Marvell/include/memory.h"
38 #include "../../Marvell/include/pci.h"
39 #include "../../Marvell/include/mv_gen_reg.h"
44 #include "../../Marvell/common/i2c.h"
53 #endif /* of CONFIG_PCI */
61 int set_dfcdlInit(void); /* setup delay line of Mv64360 */
63 /* ------------------------------------------------------------------------- */
66 memory_map_bank(unsigned int bankNo,
67 unsigned int bankBase,
68 unsigned int bankLength)
77 printf("mapping bank %d at %08x - %08x\n",
78 bankNo, bankBase, bankBase + bankLength - 1);
80 printf("unmapping bank %d\n", bankNo);
84 memoryMapBank(bankNo, bankBase, bankLength);
87 for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
92 READ_LINE_AGGRESSIVE_PREFETCH |
93 READ_MULTI_AGGRESSIVE_PREFETCH |
97 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
99 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
102 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
110 /* much of this code is based on (or is) the code in the pip405 port */
111 /* thanks go to the authors of said port - Josh */
113 /* structure to store the relevant information about an sdram bank */
114 typedef struct sdram_info {
116 uchar registered, ecc;
123 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
125 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
127 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
128 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
131 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
132 typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
135 /* SDRAM/DDR information struct */
136 typedef struct _gtMemoryDimmInfo
138 MEMORY_TYPE memoryType;
139 unsigned int numOfRowAddresses;
140 unsigned int numOfColAddresses;
141 unsigned int numOfModuleBanks;
142 unsigned int dataWidth;
143 VOLTAGE_INTERFACE voltageInterface;
144 unsigned int errorCheckType; /* ECC , PARITY..*/
145 unsigned int sdramWidth; /* 4,8,16 or 32 */;
146 unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
147 unsigned int minClkDelay;
148 unsigned int burstLengthSupported;
149 unsigned int numOfBanksOnEachDevice;
150 unsigned int suportedCasLatencies;
151 unsigned int RefreshInterval;
152 unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
153 unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns)*/
154 MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
155 MAX_CL_SUPPORTED_SD maxClSupported_SD;
156 unsigned int moduleBankDensity;
157 /* module attributes (true for yes) */
158 bool bufferedAddrAndControlInputs;
159 bool registeredAddrAndControlInputs;
161 bool bufferedDQMBinputs;
162 bool registeredDQMBinputs;
163 bool differentialClockInput;
164 bool redundantRowAddressing;
166 /* module general attributes */
167 bool suportedAutoPreCharge;
168 bool suportedPreChargeAll;
169 bool suportedEarlyRasPreCharge;
170 bool suportedWrite1ReadBurst;
171 bool suported5PercentLowVCC;
172 bool suported5PercentUpperVCC;
173 /* module timing parameters */
174 unsigned int minRasToCasDelay;
175 unsigned int minRowActiveRowActiveDelay;
176 unsigned int minRasPulseWidth;
177 unsigned int minRowPrechargeTime; /* measured in ns */
179 int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
180 int addrAndCommandSetupTime; /* (measured in ns/100) */
181 int dataInputSetupTime; /* LoP left of point (measured in ns) */
182 int dataInputHoldTime; /* LoP left of point (measured in ns) */
183 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
184 unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
185 unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns)*/
186 unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
187 unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns)*/
188 unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
189 unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns)*/
191 unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
192 unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns)*/
194 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
195 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns)*/
197 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
198 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns)*/
200 /* Parameters calculated from
201 the extracted DIMM information */
203 unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
204 unsigned int numberOfDevices;
205 uchar drb_size; /* DRAM size in n*64Mbit */
206 uchar slot; /* Slot Number this module is inserted in */
207 uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
209 uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
210 uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
211 uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
212 unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
213 unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
214 unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
215 uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
222 * translate ns.ns/10 coding of SPD timing values
223 * into 10 ps unit values
225 static inline unsigned short
226 NS10to10PS(unsigned char spd_byte)
228 unsigned short ns, ns10;
230 /* isolate upper nibble */
231 ns = (spd_byte >> 4) & 0x0F;
232 /* isolate lower nibble */
233 ns10 = (spd_byte & 0x0F);
235 return(ns*100 + ns10*10);
239 * translate ns coding of SPD timing values
240 * into 10 ps unit values
242 static inline unsigned short
243 NSto10PS(unsigned char spd_byte)
245 return(spd_byte*100);
248 /* This code reads the SPD chip on the sdram and populates
249 * the array which is passed in with the relevant information */
250 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
251 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
253 DECLARE_GLOBAL_DATA_PTR;
255 unsigned long spd_checksum;
257 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
259 unsigned int i, j, density = 1, devicesForErrCheck = 0;
264 unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
265 int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
266 uchar supp_cal, cal_val;
267 ulong memclk, tmemclk;
269 uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
272 memclk = gd->bus_clk;
273 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
275 memset (data, 0, sizeof (data));
280 DP (puts ("before i2c read\n"));
282 ret = i2c_read (addr, 0, 2, data, 128);
284 DP (puts ("after i2c read\n"));
286 if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
287 || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
288 || (data[70] != 'b') || (data[71] != 'h')) {
292 if ((ret != 0) && (slot == 0)) {
293 memset (data, 0, sizeof (data));
341 /* zero all the values */
342 memset (dimmInfo, 0, sizeof (*dimmInfo));
344 /* copy the SPD content 1:1 into the dimmInfo structure */
345 for (i = 0; i <= 127; i++) {
346 dimmInfo->spd_raw_data[i] = data[i];
350 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
353 dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
355 #ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
357 for (i = 0; i <= 127; i++) {
358 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
364 /* find Manufacturer of Dimm Module */
365 for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
366 dimmInfo->manufactura[i] = data[64 + i];
368 printf ("\nThis RAM-Module is produced by: %s\n",
369 dimmInfo->manufactura);
371 /* find Manul-ID of Dimm Module */
372 for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
373 dimmInfo->modul_id[i] = data[73 + i];
375 printf ("The Module-ID of this RAM-Module is: %s\n",
378 /* find Vendor-Data of Dimm Module */
379 for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
380 dimmInfo->vendor_data[i] = data[99 + i];
382 printf ("Vendor Data of this RAM-Module is: %s\n",
383 dimmInfo->vendor_data);
385 /* find modul_serial_no of Dimm Module */
386 dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
387 printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
388 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
390 /* find Manufac-Data of Dimm Module */
391 dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
392 printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
394 /* find modul_revision of Dimm Module */
395 dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
396 printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
398 /* find manufac_place of Dimm Module */
399 dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
400 printf ("manufac_place of this RAM-Module is: %d\n",
401 dimmInfo->manufac_place);
404 /*------------------------------------------------------------------------------------------------------------------------------*/
405 /* calculate SPD checksum */
406 /*------------------------------------------------------------------------------------------------------------------------------*/
408 #if 0 /* test-only */
409 for (i = 0; i <= 62; i++) {
410 spd_checksum += data[i];
413 if ((spd_checksum & 0xff) != data[63]) {
414 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
419 printf ("SPD Checksum ok!\n");
420 #endif /* test-only */
422 /*------------------------------------------------------------------------------------------------------------------------------*/
423 for (i = 2; i <= 35; i++) {
425 case 2: /* Memory type (DDR / SDRAM) */
426 dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
428 if (dimmInfo->memoryType == 0)
430 ("Dram_type in slot %d is: SDRAM\n",
432 if (dimmInfo->memoryType == 1)
434 ("Dram_type in slot %d is: DDRAM\n",
438 /*------------------------------------------------------------------------------------------------------------------------------*/
440 case 3: /* Number Of Row Addresses */
441 dimmInfo->numOfRowAddresses = data[i];
443 ("Module Number of row addresses: %d\n",
444 dimmInfo->numOfRowAddresses));
446 /*------------------------------------------------------------------------------------------------------------------------------*/
448 case 4: /* Number Of Column Addresses */
449 dimmInfo->numOfColAddresses = data[i];
451 ("Module Number of col addresses: %d\n",
452 dimmInfo->numOfColAddresses));
454 /*------------------------------------------------------------------------------------------------------------------------------*/
456 case 5: /* Number Of Module Banks */
457 dimmInfo->numOfModuleBanks = data[i];
459 ("Number of Banks on Mod. : %d\n",
460 dimmInfo->numOfModuleBanks));
462 /*------------------------------------------------------------------------------------------------------------------------------*/
464 case 6: /* Data Width */
465 dimmInfo->dataWidth = data[i];
467 ("Module Data Width: %d\n",
468 dimmInfo->dataWidth));
470 /*------------------------------------------------------------------------------------------------------------------------------*/
472 case 8: /* Voltage Interface */
475 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
477 ("Module is TTL_5V_TOLERANT\n"));
480 dimmInfo->voltageInterface = LVTTL;
482 ("Module is LVTTL\n"));
485 dimmInfo->voltageInterface = HSTL_1_5V;
487 ("Module is TTL_5V_TOLERANT\n"));
490 dimmInfo->voltageInterface = SSTL_3_3V;
492 ("Module is HSTL_1_5V\n"));
495 dimmInfo->voltageInterface = SSTL_2_5V;
497 ("Module is SSTL_2_5V\n"));
500 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
502 ("Module is VOLTAGE_UNKNOWN\n"));
506 /*------------------------------------------------------------------------------------------------------------------------------*/
508 case 9: /* Minimum Cycle Time At Max CasLatancy */
509 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
510 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
512 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
514 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
515 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
516 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
517 dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
519 dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
522 ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
523 leftOfPoint, rightOfPoint));
525 /*------------------------------------------------------------------------------------------------------------------------------*/
527 case 10: /* Clock To Data Out */
528 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
530 (((data[i] & 0xf0) >> 4) * 10) +
532 leftOfPoint = time_tmp / div;
533 rightOfPoint = time_tmp % div;
534 dimmInfo->clockToDataOut_LoP = leftOfPoint;
535 dimmInfo->clockToDataOut_RoP = rightOfPoint;
537 ("Clock To Data Out: %d.%2d [ns]\n",
538 leftOfPoint, rightOfPoint));
539 /*dimmInfo->clockToDataOut */
541 /*------------------------------------------------------------------------------------------------------------------------------*/
544 case 11: /* Error Check Type */
545 dimmInfo->errorCheckType = data[i];
547 ("Error Check Type (0=NONE): %d\n",
548 dimmInfo->errorCheckType));
551 /*------------------------------------------------------------------------------------------------------------------------------*/
553 case 12: /* Refresh Interval */
554 dimmInfo->RefreshInterval = data[i];
556 ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
557 dimmInfo->RefreshInterval));
559 /*------------------------------------------------------------------------------------------------------------------------------*/
561 case 13: /* Sdram Width */
562 dimmInfo->sdramWidth = data[i];
564 ("Sdram Width: %d\n",
565 dimmInfo->sdramWidth));
567 /*------------------------------------------------------------------------------------------------------------------------------*/
569 case 14: /* Error Check Data Width */
570 dimmInfo->errorCheckDataWidth = data[i];
572 ("Error Check Data Width: %d\n",
573 dimmInfo->errorCheckDataWidth));
575 /*------------------------------------------------------------------------------------------------------------------------------*/
577 case 15: /* Minimum Clock Delay */
578 dimmInfo->minClkDelay = data[i];
580 ("Minimum Clock Delay: %d\n",
581 dimmInfo->minClkDelay));
583 /*------------------------------------------------------------------------------------------------------------------------------*/
585 case 16: /* Burst Length Supported */
586 /******-******-******-*******
587 * bit3 | bit2 | bit1 | bit0 *
588 *******-******-******-*******
589 burst length = * 8 | 4 | 2 | 1 *
590 *****************************
592 If for example bit0 and bit2 are set, the burst
593 length supported are 1 and 4. */
595 dimmInfo->burstLengthSupported = data[i];
598 ("Burst Length Supported: "));
599 if (dimmInfo->burstLengthSupported & 0x01)
601 if (dimmInfo->burstLengthSupported & 0x02)
603 if (dimmInfo->burstLengthSupported & 0x04)
605 if (dimmInfo->burstLengthSupported & 0x08)
607 DP (printf (" Bit \n"));
610 /*------------------------------------------------------------------------------------------------------------------------------*/
612 case 17: /* Number Of Banks On Each Device */
613 dimmInfo->numOfBanksOnEachDevice = data[i];
615 ("Number Of Banks On Each Chip: %d\n",
616 dimmInfo->numOfBanksOnEachDevice));
618 /*------------------------------------------------------------------------------------------------------------------------------*/
620 case 18: /* Suported Cas Latencies */
623 *******-******-******-******-******-******-******-*******
624 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
625 *******-******-******-******-******-******-******-*******
626 CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
627 *********************************************************
629 *******-******-******-******-******-******-******-*******
630 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
631 *******-******-******-******-******-******-******-*******
632 CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
633 ********************************************************/
634 dimmInfo->suportedCasLatencies = data[i];
637 ("Suported Cas Latencies: (CL) "));
638 if (dimmInfo->memoryType == 0) { /* SDRAM */
639 for (k = 0; k <= 7; k++) {
641 suportedCasLatencies & (1 << k))
647 } else { /* DDR-RAM */
649 if (dimmInfo->suportedCasLatencies & 1)
651 if (dimmInfo->suportedCasLatencies & 2)
652 DP (printf ("1.5, "));
653 if (dimmInfo->suportedCasLatencies & 4)
655 if (dimmInfo->suportedCasLatencies & 8)
656 DP (printf ("2.5, "));
657 if (dimmInfo->suportedCasLatencies & 16)
659 if (dimmInfo->suportedCasLatencies & 32)
660 DP (printf ("3.5, "));
665 /* Calculating MAX CAS latency */
666 for (j = 7; j > 0; j--) {
668 suportedCasLatencies >> j) & 0x1) ==
670 switch (dimmInfo->memoryType) {
672 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
676 ("Max. Cas Latencies (DDR): ERROR !!!\n"));
685 ("Max. Cas Latencies (DDR): ERROR !!!\n"));
694 ("Max. Cas Latencies (DDR): 3.5 clk's\n"));
701 ("Max. Cas Latencies (DDR): 3 clk's \n"));
708 ("Max. Cas Latencies (DDR): 2.5 clk's \n"));
715 ("Max. Cas Latencies (DDR): 2 clk's \n"));
722 ("Max. Cas Latencies (DDR): 1.5 clk's \n"));
729 maxCASlatencySupported_LoP
733 if (((5 * j) % 10) != 0)
735 maxCASlatencySupported_RoP
739 maxCASlatencySupported_RoP
742 ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
744 maxCASlatencySupported_LoP,
746 maxCASlatencySupported_RoP));
749 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
750 dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
752 ("Max. Cas Latencies (SD): %d\n",
756 maxCASlatencySupported_LoP
759 maxCASlatencySupported_RoP
762 ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
764 maxCASlatencySupported_LoP,
766 maxCASlatencySupported_RoP));
773 /*------------------------------------------------------------------------------------------------------------------------------*/
775 case 21: /* Buffered Address And Control Inputs */
776 DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
777 dimmInfo->bufferedAddrAndControlInputs =
779 dimmInfo->registeredAddrAndControlInputs =
780 (data[i] & BIT1) >> 1;
781 dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
782 dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
783 dimmInfo->registeredDQMBinputs =
784 (data[i] & BIT4) >> 4;
785 dimmInfo->differentialClockInput =
786 (data[i] & BIT5) >> 5;
787 dimmInfo->redundantRowAddressing =
788 (data[i] & BIT6) >> 6;
790 if (dimmInfo->bufferedAddrAndControlInputs == 1)
792 (" - Buffered Address/Control Input: Yes \n"));
795 (" - Buffered Address/Control Input: No \n"));
797 if (dimmInfo->registeredAddrAndControlInputs == 1)
799 (" - Registered Address/Control Input: Yes \n"));
802 (" - Registered Address/Control Input: No \n"));
804 if (dimmInfo->onCardPLL == 1)
806 (" - On-Card PLL (clock): Yes \n"));
809 (" - On-Card PLL (clock): No \n"));
811 if (dimmInfo->bufferedDQMBinputs == 1)
813 (" - Bufferd DQMB Inputs: Yes \n"));
816 (" - Bufferd DQMB Inputs: No \n"));
818 if (dimmInfo->registeredDQMBinputs == 1)
820 (" - Registered DQMB Inputs: Yes \n"));
823 (" - Registered DQMB Inputs: No \n"));
825 if (dimmInfo->differentialClockInput == 1)
827 (" - Differential Clock Input: Yes \n"));
830 (" - Differential Clock Input: No \n"));
832 if (dimmInfo->redundantRowAddressing == 1)
834 (" - redundant Row Addressing: Yes \n"));
837 (" - redundant Row Addressing: No \n"));
841 /*------------------------------------------------------------------------------------------------------------------------------*/
843 case 22: /* Suported AutoPreCharge */
844 DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
845 dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
846 dimmInfo->suportedAutoPreCharge =
847 (data[i] & BIT1) >> 1;
848 dimmInfo->suportedPreChargeAll =
849 (data[i] & BIT2) >> 2;
850 dimmInfo->suportedWrite1ReadBurst =
851 (data[i] & BIT3) >> 3;
852 dimmInfo->suported5PercentLowVCC =
853 (data[i] & BIT4) >> 4;
854 dimmInfo->suported5PercentUpperVCC =
855 (data[i] & BIT5) >> 5;
857 if (dimmInfo->suportedEarlyRasPreCharge == 1)
859 (" - Early Ras Precharge: Yes \n"));
862 (" - Early Ras Precharge: No \n"));
864 if (dimmInfo->suportedAutoPreCharge == 1)
866 (" - AutoPreCharge: Yes \n"));
869 (" - AutoPreCharge: No \n"));
871 if (dimmInfo->suportedPreChargeAll == 1)
873 (" - Precharge All: Yes \n"));
876 (" - Precharge All: No \n"));
878 if (dimmInfo->suportedWrite1ReadBurst == 1)
880 (" - Write 1/ReadBurst: Yes \n"));
883 (" - Write 1/ReadBurst: No \n"));
885 if (dimmInfo->suported5PercentLowVCC == 1)
887 (" - lower VCC tolerance: 5 Percent \n"));
890 (" - lower VCC tolerance: 10 Percent \n"));
892 if (dimmInfo->suported5PercentUpperVCC == 1)
894 (" - upper VCC tolerance: 5 Percent \n"));
897 (" - upper VCC tolerance: 10 Percent \n"));
901 /*------------------------------------------------------------------------------------------------------------------------------*/
903 case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
904 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
905 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
907 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
909 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
910 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
911 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
912 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
914 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
917 ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
918 leftOfPoint, rightOfPoint));
919 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
921 /*------------------------------------------------------------------------------------------------------------------------------*/
923 case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
924 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
926 (((data[i] & 0xf0) >> 4) * 10) +
928 leftOfPoint = time_tmp / div;
929 rightOfPoint = time_tmp % div;
930 dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
931 dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
933 ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
934 leftOfPoint, rightOfPoint));
936 /*------------------------------------------------------------------------------------------------------------------------------*/
938 case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
939 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
940 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
942 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
944 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
945 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
946 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
947 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
949 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
952 ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
953 leftOfPoint, rightOfPoint));
954 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
956 /*------------------------------------------------------------------------------------------------------------------------------*/
958 case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
959 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
961 (((data[i] & 0xf0) >> 4) * 10) +
963 leftOfPoint = time_tmp / div;
964 rightOfPoint = time_tmp % div;
965 dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
966 dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
968 ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
969 leftOfPoint, rightOfPoint));
971 /*------------------------------------------------------------------------------------------------------------------------------*/
973 case 27: /* Minimum Row Precharge Time */
974 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
976 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
978 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
979 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
980 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
982 dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
984 (dimmInfo->minRowPrechargeTime +
985 (tmemclk - 1)) / tmemclk;
987 ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
988 tmemclk, tmemclk / 100, tmemclk % 100));
990 ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
991 leftOfPoint, rightOfPoint, trp_clocks));
993 /*------------------------------------------------------------------------------------------------------------------------------*/
995 case 28: /* Minimum Row Active to Row Active Time */
996 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
998 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1000 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1001 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1002 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1004 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
1006 (dimmInfo->minRowActiveRowActiveDelay +
1007 (tmemclk - 1)) / tmemclk;
1009 ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
1010 leftOfPoint, rightOfPoint, trp_clocks));
1012 /*------------------------------------------------------------------------------------------------------------------------------*/
1014 case 29: /* Minimum Ras-To-Cas Delay */
1015 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
1017 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1019 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1020 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1021 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1023 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
1025 (dimmInfo->minRowActiveRowActiveDelay +
1026 (tmemclk - 1)) / tmemclk;
1028 ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
1029 leftOfPoint, rightOfPoint, trp_clocks));
1031 /*------------------------------------------------------------------------------------------------------------------------------*/
1033 case 30: /* Minimum Ras Pulse Width */
1034 dimmInfo->minRasPulseWidth = data[i];
1036 (NSto10PS (data[i]) +
1037 (tmemclk - 1)) / tmemclk;
1039 ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
1040 dimmInfo->minRasPulseWidth, tras_clocks));
1043 /*------------------------------------------------------------------------------------------------------------------------------*/
1045 case 31: /* Module Bank Density */
1046 dimmInfo->moduleBankDensity = data[i];
1048 ("Module Bank Density: %d\n",
1049 dimmInfo->moduleBankDensity));
1052 ("*** Offered Densities (more than 1 = Multisize-Module): "));
1054 if (dimmInfo->moduleBankDensity & 1)
1055 DP (printf ("4MB, "));
1056 if (dimmInfo->moduleBankDensity & 2)
1057 DP (printf ("8MB, "));
1058 if (dimmInfo->moduleBankDensity & 4)
1059 DP (printf ("16MB, "));
1060 if (dimmInfo->moduleBankDensity & 8)
1061 DP (printf ("32MB, "));
1062 if (dimmInfo->moduleBankDensity & 16)
1063 DP (printf ("64MB, "));
1064 if (dimmInfo->moduleBankDensity & 32)
1065 DP (printf ("128MB, "));
1066 if ((dimmInfo->moduleBankDensity & 64)
1067 || (dimmInfo->moduleBankDensity & 128)) {
1068 DP (printf ("ERROR, "));
1075 /*------------------------------------------------------------------------------------------------------------------------------*/
1077 case 32: /* Address And Command Setup Time (measured in ns/1000) */
1079 switch (dimmInfo->memoryType) {
1082 (((data[i] & 0xf0) >> 4) * 10) +
1084 leftOfPoint = time_tmp / 100;
1085 rightOfPoint = time_tmp % 100;
1088 leftOfPoint = (data[i] & 0xf0) >> 4;
1089 if (leftOfPoint > 7) {
1090 leftOfPoint = data[i] & 0x70 >> 4;
1093 rightOfPoint = (data[i] & 0x0f);
1096 dimmInfo->addrAndCommandSetupTime =
1097 (leftOfPoint * 100 + rightOfPoint) * sign;
1099 ("Address And Command Setup Time [ns]: %d.%d\n",
1100 sign * leftOfPoint, rightOfPoint));
1102 /*------------------------------------------------------------------------------------------------------------------------------*/
1104 case 33: /* Address And Command Hold Time */
1106 switch (dimmInfo->memoryType) {
1109 (((data[i] & 0xf0) >> 4) * 10) +
1111 leftOfPoint = time_tmp / 100;
1112 rightOfPoint = time_tmp % 100;
1115 leftOfPoint = (data[i] & 0xf0) >> 4;
1116 if (leftOfPoint > 7) {
1117 leftOfPoint = data[i] & 0x70 >> 4;
1120 rightOfPoint = (data[i] & 0x0f);
1123 dimmInfo->addrAndCommandHoldTime =
1124 (leftOfPoint * 100 + rightOfPoint) * sign;
1126 ("Address And Command Hold Time [ns]: %d.%d\n",
1127 sign * leftOfPoint, rightOfPoint));
1129 /*------------------------------------------------------------------------------------------------------------------------------*/
1131 case 34: /* Data Input Setup Time */
1133 switch (dimmInfo->memoryType) {
1136 (((data[i] & 0xf0) >> 4) * 10) +
1138 leftOfPoint = time_tmp / 100;
1139 rightOfPoint = time_tmp % 100;
1142 leftOfPoint = (data[i] & 0xf0) >> 4;
1143 if (leftOfPoint > 7) {
1144 leftOfPoint = data[i] & 0x70 >> 4;
1147 rightOfPoint = (data[i] & 0x0f);
1150 dimmInfo->dataInputSetupTime =
1151 (leftOfPoint * 100 + rightOfPoint) * sign;
1153 ("Data Input Setup Time [ns]: %d.%d\n",
1154 sign * leftOfPoint, rightOfPoint));
1156 /*------------------------------------------------------------------------------------------------------------------------------*/
1158 case 35: /* Data Input Hold Time */
1160 switch (dimmInfo->memoryType) {
1163 (((data[i] & 0xf0) >> 4) * 10) +
1165 leftOfPoint = time_tmp / 100;
1166 rightOfPoint = time_tmp % 100;
1169 leftOfPoint = (data[i] & 0xf0) >> 4;
1170 if (leftOfPoint > 7) {
1171 leftOfPoint = data[i] & 0x70 >> 4;
1174 rightOfPoint = (data[i] & 0x0f);
1177 dimmInfo->dataInputHoldTime =
1178 (leftOfPoint * 100 + rightOfPoint) * sign;
1180 ("Data Input Hold Time [ns]: %d.%d\n\n",
1181 sign * leftOfPoint, rightOfPoint));
1183 /*------------------------------------------------------------------------------------------------------------------------------*/
1186 /* calculating the sdram density */
1188 i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1190 density = density * 2;
1192 dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1193 dimmInfo->sdramWidth;
1194 dimmInfo->numberOfDevices =
1195 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1196 dimmInfo->numOfModuleBanks;
1197 devicesForErrCheck =
1198 (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1199 if ((dimmInfo->errorCheckType == 0x1)
1200 || (dimmInfo->errorCheckType == 0x2)
1201 || (dimmInfo->errorCheckType == 0x3)) {
1203 (dimmInfo->deviceDensity / 8) *
1204 (dimmInfo->numberOfDevices - devicesForErrCheck);
1207 (dimmInfo->deviceDensity / 8) *
1208 dimmInfo->numberOfDevices;
1211 /* compute the module DRB size */
1213 (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1214 tmp *= dimmInfo->numOfModuleBanks;
1215 tmp *= dimmInfo->sdramWidth;
1216 tmp = tmp >> 24; /* div by 0x4000000 (64M) */
1217 dimmInfo->drb_size = (uchar) tmp;
1218 DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
1220 /* try a CAS latency of 3 first... */
1222 /* bit 1 is CL2, bit 2 is CL3 */
1223 supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1227 if (NS10to10PS (data[9]) <= tmemclk)
1231 if (NS10to10PS (data[9]) <= tmemclk)
1237 if (NS10to10PS (data[23]) <= tmemclk)
1241 DP (printf ("cal_val = %d\n", cal_val * 5));
1243 /* bummer, did't work... */
1245 DP (printf ("Couldn't find a good CAS latency\n"));
1253 /* sets up the GT properly with information passed in */
1254 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1257 ulong tmp_sdram_mode = 0; /* 0x141c */
1258 ulong tmp_dunit_control_low = 0; /* 0x1404 */
1261 /* sanity checking */
1262 if (!info->numOfModuleBanks) {
1263 printf ("setup_sdram called with 0 banks\n");
1269 /* Program the GT with the discovered data */
1270 if (info->registeredAddrAndControlInputs == true)
1272 ("Module is registered, but we do not support registered Modules !!!\n"));
1276 set_dfcdlInit (); /* may be its not needed */
1277 DP (printf ("Delay line set done\n"));
1279 /* set SDRAM mode NOP */ /* To_do check it */
1280 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1281 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1283 ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
1286 /* SDRAM configuration */
1287 GT_REG_WRITE (SDRAM_CONFIG, 0x58200400);
1288 DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
1290 /* SDRAM open pages controll keep open as much as I can */
1291 GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1293 ("sdram_open_pages_controll 0x1414: %08x\n",
1294 GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
1297 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1298 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1300 DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
1303 ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
1305 /* SDRAM set CAS Lentency according to SPD information */
1306 switch (info->memoryType) {
1308 DP (printf ("### SD-RAM not supported yet !!!\n"));
1310 /* ToDo fill SD-RAM if needed !!!!! */
1314 DP (printf ("### SET-CL for DDR-RAM\n"));
1316 switch (info->maxClSupported_DDR) {
1318 tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */
1319 tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
1321 ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1322 tmp_sdram_mode, tmp_dunit_control_low));
1326 if (tmp == 1) { /* clocks sync */
1327 tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */
1328 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1330 ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1331 tmp_sdram_mode, tmp_dunit_control_low));
1332 } else { /* clk sync. bypassed */
1334 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1335 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
1337 ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1338 tmp_sdram_mode, tmp_dunit_control_low));
1343 if (tmp == 1) { /* Sync */
1344 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
1345 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1347 ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1348 tmp_sdram_mode, tmp_dunit_control_low));
1349 } else { /* Not sync. */
1351 tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */
1352 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1354 ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1355 tmp_sdram_mode, tmp_dunit_control_low));
1360 if (tmp == 1) { /* Sync */
1361 tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */
1362 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1364 ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1365 tmp_sdram_mode, tmp_dunit_control_low));
1366 } else { /* not sync */
1368 tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */
1369 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
1371 ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1372 tmp_sdram_mode, tmp_dunit_control_low));
1377 printf ("Max. CL is out of range %d\n",
1378 info->maxClSupported_DDR);
1385 /* Write results of CL detection procedure */
1386 GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1387 /* set SDRAM mode SetCommand 0x1418 */
1388 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1389 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1391 ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1395 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1396 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1397 if (tmp != 1) { /*clocks are not sync */
1399 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1400 (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1401 0x18110780 | tmp_dunit_control_low);
1404 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1405 (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1406 0x00110000 | tmp_dunit_control_low);
1409 /* set SDRAM mode SetCommand 0x1418 */
1410 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1411 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1413 ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
1416 /*------------------------------------------------------------------------------ */
1419 /* bank parameters */
1420 /* SDRAM address decode register */
1421 /* program this with the default value */
1425 DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
1426 switch (info->drb_size) {
1427 case 1: /* 64 Mbit */
1428 case 2: /* 128 Mbit */
1429 DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
1432 case 4: /* 256 Mbit */
1433 case 8: /* 512 Mbit */
1434 DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
1437 case 16: /* 1 Gbit */
1438 case 32: /* 2 Gbit */
1439 DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
1443 printf ("Error in dram size calculation\n");
1444 DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
1449 /* SDRAM bank parameters */
1450 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1452 ("setting up slot %d config with: %08lx \n", info->slot, tmp));
1453 GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1455 /* ------------------------------------------------------------------------------ */
1458 ("setting up sdram_timing_control_low with: %08x \n",
1460 GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1463 /* ------------------------------------------------------------------------------ */
1465 /* SDRAM configuration */
1466 tmp = GTREGREAD (SDRAM_CONFIG);
1468 if (info->registeredAddrAndControlInputs
1469 || info->registeredDQMBinputs) {
1472 ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1473 info->registeredAddrAndControlInputs,
1474 info->registeredDQMBinputs));
1477 /* Use buffer 1 to return read data to the CPU
1478 * Page 426 MV64360 */
1481 ("Before Buffer assignment - sdram_conf: %08x\n",
1482 GTREGREAD (SDRAM_CONFIG)));
1484 ("After Buffer assignment - sdram_conf: %08x\n",
1485 GTREGREAD (SDRAM_CONFIG)));
1487 /* SDRAM timing To_do: */
1490 tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1491 DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp));
1493 /* SDRAM address decode register */
1494 /* program this with the default value */
1495 tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1497 ("SDRAM address control (before: decode): %08x ",
1498 GTREGREAD (SDRAM_ADDR_CONTROL)));
1499 GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1501 ("SDRAM address control (after: decode): %08x\n",
1502 GTREGREAD (SDRAM_ADDR_CONTROL)));
1504 /* set the SDRAM configuration for each bank */
1506 /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1510 ("\n*** Running a MRS cycle for bank %d ***\n", i));
1513 memory_map_bank (i, 0, GB / 4);
1514 #if 1 /* test only */
1515 /* set SDRAM mode */ /* To_do check it */
1516 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1517 check = GTREGREAD (SDRAM_OPERATION);
1519 ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1523 /* switch back to normal operation mode */
1524 GT_REG_WRITE (SDRAM_OPERATION, 0);
1525 check = GTREGREAD (SDRAM_OPERATION);
1527 ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1529 #endif /* test only */
1530 /* unmap the bank */
1531 memory_map_bank (i, 0, 0);
1538 * Check memory range for valid RAM. A simple memory test determines
1539 * the actually available RAM size between addresses `base' and
1540 * `base + maxsize'. Some (not all) hardware errors are detected:
1541 * - short between address lines
1542 * - short between data lines
1545 dram_size(long int *base, long int maxsize)
1547 volatile long int *addr, *b=base;
1548 long int cnt, val, save1, save2;
1550 #define STARTVAL (1<<20) /* start test at 1M */
1551 for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1552 addr = base + cnt; /* pointer arith! */
1554 save1=*addr; /* save contents of addr */
1555 save2=*b; /* save contents of base */
1557 *addr=cnt; /* write cnt to addr */
1558 *b=0; /* put null at base */
1560 /* check at base address */
1562 *addr=save1; /* restore *addr */
1563 *b=save2; /* restore *b */
1566 val = *addr; /* read *addr */
1567 val = *addr; /* read *addr */
1573 DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
1574 /* fix boundary condition.. STARTVAL means zero */
1575 if(cnt==STARTVAL/sizeof(long)) cnt=0;
1576 return (cnt * sizeof(long));
1582 /* ------------------------------------------------------------------------- */
1584 /* ppcboot interface function to SDRAM init - this is where all the
1585 * controlling logic happens */
1587 initdram(int board_type)
1590 int checkbank[4] = { [0 ... 3] = 0 };
1591 ulong bank_no, realsize, total, check;
1592 AUX_MEM_DIMM_INFO dimmInfo1;
1593 AUX_MEM_DIMM_INFO dimmInfo2;
1596 /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1598 /* check the NHR bit and skip mem init if it's already done */
1599 nhr = get_hid0() & (1 << 16);
1602 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1605 s0 = check_dimm(0, &dimmInfo1);
1608 s1 = check_dimm(1, &dimmInfo2);
1610 memory_map_bank(0, 0, 0);
1611 memory_map_bank(1, 0, 0);
1612 memory_map_bank(2, 0, 0);
1613 memory_map_bank(3, 0, 0);
1615 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1616 printf("Setup for DIMM1 failed.\n");
1619 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1620 printf("Setup for DIMM2 failed.\n");
1623 /* set the NHR bit */
1624 set_hid0(get_hid0() | (1 << 16));
1626 /* next, size the SDRAM banks */
1628 realsize = total = 0;
1630 if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1631 if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1632 if (dimmInfo1.numOfModuleBanks > 2)
1633 printf("Error, SPD claims DIMM1 has >2 banks\n");
1635 if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1636 if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1637 if (dimmInfo2.numOfModuleBanks > 2)
1638 printf("Error, SPD claims DIMM2 has >2 banks\n");
1640 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
1641 /* skip over banks that are not populated */
1642 if (! checkbank[bank_no])
1645 if ((total + check) > CFG_GT_REGS)
1646 check = CFG_GT_REGS - total;
1648 memory_map_bank(bank_no, total, check);
1649 realsize = dram_size((long int *)total, check);
1650 memory_map_bank(bank_no, total, realsize);
1655 /* Setup Ethernet DMA Adress window to DRAM Area */
1659 /* ***************************************************************************************
1661 ! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
1662 ! * This procedure fits only the Atlantis *
1664 ! *************************************************************************************** */
1667 /* ***************************************************************************************
1668 ! * DFCDL initialize MV643xx Design Considerations *
1670 ! *************************************************************************************** */
1671 int set_dfcdlInit (void)
1674 unsigned int dfcdl_word = 0x0000014f;
1676 for (i = 0; i < 64; i++) {
1677 GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1679 GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */