git.sur5r.net Git - u-boot/blob - board/esd/cpci750/sdram_init.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * adaption for the Marvell DB64360 Board
  26  * Ingo Assmus (ingo.assmus@keymile.com)
  27  *
  28  * adaption for the cpci750 Board
  29  * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
  30  *************************************************************************/
  31
  32
  33 /* sdram_init.c - automatic memory sizing */
  34
  35 #include <common.h>
  36 #include <74xx_7xx.h>
  37 #include "../../Marvell/include/memory.h"
  38 #include "../../Marvell/include/pci.h"
  39 #include "../../Marvell/include/mv_gen_reg.h"
  40 #include <net.h>
  41
  42 #include "eth.h"
  43 #include "mpsc.h"
  44 #include "../../Marvell/common/i2c.h"
  45 #include "64360.h"
  46 #include "mv_regs.h"
  47
  48
  49 #undef  DEBUG
  50 /* #define DEBUG */
  51 #ifdef CONFIG_PCI
  52 #define MAP_PCI
  53 #endif /* of CONFIG_PCI */
  54
  55 #ifdef DEBUG
  56 #define DP(x) x
  57 #else
  58 #define DP(x)
  59 #endif
  60
  61 int set_dfcdlInit(void);        /* setup delay line of Mv64360 */
  62
  63 /* ------------------------------------------------------------------------- */
  64
  65 int
  66 memory_map_bank(unsigned int bankNo,
  67                 unsigned int bankBase,
  68                 unsigned int bankLength)
  69 {
  70 #ifdef MAP_PCI
  71         PCI_HOST host;
  72 #endif
  73
  74
  75 #ifdef DEBUG
  76         if (bankLength > 0) {
  77                 printf("mapping bank %d at %08x - %08x\n",
  78                        bankNo, bankBase, bankBase + bankLength - 1);
  79         } else {
  80                 printf("unmapping bank %d\n", bankNo);
  81         }
  82 #endif
  83
  84         memoryMapBank(bankNo, bankBase, bankLength);
  85
  86 #ifdef MAP_PCI
  87         for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
  88                 const int features=
  89                         PREFETCH_ENABLE |
  90                         DELAYED_READ_ENABLE |
  91                         AGGRESSIVE_PREFETCH |
  92                         READ_LINE_AGGRESSIVE_PREFETCH |
  93                         READ_MULTI_AGGRESSIVE_PREFETCH |
  94                         MAX_BURST_4 |
  95                         PCI_NO_SWAP;
  96
  97                 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
  98
  99                 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
 100                                 bankLength);
 101
 102                 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
 103         }
 104 #endif
 105         return 0;
 106 }
 107
 108 #define GB         (1 << 30)
 109
 110 /* much of this code is based on (or is) the code in the pip405 port */
 111 /* thanks go to the authors of said port - Josh */
 112
 113 /* structure to store the relevant information about an sdram bank */
 114 typedef struct sdram_info {
 115         uchar drb_size;
 116         uchar registered, ecc;
 117         uchar tpar;
 118         uchar tras_clocks;
 119         uchar burst_len;
 120         uchar banks, slot;
 121 } sdram_info_t;
 122
 123 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
 124
 125 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
 126
 127 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
 128                                 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
 129                                } VOLTAGE_INTERFACE;
 130
 131 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
 132 typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
 133
 134
 135 /* SDRAM/DDR information struct */
 136 typedef struct _gtMemoryDimmInfo
 137 {
 138     MEMORY_TYPE          memoryType;
 139     unsigned int         numOfRowAddresses;
 140     unsigned int         numOfColAddresses;
 141     unsigned int         numOfModuleBanks;
 142     unsigned int         dataWidth;
 143     VOLTAGE_INTERFACE    voltageInterface;
 144     unsigned int         errorCheckType;                                /* ECC , PARITY..*/
 145     unsigned int         sdramWidth;                                    /* 4,8,16 or 32 */;
 146     unsigned int         errorCheckDataWidth;                           /* 0 - no, 1 - Yes */
 147     unsigned int         minClkDelay;
 148     unsigned int         burstLengthSupported;
 149     unsigned int         numOfBanksOnEachDevice;
 150     unsigned int         suportedCasLatencies;
 151     unsigned int         RefreshInterval;
 152     unsigned int         maxCASlatencySupported_LoP;                    /* LoP left of point (measured in ns) */
 153     unsigned int         maxCASlatencySupported_RoP;                    /* RoP right of point (measured in ns)*/
 154     MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
 155     MAX_CL_SUPPORTED_SD  maxClSupported_SD;
 156     unsigned int         moduleBankDensity;
 157     /* module attributes (true for yes) */
 158     bool                 bufferedAddrAndControlInputs;
 159     bool                 registeredAddrAndControlInputs;
 160     bool                 onCardPLL;
 161     bool                 bufferedDQMBinputs;
 162     bool                 registeredDQMBinputs;
 163     bool                 differentialClockInput;
 164     bool                 redundantRowAddressing;
 165
 166     /* module general attributes */
 167     bool                 suportedAutoPreCharge;
 168     bool                 suportedPreChargeAll;
 169     bool                 suportedEarlyRasPreCharge;
 170     bool                 suportedWrite1ReadBurst;
 171     bool                 suported5PercentLowVCC;
 172     bool                 suported5PercentUpperVCC;
 173     /* module timing parameters */
 174     unsigned int         minRasToCasDelay;
 175     unsigned int         minRowActiveRowActiveDelay;
 176     unsigned int         minRasPulseWidth;
 177     unsigned int         minRowPrechargeTime;                           /* measured in ns */
 178
 179     int                  addrAndCommandHoldTime;                        /* LoP left of point (measured in ns) */
 180     int                  addrAndCommandSetupTime;                               /* (measured in ns/100) */
 181     int                  dataInputSetupTime;                            /* LoP left of point (measured in ns) */
 182     int                  dataInputHoldTime;                             /* LoP left of point (measured in ns) */
 183 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
 184     unsigned int         clockToDataOut_LoP;                            /* LoP left of point (measured in ns) */
 185     unsigned int         clockToDataOut_RoP;                            /* RoP right of point (measured in ns)*/
 186     unsigned int         clockToDataOutMinus1_LoP;                              /* LoP left of point (measured in ns) */
 187     unsigned int         clockToDataOutMinus1_RoP;                      /* RoP right of point (measured in ns)*/
 188     unsigned int         clockToDataOutMinus2_LoP;                              /* LoP left of point (measured in ns) */
 189     unsigned int         clockToDataOutMinus2_RoP;                      /* RoP right of point (measured in ns)*/
 190
 191     unsigned int         minimumCycleTimeAtMaxCasLatancy_LoP;           /* LoP left of point (measured in ns) */
 192     unsigned int         minimumCycleTimeAtMaxCasLatancy_RoP;           /* RoP right of point (measured in ns)*/
 193
 194     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus1_LoP;     /* LoP left of point (measured in ns) */
 195     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus1_RoP;     /* RoP right of point (measured in ns)*/
 196
 197     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus2_LoP;     /* LoP left of point (measured in ns) */
 198     unsigned int         minimumCycleTimeAtMaxCasLatancyMinus2_RoP;     /* RoP right of point (measured in ns)*/
 199
 200     /* Parameters calculated from
 201        the extracted DIMM information */
 202     unsigned int         size;
 203     unsigned int         deviceDensity;                                 /* 16,64,128,256 or 512 Mbit */
 204     unsigned int         numberOfDevices;
 205     uchar                drb_size;                                      /* DRAM size in n*64Mbit */
 206     uchar                slot;                                          /* Slot Number this module is inserted in */
 207     uchar                spd_raw_data[128];                             /* Content of SPD-EEPROM copied 1:1 */
 208 #ifdef DEBUG
 209     uchar                manufactura[8];                                /* Content of SPD-EEPROM Byte 64-71 */
 210     uchar                modul_id[18];                                  /* Content of SPD-EEPROM Byte 73-90 */
 211     uchar                vendor_data[27];                               /* Content of SPD-EEPROM Byte 99-125 */
 212     unsigned long        modul_serial_no;                               /* Content of SPD-EEPROM Byte 95-98 */
 213     unsigned int         manufac_date;                                  /* Content of SPD-EEPROM Byte 93-94 */
 214     unsigned int         modul_revision;                                /* Content of SPD-EEPROM Byte 91-92 */
 215     uchar                manufac_place;                                 /* Content of SPD-EEPROM Byte 72 */
 216
 217 #endif
 218 } AUX_MEM_DIMM_INFO;
 219
 220
 221 /*
 222  * translate ns.ns/10 coding of SPD timing values
 223  * into 10 ps unit values
 224  */
 225 static inline unsigned short
 226 NS10to10PS(unsigned char spd_byte)
 227 {
 228         unsigned short ns, ns10;
 229
 230         /* isolate upper nibble */
 231         ns = (spd_byte >> 4) & 0x0F;
 232         /* isolate lower nibble */
 233         ns10 = (spd_byte & 0x0F);
 234
 235         return(ns*100 + ns10*10);
 236 }
 237
 238 /*
 239  * translate ns coding of SPD timing values
 240  * into 10 ps unit values
 241  */
 242 static inline unsigned short
 243 NSto10PS(unsigned char spd_byte)
 244 {
 245         return(spd_byte*100);
 246 }
 247
 248 /* This code reads the SPD chip on the sdram and populates
 249  * the array which is passed in with the relevant information */
 250 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 251 static int
 252 check_dimm(uchar slot, AUX_MEM_DIMM_INFO *dimmInfo)
 253
 254 {
 255  DECLARE_GLOBAL_DATA_PTR;
 256
 257      unsigned long spd_checksum;
 258
 259         uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 260         int ret;
 261         unsigned int        i,j,density = 1,devicesForErrCheck = 0;
 262 #ifdef DEBUG
 263         unsigned int        k;
 264 #endif
 265         unsigned int    rightOfPoint = 0,leftOfPoint = 0, mult, div, time_tmp;
 266         int                 sign = 1,shift,maskLeftOfPoint,maskRightOfPoint;
 267         uchar supp_cal, cal_val;
 268         ulong memclk, tmemclk;
 269         ulong tmp;
 270         uchar trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks;
 271         uchar data[128];
 272
 273         memclk = gd->bus_clk;
 274         tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
 275
 276         memset(data, 0, sizeof(data));
 277
 278
 279         ret = 0;
 280
 281         DP(puts("before i2c read\n"));
 282
 283         ret = i2c_read(addr, 0, 2, data, 128);
 284
 285         DP(puts("after i2c read\n"));
 286
 287         if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') || (data[67] != '-') ||
 288             (data[68] != 'g') || (data[69] != 'm') || (data[70] != 'b') || (data[71] != 'h'))
 289             {
 290             ret = -1;
 291             }
 292
 293         if ((ret != 0) && (slot == 0))
 294             {
 295             memset(data, 0, sizeof(data));
 296             data[ 0] = 0x80; data[ 1] = 0x08; data[ 2] = 0x07; data[ 3] = 0x0c;
 297             data[ 4] = 0x09; data[ 5] = 0x01; data[ 6] = 0x48; data[ 7] = 0x00;
 298             data[ 8] = 0x04; data[ 9] = 0x75; data[10] = 0x80; data[11] = 0x02;
 299             data[12] = 0x80; data[13] = 0x10; data[14] = 0x08; data[15] = 0x01;
 300             data[16] = 0x0e; data[17] = 0x04; data[18] = 0x0c; data[19] = 0x01;
 301             data[20] = 0x02; data[21] = 0x20; data[22] = 0x00; data[23] = 0xa0;
 302             data[24] = 0x80; data[25] = 0x00; data[26] = 0x00; data[27] = 0x50;
 303             data[28] = 0x3c; data[29] = 0x50; data[30] = 0x32; data[31] = 0x10;
 304             data[32] = 0xb0; data[33] = 0xb0; data[34] = 0x60; data[35] = 0x60;
 305             data[64] = 'e' ; data[65] = 's' ; data[66] = 'd' ; data[67] = '-' ;
 306             data[68] = 'g' ; data[69] = 'm' ; data[70] = 'b' ; data[71] = 'h' ;
 307             ret = 0;
 308             }
 309
 310         /* zero all the values */
 311         memset(dimmInfo, 0, sizeof(*dimmInfo));
 312
 313         /* copy the SPD content 1:1 into the dimmInfo structure*/
 314         for(i = 0 ; i <= 127 ; i++)
 315         {
 316           dimmInfo->spd_raw_data[i] = data[i];
 317         }
 318
 319         if (ret) {
 320                 DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
 321                 return 0;
 322         }
 323         else
 324         dimmInfo->slot = slot;          /* start to fill up dimminfo for this "slot" */
 325
 326 #ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
 327
 328     for(i = 0 ; i <= 127 ; i++)
 329     {
 330         printf("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], data[i]);
 331     }
 332
 333 #endif
 334 #ifdef DEBUG
 335 /* find Manufactura of Dimm Module */
 336     for(i = 0 ; i < sizeof(dimmInfo->manufactura) ; i++)
 337     {
 338         dimmInfo->manufactura[i] = data[64+i];
 339     }
 340     printf("\nThis RAM-Module is produced by:           %s\n", dimmInfo->manufactura);
 341
 342 /* find Manul-ID of Dimm Module */
 343     for(i = 0 ; i < sizeof(dimmInfo->modul_id) ; i++)
 344     {
 345         dimmInfo->modul_id[i] = data[73+i];
 346     }
 347     printf("The Module-ID of this RAM-Module is:                %s\n", dimmInfo->modul_id);
 348
 349 /* find Vendor-Data of Dimm Module */
 350     for(i = 0 ; i < sizeof(dimmInfo->vendor_data) ; i++)
 351     {
 352         dimmInfo->vendor_data[i] = data[99+i];
 353     }
 354     printf("Vendor Data of this RAM-Module is:          %s\n", dimmInfo->vendor_data);
 355
 356 /* find modul_serial_no of Dimm Module */
 357     dimmInfo->modul_serial_no = (*((unsigned long *)(&data[95])));
 358     printf("Serial No. of this RAM-Module is:           %ld (%lx)\n", dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 359
 360 /* find Manufac-Data of Dimm Module */
 361     dimmInfo->manufac_date = (*((unsigned int *)(&data[93])));
 362     printf("Manufactoring Date of this RAM-Module is:   %d.%d\n", data[93], data [94]); /*dimmInfo->manufac_date*/
 363
 364 /* find modul_revision of Dimm Module */
 365     dimmInfo->modul_revision = (*((unsigned int *)(&data[91])));
 366     printf("Module Revision of this RAM-Module is:              %d.%d\n", data[91], data [92]); /* dimmInfo->modul_revision*/
 367
 368 /* find manufac_place of Dimm Module */
 369     dimmInfo->manufac_place = (*((unsigned char *)(&data[72])));
 370     printf("manufac_place of this RAM-Module is:                %d\n", dimmInfo->manufac_place);
 371
 372 #endif
 373 /*------------------------------------------------------------------------------------------------------------------------------*/
 374 /* calculate SPD checksum */
 375 /*------------------------------------------------------------------------------------------------------------------------------*/
 376     spd_checksum = 0;
 377 #if 0 /* test-only */
 378     for(i = 0 ; i <= 62 ; i++)
 379     {
 380      spd_checksum += data[i];
 381     }
 382
 383     if ((spd_checksum & 0xff) != data[63])
 384     {
 385         printf("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int)(spd_checksum & 0xff), data[63]);
 386                 hang();
 387     }
 388
 389     else
 390         printf("SPD Checksum ok!\n");
 391 #endif /* test-only */
 392
 393 /*------------------------------------------------------------------------------------------------------------------------------*/
 394     for(i = 2 ; i <= 35 ; i++)
 395     {
 396         switch(i)
 397         {
 398         case 2:  /* Memory type (DDR / SDRAM) */
 399             dimmInfo->memoryType = (data[i] == 0x7)? DDR:SDRAM;
 400         #ifdef DEBUG
 401         if (dimmInfo->memoryType == 0)
 402                 DP(printf("Dram_type in slot %d is:                     SDRAM\n", dimmInfo->slot));
 403         if (dimmInfo->memoryType == 1)
 404                 DP(printf("Dram_type in slot %d is:                     DDRAM\n", dimmInfo->slot));
 405         #endif
 406             break;
 407 /*------------------------------------------------------------------------------------------------------------------------------*/
 408
 409         case 3:  /* Number Of Row Addresses */
 410             dimmInfo->numOfRowAddresses = data[i];
 411             DP(printf("Module Number of row addresses:          %d\n", dimmInfo->numOfRowAddresses));
 412             break;
 413 /*------------------------------------------------------------------------------------------------------------------------------*/
 414
 415         case 4:  /* Number Of Column Addresses */
 416             dimmInfo->numOfColAddresses = data[i];
 417             DP(printf("Module Number of col addresses:          %d\n", dimmInfo->numOfColAddresses));
 418             break;
 419 /*------------------------------------------------------------------------------------------------------------------------------*/
 420
 421         case 5:  /* Number Of Module Banks */
 422             dimmInfo->numOfModuleBanks = data[i];
 423             DP(printf("Number of Banks on Mod. :                                %d\n", dimmInfo->numOfModuleBanks));
 424             break;
 425 /*------------------------------------------------------------------------------------------------------------------------------*/
 426
 427         case 6:  /* Data Width */
 428             dimmInfo->dataWidth = data[i];
 429             DP(printf("Module Data Width:                               %d\n", dimmInfo->dataWidth));
 430             break;
 431 /*------------------------------------------------------------------------------------------------------------------------------*/
 432
 433         case 8:  /* Voltage Interface */
 434             switch(data[i])
 435             {
 436             case 0x0:
 437                 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
 438                 DP(printf("Module is                                    TTL_5V_TOLERANT\n"));
 439                 break;
 440             case 0x1:
 441                 dimmInfo->voltageInterface = LVTTL;
 442                 DP(printf("Module is                                    LVTTL\n"));
 443                 break;
 444             case 0x2:
 445                 dimmInfo->voltageInterface = HSTL_1_5V;
 446             DP(printf("Module is                                        TTL_5V_TOLERANT\n"));
 447                 break;
 448             case 0x3:
 449                 dimmInfo->voltageInterface = SSTL_3_3V;
 450                 DP(printf("Module is                                    HSTL_1_5V\n"));
 451                 break;
 452             case 0x4:
 453                 dimmInfo->voltageInterface = SSTL_2_5V;
 454                 DP(printf("Module is                                    SSTL_2_5V\n"));
 455                 break;
 456             default:
 457                 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
 458                 DP(printf("Module is                                    VOLTAGE_UNKNOWN\n"));
 459                 break;
 460             }
 461             break;
 462 /*------------------------------------------------------------------------------------------------------------------------------*/
 463
 464         case 9:  /* Minimum Cycle Time At Max CasLatancy */
 465             shift = (dimmInfo->memoryType == DDR)? 4:2;
 466             mult = (dimmInfo->memoryType == DDR)? 10:25;
 467             maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xf0:0xfc;
 468             maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0xf:0x03;
 469             leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 470             rightOfPoint = (data[i] & maskRightOfPoint)* mult;
 471             dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = leftOfPoint;
 472             dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint;
 473             DP(printf("Minimum Cycle Time At Max CasLatancy:            %d.%d [ns]\n",leftOfPoint, rightOfPoint));
 474             break;
 475 /*------------------------------------------------------------------------------------------------------------------------------*/
 476
 477         case 10: /* Clock To Data Out */
 478             div = (dimmInfo->memoryType == DDR)? 100:10;
 479             time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
 480             leftOfPoint     = time_tmp / div;
 481             rightOfPoint    = time_tmp % div;
 482             dimmInfo->clockToDataOut_LoP = leftOfPoint;
 483             dimmInfo->clockToDataOut_RoP = rightOfPoint;
 484             DP(printf("Clock To Data Out:                               %d.%2d [ns]\n",leftOfPoint,  rightOfPoint ));
 485             /*dimmInfo->clockToDataOut*/
 486             break;
 487 /*------------------------------------------------------------------------------------------------------------------------------*/
 488
 489 #ifdef CONFIG_ECC
 490         case 11: /* Error Check Type */
 491             dimmInfo->errorCheckType = data[i];
 492         DP(printf("Error Check Type (0=NONE):                   %d\n", dimmInfo->errorCheckType));
 493             break;
 494 #endif
 495 /*------------------------------------------------------------------------------------------------------------------------------*/
 496
 497         case 12: /* Refresh Interval */
 498             dimmInfo->RefreshInterval = data[i];
 499         DP(printf("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", dimmInfo->RefreshInterval));
 500             break;
 501 /*------------------------------------------------------------------------------------------------------------------------------*/
 502
 503         case 13: /* Sdram Width */
 504             dimmInfo->sdramWidth = data[i];
 505         DP(printf("Sdram Width:                                         %d\n", dimmInfo->sdramWidth));
 506             break;
 507 /*------------------------------------------------------------------------------------------------------------------------------*/
 508
 509         case 14: /* Error Check Data Width */
 510             dimmInfo->errorCheckDataWidth = data[i];
 511         DP(printf("Error Check Data Width:                      %d\n", dimmInfo->errorCheckDataWidth));
 512             break;
 513 /*------------------------------------------------------------------------------------------------------------------------------*/
 514
 515         case 15: /* Minimum Clock Delay */
 516             dimmInfo->minClkDelay = data[i];
 517         DP(printf("Minimum Clock Delay:                                 %d\n", dimmInfo->minClkDelay));
 518             break;
 519 /*------------------------------------------------------------------------------------------------------------------------------*/
 520
 521         case 16: /* Burst Length Supported */
 522                            /******-******-******-*******
 523                            * bit3 | bit2 | bit1 | bit0 *
 524                            *******-******-******-*******
 525             burst length = *  8   |  4   |   2  |   1  *
 526                            *****************************
 527
 528             If for example bit0 and bit2 are set, the burst
 529             length supported are 1 and 4. */
 530
 531             dimmInfo->burstLengthSupported = data[i];
 532 #ifdef DEBUG
 533         DP(printf("Burst Length Supported:                      "));
 534         if (dimmInfo->burstLengthSupported & 0x01)
 535                 DP(printf("1, "));
 536         if (dimmInfo->burstLengthSupported & 0x02)
 537                 DP(printf("2, "));
 538         if (dimmInfo->burstLengthSupported & 0x04)
 539                 DP(printf("4, "));
 540         if (dimmInfo->burstLengthSupported & 0x08)
 541                 DP(printf("8, "));
 542         DP(printf(" Bit \n"));
 543 #endif
 544             break;
 545 /*------------------------------------------------------------------------------------------------------------------------------*/
 546
 547         case 17: /* Number Of Banks On Each Device */
 548             dimmInfo->numOfBanksOnEachDevice = data[i];
 549             DP(printf("Number Of Banks On Each Chip:                    %d\n", dimmInfo->numOfBanksOnEachDevice));
 550             break;
 551 /*------------------------------------------------------------------------------------------------------------------------------*/
 552
 553         case 18: /* Suported Cas Latencies */
 554
 555           /*     DDR:
 556                    *******-******-******-******-******-******-******-*******
 557                    * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 558                    *******-******-******-******-******-******-******-*******
 559            CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 560                    *********************************************************
 561            SDRAM:
 562                    *******-******-******-******-******-******-******-*******
 563                    * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 564                    *******-******-******-******-******-******-******-*******
 565            CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
 566                    ********************************************************/
 567           dimmInfo->suportedCasLatencies = data[i];
 568 #ifdef DEBUG
 569           DP(printf("Suported Cas Latencies: (CL)                       "));
 570           if (dimmInfo->memoryType == 0)                /* SDRAM*/
 571             {
 572               for (k = 0; k <=7; k++)
 573                 {
 574                   if (dimmInfo->suportedCasLatencies & (1 << k))
 575                     DP(printf("%d,                      ", k+1));
 576                 }
 577
 578             }
 579           else                                  /* DDR-RAM*/
 580             {
 581               if (dimmInfo->suportedCasLatencies & 1)
 582                 DP(printf("1, "));
 583               if (dimmInfo->suportedCasLatencies & 2)
 584                 DP(printf("1.5, "));
 585               if (dimmInfo->suportedCasLatencies & 4)
 586                 DP(printf("2, "));
 587               if (dimmInfo->suportedCasLatencies & 8)
 588                 DP(printf("2.5, "));
 589               if (dimmInfo->suportedCasLatencies & 16)
 590                 DP(printf("3, "));
 591               if (dimmInfo->suportedCasLatencies & 32)
 592                 DP(printf("3.5, "));
 593
 594             }
 595           DP(printf("\n"));
 596 #endif
 597           /* Calculating MAX CAS latency */
 598           for(j = 7 ; j > 0 ; j--)
 599             {
 600               if(((dimmInfo->suportedCasLatencies >> j) & 0x1) == 1)
 601                 {
 602                   switch(dimmInfo->memoryType)
 603                     {
 604                     case DDR:
 605                       /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
 606                       switch (j)
 607                         {
 608                         case 7:
 609                           DP(printf("Max. Cas Latencies (DDR):                  ERROR !!!\n"));
 610                           dimmInfo->maxClSupported_DDR = DDR_CL_FAULT;
 611                           hang();
 612                           break;
 613                         case 6:
 614                           DP(printf("Max. Cas Latencies (DDR):                  ERROR !!!\n"));
 615                           dimmInfo->maxClSupported_DDR = DDR_CL_FAULT;
 616                           hang();
 617                           break;
 618                         case 5:
 619                           DP(printf("Max. Cas Latencies (DDR):                  3.5 clk's\n"));
 620                           dimmInfo->maxClSupported_DDR = DDR_CL_3_5;
 621                           break;
 622                         case 4:
 623                           DP(printf("Max. Cas Latencies (DDR):                  3 clk's \n"));
 624                           dimmInfo->maxClSupported_DDR = DDR_CL_3;
 625                           break;
 626                         case 3:
 627                           DP(printf("Max. Cas Latencies (DDR):                  2.5 clk's \n"));
 628                           dimmInfo->maxClSupported_DDR = DDR_CL_2_5;
 629                           break;
 630                         case 2:
 631                           DP(printf("Max. Cas Latencies (DDR):                  2 clk's \n"));
 632                           dimmInfo->maxClSupported_DDR = DDR_CL_2;
 633                           break;
 634                         case 1:
 635                           DP(printf("Max. Cas Latencies (DDR):                  1.5 clk's \n"));
 636                           dimmInfo->maxClSupported_DDR = DDR_CL_1_5;
 637                           break;
 638                         }
 639                       dimmInfo->maxCASlatencySupported_LoP = 1 + (int) (5 * j /10);
 640                       if (((5*j) % 10) != 0)
 641                         dimmInfo->maxCASlatencySupported_RoP =  5;
 642                       else
 643                         dimmInfo->maxCASlatencySupported_RoP =  0;
 644                       DP(printf("Max. Cas Latencies (DDR LoP.RoP Notation):     %d.%d \n", dimmInfo->maxCASlatencySupported_LoP, dimmInfo->maxCASlatencySupported_RoP));
 645                       break;
 646                     case SDRAM:
 647                       /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
 648                       dimmInfo->maxClSupported_SD = j;                  /*  Cas Latency DDR-RAM Coded                   */
 649                       DP(printf("Max. Cas Latencies (SD): %d\n", dimmInfo->maxClSupported_SD));
 650                       dimmInfo->maxCASlatencySupported_LoP =  j ;
 651                       dimmInfo->maxCASlatencySupported_RoP =  0;
 652                       DP(printf("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo->maxCASlatencySupported_LoP, dimmInfo->maxCASlatencySupported_RoP));
 653                       break;
 654                     }
 655                   break;
 656                 }
 657             }
 658           break;
 659 /*------------------------------------------------------------------------------------------------------------------------------*/
 660
 661         case 21: /* Buffered Address And Control Inputs */
 662             DP(printf("\nModul Attributes (SPD Byte 21): \n"));
 663             dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0;
 664             dimmInfo->registeredAddrAndControlInputs = (data[i] & BIT1) >> 1;
 665             dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
 666             dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
 667             dimmInfo->registeredDQMBinputs = (data[i] & BIT4) >> 4;
 668             dimmInfo->differentialClockInput = (data[i] & BIT5) >> 5;
 669             dimmInfo->redundantRowAddressing = (data[i] & BIT6) >> 6;
 670 #ifdef DEBUG
 671             if (dimmInfo->bufferedAddrAndControlInputs == 1)
 672                    DP(printf(" - Buffered Address/Control Input:                Yes \n"));
 673             else
 674                    DP(printf(" - Buffered Address/Control Input:                No \n"));
 675
 676             if (dimmInfo->registeredAddrAndControlInputs == 1)
 677                    DP(printf(" - Registered Address/Control Input:              Yes \n"));
 678             else
 679                    DP(printf(" - Registered Address/Control Input:              No \n"));
 680
 681             if (dimmInfo->onCardPLL == 1)
 682                    DP(printf(" - On-Card PLL (clock):                           Yes \n"));
 683             else
 684                    DP(printf(" - On-Card PLL (clock):                           No \n"));
 685
 686             if (dimmInfo->bufferedDQMBinputs == 1)
 687                    DP(printf(" - Bufferd DQMB Inputs:                           Yes \n"));
 688             else
 689                    DP(printf(" - Bufferd DQMB Inputs:                           No \n"));
 690
 691             if (dimmInfo->registeredDQMBinputs == 1)
 692                    DP(printf(" - Registered DQMB Inputs:                        Yes \n"));
 693             else
 694                    DP(printf(" - Registered DQMB Inputs:                        No \n"));
 695
 696             if (dimmInfo->differentialClockInput == 1)
 697                    DP(printf(" - Differential Clock Input:                      Yes \n"));
 698             else
 699                    DP(printf(" - Differential Clock Input:                      No \n"));
 700
 701             if (dimmInfo->redundantRowAddressing == 1)
 702                    DP(printf(" - redundant Row Addressing:                      Yes \n"));
 703             else
 704                    DP(printf(" - redundant Row Addressing:                      No \n"));
 705
 706 #endif
 707             break;
 708 /*------------------------------------------------------------------------------------------------------------------------------*/
 709
 710         case 22: /* Suported AutoPreCharge */
 711             DP(printf("\nModul Attributes (SPD Byte 22): \n"));
 712             dimmInfo->suportedEarlyRasPreCharge= data[i] & BIT0;
 713             dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1;
 714             dimmInfo->suportedPreChargeAll = (data[i] & BIT2) >> 2;
 715             dimmInfo->suportedWrite1ReadBurst= (data[i] & BIT3) >> 3;
 716             dimmInfo->suported5PercentLowVCC= (data[i] & BIT4) >> 4;
 717             dimmInfo->suported5PercentUpperVCC= (data[i] & BIT5) >> 5;
 718 #ifdef DEBUG
 719             if (dimmInfo->suportedEarlyRasPreCharge == 1)
 720                    DP(printf(" - Early Ras Precharge:                   Yes \n"));
 721             else
 722                    DP(printf(" -  Early Ras Precharge:                  No \n"));
 723
 724             if (dimmInfo->suportedAutoPreCharge == 1)
 725                    DP(printf(" - AutoPreCharge:                         Yes \n"));
 726             else
 727                    DP(printf(" -  AutoPreCharge:                                No \n"));
 728
 729             if (dimmInfo->suportedPreChargeAll == 1)
 730                    DP(printf(" - Precharge All:                         Yes \n"));
 731             else
 732                    DP(printf(" -  Precharge All:                                No \n"));
 733
 734             if (dimmInfo->suportedWrite1ReadBurst == 1)
 735                    DP(printf(" - Write 1/ReadBurst:                             Yes \n"));
 736             else
 737                    DP(printf(" -  Write 1/ReadBurst:                            No \n"));
 738
 739             if (dimmInfo->suported5PercentLowVCC == 1)
 740                    DP(printf(" - lower VCC tolerance:                   5 Percent \n"));
 741             else
 742                    DP(printf("  - lower VCC tolerance:                  10 Percent \n"));
 743
 744             if (dimmInfo->suported5PercentUpperVCC == 1)
 745                    DP(printf(" - upper VCC tolerance:                   5 Percent \n"));
 746             else
 747                    DP(printf(" -  upper VCC tolerance:                  10 Percent \n"));
 748
 749 #endif
 750             break;
 751 /*------------------------------------------------------------------------------------------------------------------------------*/
 752
 753         case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
 754             shift = (dimmInfo->memoryType == DDR)? 4:2;
 755             mult = (dimmInfo->memoryType == DDR)? 10:25;
 756             maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xf0:0xfc;
 757             maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0xf:0x03;
 758             leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 759             rightOfPoint = (data[i] & maskRightOfPoint)* mult;
 760             dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = leftOfPoint;
 761             dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint;
 762             DP(printf("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",leftOfPoint, rightOfPoint ));
 763             /*dimmInfo->minimumCycleTimeAtMaxCasLatancy*/
 764             break;
 765 /*------------------------------------------------------------------------------------------------------------------------------*/
 766
 767         case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/
 768             div = (dimmInfo->memoryType == DDR)? 100:10;
 769             time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
 770             leftOfPoint     = time_tmp / div;
 771             rightOfPoint    = time_tmp % div;
 772             dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
 773             dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
 774             DP(printf("Clock To Data Out (2nd CL value):                %d.%2d [ns]\n",leftOfPoint,  rightOfPoint ));
 775             break;
 776 /*------------------------------------------------------------------------------------------------------------------------------*/
 777
 778         case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
 779             shift = (dimmInfo->memoryType == DDR)? 4:2;
 780             mult = (dimmInfo->memoryType == DDR)? 10:25;
 781             maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xf0:0xfc;
 782             maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0xf:0x03;
 783             leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 784             rightOfPoint = (data[i] & maskRightOfPoint)* mult;
 785             dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = leftOfPoint;
 786             dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint;
 787             DP(printf("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",leftOfPoint, rightOfPoint ));
 788             /*dimmInfo->minimumCycleTimeAtMaxCasLatancy*/
 789             break;
 790 /*------------------------------------------------------------------------------------------------------------------------------*/
 791
 792         case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/
 793             div = (dimmInfo->memoryType == DDR)? 100:10;
 794             time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
 795             leftOfPoint     = time_tmp / div;
 796             rightOfPoint    = time_tmp % div;
 797             dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
 798             dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
 799             DP(printf("Clock To Data Out (3rd CL value):                %d.%2d [ns]\n",leftOfPoint,  rightOfPoint ));
 800             break;
 801 /*------------------------------------------------------------------------------------------------------------------------------*/
 802
 803         case 27: /* Minimum Row Precharge Time */
 804             shift = (dimmInfo->memoryType == DDR)? 2:0;
 805             maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xfc:0xff;
 806             maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0x03:0x00;
 807             leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 808             rightOfPoint = (data[i] & maskRightOfPoint)*25;
 809
 810             dimmInfo->minRowPrechargeTime = ((leftOfPoint*100) + rightOfPoint); /* measured in n times 10ps Intervals */
 811         trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk-1)) /  tmemclk;
 812         DP(printf("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n", tmemclk, tmemclk/100, tmemclk%100 ));
 813         DP(printf("Minimum Row Precharge Time [ns]:             %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks));
 814             break;
 815 /*------------------------------------------------------------------------------------------------------------------------------*/
 816
 817         case 28: /* Minimum Row Active to Row Active Time */
 818             shift = (dimmInfo->memoryType == DDR)? 2:0;
 819             maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xfc:0xff;
 820             maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0x03:0x00;
 821             leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 822             rightOfPoint = (data[i] & maskRightOfPoint)*25;
 823
 824             dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint*100) + rightOfPoint);  /* measured in 100ns Intervals */
 825         trrd_clocks = (dimmInfo->minRowActiveRowActiveDelay + (tmemclk-1)) / tmemclk;
 826         DP(printf("Minimum Row Active -To- Row Active Delay [ns]:       %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks));
 827             break;
 828 /*------------------------------------------------------------------------------------------------------------------------------*/
 829
 830         case 29: /* Minimum Ras-To-Cas Delay */
 831             shift = (dimmInfo->memoryType == DDR)? 2:0;
 832             maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xfc:0xff;
 833             maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0x03:0x00;
 834             leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 835             rightOfPoint = (data[i] & maskRightOfPoint)*25;
 836
 837             dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint*100) + rightOfPoint);  /* measured in 100ns Intervals */
 838         trcd_clocks = (dimmInfo->minRowActiveRowActiveDelay + (tmemclk-1) )/ tmemclk;
 839         DP(printf("Minimum Ras-To-Cas Delay [ns]:                       %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks));
 840             break;
 841 /*------------------------------------------------------------------------------------------------------------------------------*/
 842
 843         case 30: /* Minimum Ras Pulse Width */
 844             dimmInfo->minRasPulseWidth = data[i];
 845         tras_clocks = (NSto10PS(data[i])+(tmemclk-1)) / tmemclk;
 846         DP(printf("Minimum Ras Pulse Width [ns]:                        %d = in Clk cycles %d\n", dimmInfo->minRasPulseWidth, tras_clocks));
 847
 848             break;
 849 /*------------------------------------------------------------------------------------------------------------------------------*/
 850
 851         case 31: /* Module Bank Density */
 852             dimmInfo->moduleBankDensity = data[i];
 853         DP(printf("Module Bank Density:                                 %d\n", dimmInfo->moduleBankDensity));
 854 #ifdef DEBUG
 855         DP(printf("*** Offered Densities (more than 1 = Multisize-Module): "));
 856         {
 857                 if (dimmInfo->moduleBankDensity & 1)
 858                         DP(printf("4MB, "));
 859                 if (dimmInfo->moduleBankDensity & 2)
 860                         DP(printf("8MB, "));
 861                 if (dimmInfo->moduleBankDensity & 4)
 862                         DP(printf("16MB, "));
 863                 if (dimmInfo->moduleBankDensity & 8)
 864                         DP(printf("32MB, "));
 865                 if (dimmInfo->moduleBankDensity & 16)
 866                         DP(printf("64MB, "));
 867                 if (dimmInfo->moduleBankDensity & 32)
 868                         DP(printf("128MB, "));
 869                 if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) {
 870                         DP(printf("ERROR, "));
 871                                 hang();
 872                         }
 873         }
 874         DP(printf("\n"));
 875 #endif
 876             break;
 877 /*------------------------------------------------------------------------------------------------------------------------------*/
 878
 879         case 32: /* Address And Command Setup Time (measured in ns/1000) */
 880             sign = 1;
 881             switch(dimmInfo->memoryType)
 882             {
 883             case DDR:
 884                   time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
 885                 leftOfPoint = time_tmp / 100;
 886                 rightOfPoint = time_tmp % 100;
 887                 break;
 888             case SDRAM:
 889                 leftOfPoint = (data[i] & 0xf0) >> 4;
 890                 if(leftOfPoint > 7)
 891                 {
 892                     leftOfPoint = data[i] & 0x70 >> 4;
 893                     sign = -1;
 894                 }
 895                 rightOfPoint = (data[i] & 0x0f);
 896                 break;
 897             }
 898             dimmInfo->addrAndCommandSetupTime = (leftOfPoint*100 + rightOfPoint) * sign;
 899         DP(printf("Address And Command Setup Time [ns]:                 %d.%d\n", sign*leftOfPoint, rightOfPoint));
 900             break;
 901 /*------------------------------------------------------------------------------------------------------------------------------*/
 902
 903         case 33: /* Address And Command Hold Time */
 904             sign = 1;
 905             switch(dimmInfo->memoryType)
 906             {
 907             case DDR:
 908                   time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
 909                 leftOfPoint = time_tmp / 100;
 910                 rightOfPoint = time_tmp % 100;
 911                 break;
 912             case SDRAM:
 913                 leftOfPoint = (data[i] & 0xf0) >> 4;
 914                 if(leftOfPoint > 7)
 915                 {
 916                     leftOfPoint = data[i] & 0x70 >> 4;
 917                     sign = -1;
 918                 }
 919                 rightOfPoint = (data[i] & 0x0f) ;
 920                 break;
 921             }
 922             dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign;
 923         DP(printf("Address And Command Hold Time [ns]:          %d.%d\n", sign*leftOfPoint, rightOfPoint));
 924             break;
 925 /*------------------------------------------------------------------------------------------------------------------------------*/
 926
 927         case 34: /* Data Input Setup Time */
 928             sign = 1;
 929             switch(dimmInfo->memoryType)
 930             {
 931             case DDR:
 932                   time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
 933                 leftOfPoint = time_tmp / 100;
 934                 rightOfPoint = time_tmp % 100;
 935                 break;
 936             case SDRAM:
 937                 leftOfPoint = (data[i] & 0xf0) >> 4;
 938                 if( leftOfPoint > 7)
 939                 {
 940                     leftOfPoint = data[i] & 0x70 >> 4;
 941                     sign = -1;
 942                 }
 943                 rightOfPoint = (data[i] & 0x0f );
 944                 break;
 945             }
 946             dimmInfo->dataInputSetupTime = (leftOfPoint *100 + rightOfPoint) * sign;
 947         DP(printf("Data Input Setup Time [ns]:                  %d.%d\n", sign*leftOfPoint, rightOfPoint));
 948             break;
 949 /*------------------------------------------------------------------------------------------------------------------------------*/
 950
 951         case 35: /* Data Input Hold Time */
 952             sign = 1;
 953             switch(dimmInfo->memoryType)
 954             {
 955             case DDR:
 956                   time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
 957                 leftOfPoint = time_tmp / 100;
 958                 rightOfPoint = time_tmp % 100;
 959                 break;
 960             case SDRAM:
 961                 leftOfPoint = (data[i] & 0xf0) >> 4;
 962                 if( leftOfPoint > 7)
 963                 {
 964                     leftOfPoint = data[i] & 0x70 >> 4;
 965                     sign = -1;
 966                 }
 967                 rightOfPoint = (data[i] & 0x0f) ;
 968                 break;
 969             }
 970             dimmInfo->dataInputHoldTime = (leftOfPoint *100 + rightOfPoint) * sign;
 971         DP(printf("Data Input Hold Time [ns]:                   %d.%d\n\n", sign*leftOfPoint, rightOfPoint));
 972             break;
 973 /*------------------------------------------------------------------------------------------------------------------------------*/
 974         }
 975     }
 976     /* calculating the sdram density */
 977     for(i = 0;i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;i++)
 978     {
 979         density = density*2;
 980     }
 981     dimmInfo->deviceDensity = density*dimmInfo->numOfBanksOnEachDevice*
 982                              dimmInfo->sdramWidth;
 983     dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth)*
 984                                  dimmInfo->numOfModuleBanks;
 985     devicesForErrCheck = (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth ;
 986     if((dimmInfo->errorCheckType == 0x1) ||
 987        (dimmInfo->errorCheckType == 0x2) ||
 988        (dimmInfo->errorCheckType == 0x3))
 989     {
 990         dimmInfo->size = (dimmInfo->deviceDensity / 8)*
 991                          (dimmInfo->numberOfDevices - devicesForErrCheck);
 992     }
 993     else
 994     {
 995         dimmInfo->size = (dimmInfo->deviceDensity/8)*dimmInfo->numberOfDevices;
 996     }
 997
 998     /* compute the module DRB size */
 999     tmp = (1 << (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1000     tmp *= dimmInfo->numOfModuleBanks;
1001     tmp *= dimmInfo->sdramWidth;
1002     tmp = tmp >> 24;    /* div by 0x4000000 (64M)       */
1003     dimmInfo->drb_size = (uchar)tmp;
1004     DP(printf("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
1005
1006         /* try a CAS latency of 3 first... */
1007
1008         /* bit 1 is CL2, bit 2 is CL3 */
1009         supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1010
1011         cal_val = 0;
1012         if (supp_cal & 8) {
1013                 if (NS10to10PS(data[9]) <= tmemclk)
1014                         cal_val = 6;
1015         }
1016         if (supp_cal & 4) {
1017                 if (NS10to10PS(data[9]) <= tmemclk)
1018                         cal_val = 5;
1019         }
1020
1021         /* then 2... */
1022         if (supp_cal & 2) {
1023                 if (NS10to10PS(data[23]) <= tmemclk)
1024                         cal_val = 4;
1025         }
1026
1027         DP(printf("cal_val = %d\n", cal_val*5));
1028
1029         /* bummer, did't work... */
1030         if (cal_val == 0) {
1031                 DP(printf("Couldn't find a good CAS latency\n"));
1032                         hang();
1033                 return 0;
1034         }
1035
1036     return true;
1037 }
1038
1039 /* sets up the GT properly with information passed in */
1040 int
1041 setup_sdram(AUX_MEM_DIMM_INFO *info)
1042 {
1043         ulong tmp, check;
1044               ulong tmp_sdram_mode=0;           /* 0x141c*/
1045               ulong tmp_dunit_control_low=0;    /* 0x1404*/
1046         int i;
1047
1048         /* sanity checking */
1049         if (! info->numOfModuleBanks) {
1050                 printf("setup_sdram called with 0 banks\n");
1051                 return 1;
1052         }
1053
1054         /* delay line */
1055
1056         /* Program the GT with the discovered data */
1057         if (info->registeredAddrAndControlInputs == true)
1058                 DP(printf("Module is registered, but we do not support registered Modules !!!\n"));
1059
1060
1061         /* delay line */
1062         set_dfcdlInit(); /* may be its not needed */
1063         DP(printf("Delay line set done\n"));
1064
1065         /* set SDRAM mode NOP*/ /* To_do check it*/
1066         GT_REG_WRITE(SDRAM_OPERATION, 0x5);
1067         while (GTREGREAD(SDRAM_OPERATION) != 0) {
1068                 DP(printf("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
1069                 }
1070
1071         /* SDRAM configuration */
1072         GT_REG_WRITE(SDRAM_CONFIG, 0x58200400);
1073         DP(printf("sdram_conf 0x1400: %08x\n", GTREGREAD(SDRAM_CONFIG)));
1074
1075         /* SDRAM open pages controll keep open as much as I can*/
1076         GT_REG_WRITE(SDRAM_OPEN_PAGES_CONTROL, 0x0);
1077         DP(printf("sdram_open_pages_controll 0x1414: %08x\n", GTREGREAD(SDRAM_OPEN_PAGES_CONTROL)));
1078
1079
1080         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1081         tmp = (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x01);           /* Clock Domain Sync from power on reset*/
1082         if (tmp == 0)
1083                 DP(printf("Core Signals are sync (by HW-Setting)!!!\n"));
1084         else
1085                 DP(printf("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
1086
1087         /* SDRAM set CAS Lentency according to SPD information*/
1088         switch(info->memoryType)
1089           {
1090           case SDRAM:
1091             DP(printf("### SD-RAM not supported yet !!!\n"));
1092             hang();
1093             /* ToDo fill SD-RAM if needed !!!!!*/
1094             break;
1095
1096           case DDR:
1097             DP(printf("### SET-CL for DDR-RAM\n"));
1098
1099             switch (info->maxClSupported_DDR)
1100               {
1101               case DDR_CL_3:
1102                 tmp_dunit_control_low = 0x3c000000;             /* Read-Data sampled on falling edge of Clk*/
1103                 tmp_sdram_mode = 0x32;                          /* CL=3 Burstlength = 4*/
1104                 DP(printf("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1105                 break;
1106
1107               case DDR_CL_2_5:
1108                 if (tmp == 1)   /* clocks sync*/
1109                   {
1110                     tmp_dunit_control_low = 0x24000000;         /* Read-Data sampled on falling edge of Clk*/
1111                     tmp_sdram_mode = 0x62;                      /* CL=2,5 Burstlength = 4*/
1112                     DP(printf("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1113                   }
1114                 else    /* clk sync. bypassed   */
1115                   {
1116                     tmp_dunit_control_low = 0x03000000;         /* Read-Data sampled on rising edge of Clk*/
1117                     tmp_sdram_mode = 0x62;                      /* CL=2,5 Burstlength = 4*/
1118                     DP(printf("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1119                   }
1120                 break;
1121
1122               case DDR_CL_2:
1123                 if (tmp == 1)   /* Sync*/
1124                   {
1125                     tmp_dunit_control_low = 0x03000000;         /* Read-Data sampled on rising edge of Clk*/
1126                     tmp_sdram_mode = 0x22;                      /* CL=2 Burstlength = 4*/
1127                     DP(printf("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1128                   }
1129                 else    /* Not sync.    */
1130                   {
1131                     tmp_dunit_control_low = 0x3b000000;         /* Read-Data sampled on rising edge of Clk*/
1132                     tmp_sdram_mode = 0x22;                      /* CL=2 Burstlength = 4*/
1133                     DP(printf("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1134                   }
1135                 break;
1136
1137               case DDR_CL_1_5:
1138                 if (tmp == 1)   /* Sync*/
1139                   {
1140                     tmp_dunit_control_low = 0x23000000;         /* Read-Data sampled on falling edge of Clk*/
1141                     tmp_sdram_mode = 0x52;                      /* CL=1,5 Burstlength = 4*/
1142                     DP(printf("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1143                   }
1144                 else    /* not sync*/
1145                   {
1146                     tmp_dunit_control_low = 0x1a000000;         /* Read-Data sampled on rising edge of Clk*/
1147                     tmp_sdram_mode = 0x52;                      /* CL=1,5 Burstlength = 4*/
1148                     DP(printf("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1149                   }
1150                 break;
1151
1152               default:
1153                 printf("Max. CL is out of range %d\n", info->maxClSupported_DDR);
1154                 hang();
1155                 break;
1156               }
1157             break;
1158           }
1159
1160         /* Write results of CL detection procedure */
1161         GT_REG_WRITE(SDRAM_MODE, tmp_sdram_mode);
1162         /* set SDRAM mode SetCommand 0x1418*/
1163         GT_REG_WRITE(SDRAM_OPERATION, 0x3);
1164         while (GTREGREAD(SDRAM_OPERATION) != 0) {
1165                 DP(printf("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1166                 }
1167
1168
1169         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1170         tmp = (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x01);           /* Clock Domain Sync from power on reset*/
1171         if (tmp != 1)   /*clocks are not sync*/
1172          {
1173                 /* asyncmode*/
1174                 GT_REG_WRITE(D_UNIT_CONTROL_LOW ,
1175                 (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x7F) | 0x18110780 | tmp_dunit_control_low );
1176          }
1177         else
1178          {
1179                 /* syncmode*/
1180                 GT_REG_WRITE(D_UNIT_CONTROL_LOW ,
1181                 (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x7F) | 0x00110000 | tmp_dunit_control_low );
1182           }
1183
1184         /* set SDRAM mode SetCommand 0x1418*/
1185         GT_REG_WRITE(SDRAM_OPERATION, 0x3);
1186         while (GTREGREAD(SDRAM_OPERATION) != 0) {
1187                 DP(printf("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
1188                 }
1189
1190 /*------------------------------------------------------------------------------ */
1191
1192
1193         /* bank parameters */
1194         /* SDRAM address decode register */
1195         /* program this with the default value */
1196         tmp = 0x02;
1197
1198
1199         DP(printf("drb_size (n*64Mbit): %d\n", info->drb_size));
1200         switch (info->drb_size) {
1201         case 1:                 /* 64 Mbit */
1202         case 2:                 /* 128 Mbit */
1203                 DP(printf("RAM-Device_size 64Mbit or 128Mbit)\n"));
1204                 tmp |= (0x00 << 4);
1205                 break;
1206         case 4:                 /* 256 Mbit */
1207         case 8:                 /* 512 Mbit */
1208                 DP(printf("RAM-Device_size 256Mbit or 512Mbit)\n"));
1209                 tmp |= (0x01 << 4);
1210                 break;
1211         case 16:                        /* 1 Gbit */
1212         case 32:                        /* 2 Gbit */
1213                 DP(printf("RAM-Device_size 1Gbit or 2Gbit)\n"));
1214                 tmp |= (0x02 << 4);
1215                 break;
1216         default:
1217                 printf("Error in dram size calculation\n");
1218                 DP(printf("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
1219                 tmp |= (0x02 << 4);
1220                 return 1;
1221         }
1222
1223         /* SDRAM bank parameters */
1224         /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1225         DP(printf("setting up slot %d config with: %08lx \n", info->slot, tmp));
1226         GT_REG_WRITE(SDRAM_ADDR_CONTROL, tmp);
1227
1228 /* ------------------------------------------------------------------------------ */
1229
1230         DP(printf("setting up sdram_timing_control_low with: %08x \n", 0x11511220));
1231         GT_REG_WRITE(SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1232
1233
1234 /* ------------------------------------------------------------------------------ */
1235
1236         /* SDRAM configuration */
1237         tmp = GTREGREAD(SDRAM_CONFIG);
1238
1239         if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) {
1240         tmp |= (1 << 17);
1241         DP(printf("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",info->registeredAddrAndControlInputs, info->registeredDQMBinputs));
1242         }
1243
1244         /* Use buffer 1 to return read data to the CPU
1245          * Page 426 MV64360 */
1246         tmp |= (1 << 26);
1247         DP(printf("Before Buffer assignment - sdram_conf: %08x\n", GTREGREAD(SDRAM_CONFIG)));
1248         DP(printf("After Buffer assignment - sdram_conf: %08x\n", GTREGREAD(SDRAM_CONFIG)));
1249
1250         /* SDRAM timing To_do:*/
1251
1252
1253         tmp = GTREGREAD(SDRAM_TIMING_CONTROL_HIGH);
1254         DP(printf("# sdram_timing_control_high is : %08lx \n", tmp));
1255
1256         /* SDRAM address decode register */
1257         /* program this with the default value */
1258         tmp = GTREGREAD(SDRAM_ADDR_CONTROL);
1259         DP(printf("SDRAM address control (before: decode): %08x  ",  GTREGREAD(SDRAM_ADDR_CONTROL)));
1260         GT_REG_WRITE(SDRAM_ADDR_CONTROL, (tmp | 0x2));
1261         DP(printf("SDRAM address control (after: decode): %08x\n",  GTREGREAD(SDRAM_ADDR_CONTROL)));
1262
1263         /* set the SDRAM configuration for each bank */
1264
1265 /*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1266         {
1267                 i = info->slot;
1268                 DP(printf("\n*** Running a MRS cycle for bank %d ***\n", i));
1269
1270                 /* map the bank */
1271                 memory_map_bank(i, 0, GB/4);
1272 #if 1 /* test only */
1273                 /* set SDRAM mode */ /* To_do check it*/
1274                 GT_REG_WRITE(SDRAM_OPERATION, 0x3);
1275                 check = GTREGREAD(SDRAM_OPERATION);
1276                 DP(printf("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", check));
1277
1278
1279                 /* switch back to normal operation mode */
1280                 GT_REG_WRITE(SDRAM_OPERATION, 0);
1281                 check = GTREGREAD(SDRAM_OPERATION);
1282                 DP(printf("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", check));
1283 #endif /* test only */
1284                 /* unmap the bank */
1285                 memory_map_bank(i, 0, 0);
1286         }
1287
1288         return 0;
1289 }
1290
1291 /*
1292  * Check memory range for valid RAM. A simple memory test determines
1293  * the actually available RAM size between addresses `base' and
1294  * `base + maxsize'. Some (not all) hardware errors are detected:
1295  * - short between address lines
1296  * - short between data lines
1297  */
1298 long int
1299 dram_size(long int *base, long int maxsize)
1300 {
1301     volatile long int    *addr, *b=base;
1302     long int     cnt, val, save1, save2;
1303
1304 #define STARTVAL (1<<20)        /* start test at 1M */
1305     for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1306             addr = base + cnt;  /* pointer arith! */
1307
1308             save1=*addr;                /* save contents of addr */
1309             save2=*b;           /* save contents of base */
1310
1311             *addr=cnt;          /* write cnt to addr */
1312             *b=0;                       /* put null at base */
1313
1314             /* check at base address */
1315             if ((*b) != 0) {
1316                 *addr=save1;    /* restore *addr */
1317                 *b=save2;       /* restore *b */
1318                 return (0);
1319             }
1320             val = *addr;                /* read *addr */
1321             val = *addr;                /* read *addr */
1322
1323             *addr=save1;
1324             *b=save2;
1325
1326             if (val != cnt) {
1327                     DP(printf("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
1328                     /* fix boundary condition.. STARTVAL means zero */
1329                     if(cnt==STARTVAL/sizeof(long)) cnt=0;
1330                     return (cnt * sizeof(long));
1331             }
1332     }
1333     return maxsize;
1334 }
1335
1336 /* ------------------------------------------------------------------------- */
1337
1338 /* ppcboot interface function to SDRAM init - this is where all the
1339  * controlling logic happens */
1340 long int
1341 initdram(int board_type)
1342 {
1343         int s0 = 0, s1 = 0;
1344         int checkbank[4] = { [0 ... 3] = 0 };
1345                 ulong bank_no, realsize, total, check;
1346         AUX_MEM_DIMM_INFO dimmInfo1;
1347         AUX_MEM_DIMM_INFO dimmInfo2;
1348         int nhr;
1349
1350         /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1351
1352         /* check the NHR bit and skip mem init if it's already done */
1353         nhr = get_hid0() & (1 << 16);
1354
1355         if (nhr) {
1356                 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1357         } else {
1358                 /* DIMM0 */
1359                 s0 = check_dimm(0, &dimmInfo1);
1360
1361                 /* DIMM1 */
1362                 s1 = check_dimm(1, &dimmInfo2);
1363
1364                 memory_map_bank(0, 0, 0);
1365                 memory_map_bank(1, 0, 0);
1366                 memory_map_bank(2, 0, 0);
1367                 memory_map_bank(3, 0, 0);
1368
1369                 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1370                         printf("Setup for DIMM1 failed.\n");
1371                 }
1372
1373                 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1374                         printf("Setup for DIMM2 failed.\n");
1375                 }
1376
1377                 /* set the NHR bit */
1378                 set_hid0(get_hid0() | (1 << 16));
1379         }
1380         /* next, size the SDRAM banks */
1381
1382         realsize = total = 0;
1383         check = GB/4;
1384         if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1385         if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1386         if (dimmInfo1.numOfModuleBanks > 2)
1387                 printf("Error, SPD claims DIMM1 has >2 banks\n");
1388
1389         if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1390         if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1391         if (dimmInfo2.numOfModuleBanks > 2)
1392                 printf("Error, SPD claims DIMM2 has >2 banks\n");
1393
1394         for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
1395                 /* skip over banks that are not populated */
1396                 if (! checkbank[bank_no])
1397                         continue;
1398
1399                 if ((total + check) > CFG_GT_REGS)
1400                         check = CFG_GT_REGS - total;
1401
1402                 memory_map_bank(bank_no, total, check);
1403                 realsize = dram_size((long int *)total, check);
1404                 memory_map_bank(bank_no, total, realsize);
1405
1406                 total += realsize;
1407         }
1408
1409 /*      Setup Ethernet DMA Adress window to DRAM Area */
1410         return(total);
1411 }
1412
1413 /* ***************************************************************************************
1414 ! *                             SDRAM INIT                                              *
1415 ! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb       *
1416 ! *               This procedure fits only the Atlantis                                *
1417 ! *                                                                                     *
1418 ! *************************************************************************************** */
1419
1420
1421 /* ***************************************************************************************
1422 ! *                             DFCDL initialize MV643xx Design Considerations             *
1423 ! *                                                                                     *
1424 ! *************************************************************************************** */
1425 int
1426 set_dfcdlInit(void)
1427 {
1428      int i;
1429      unsigned int dfcdl_word = 0x0000014f;
1430       for (i=0 ; i < 64; i++)
1431       {
1432         GT_REG_WRITE(SRAM_DATA0, dfcdl_word);
1433       }
1434      GT_REG_WRITE(DFCDL_CONFIG0, 0x00300000);   /* enable dynamic delay line updating */
1435
1436
1437      return (0);
1438 }
1439