3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
12 /* ------------------------------------------------------------------------- */
16 #define _NOT_USED_ 0xFFFFFFFF
18 /* ------------------------------------------------------------------------- */
20 /* fpga configuration data - generated by bit2inc */
21 static unsigned char fpgadata[] = {
25 #define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
26 #define LOAD_LONG(a) a
29 /******************************************************************************
31 * sysFpgaBoot - Load fpga-image into fpga
34 static int fpgaBoot (void)
40 imageSize = sizeof (fpgadata);
42 /* display infos on fpgaimage */
44 for (i = 0; i < 4; i++) {
45 len = fpgadata[index];
49 /* search for preamble 0xFF2X */
50 for (index = 0; index < imageSize - 1; index++) {
51 if ((fpgadata[index] == 0xff)
52 && ((fpgadata[index + 1] & 0xf0) == 0x20))
56 /* enable cs1 instead of user0... */
57 *(unsigned long *) 0x50000084 &= ~0x00000002;
61 ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
65 /* init fpga by asserting and deasserting PROGRAM* (USER2)... */
66 *(unsigned long *) 0x50000084 &= ~0x00000400;
67 udelay (FPGA_PRG_SLEEP * 1000);
69 *(unsigned long *) 0x50000084 |= 0x00000400;
70 udelay (FPGA_PRG_SLEEP * 1000);
74 ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
78 /* cs1: disable burst, disable ready */
79 *(unsigned long *) 0x50000114 &= ~0x00000300;
81 /* cs1: set write timing */
82 *(unsigned long *) 0x50000118 |= 0x00010900;
84 /* write configuration-data into fpga... */
85 for (i = index; i < imageSize; i++) {
87 for (j = 0; j < 8; j++) {
88 *(unsigned long *) 0x30000000 =
90 ? LOAD_LONG (0x03030101)
91 : LOAD_LONG (0x02020000);
98 ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
102 /* set cs1 to 32 bit data-width, disable burst, enable ready */
103 *(unsigned long *) 0x50000114 |= 0x00000202;
104 *(unsigned long *) 0x50000114 &= ~0x00000100;
106 /* cs1: set iop access to little endian */
107 *(unsigned long *) 0x50000114 &= ~0x00000010;
109 /* cs1: set read and write timing */
110 *(unsigned long *) 0x50000118 = 0x00010000;
111 *(unsigned long *) 0x5000011c = 0x00010001;
115 ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
116 "NOT DONE" : "DONE");
119 /* wait for 30 ms... */
121 /* check if fpga's DONE signal - correctly booted ? */
122 if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
129 int board_early_init_f (void)
134 *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
135 *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
136 *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
137 *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
138 *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
139 *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
140 *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
147 * Check Board Identity:
150 int checkboard (void)
155 int i = getenv_f("serial#", str, sizeof (str));
166 if (!i || strncmp (str, "DASA_SIM", 8)) {
167 puts ("### No HW ID - assuming DASA_SIM");
173 val = *(unsigned short *) 0x30000202;
174 printf (" (Id=%d Version=%d Revision=%d)",
175 (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
179 /* display infos on fpgaimage */
181 for (i = 0; i < 4; i++) {
182 len = fpgadata[index];
183 printf ("%s ", &(fpgadata[index + 1]));
187 puts ("\nFPGA: Booting failed!");
195 phys_size_t initdram (int board_type)
197 return (16 * 1024 * 1024);