3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/processor.h>
24 #include <asm/bitops.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
33 extern ulong flash_get_size (ulong base, int banknum);
35 int usbhub_init(void);
37 int eeprom_write_enable (unsigned dev_addr, int state);
38 int board_revision(void);
40 static int du440_post_errors;
42 int board_early_init_f(void)
45 u32 sdr0_pfc1, sdr0_pfc2;
48 mtdcr(EBC0_CFGADDR, EBC0_CFG);
49 mtdcr(EBC0_CFGDATA, 0xb8400000);
54 out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
55 out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
56 out_be32((void*)GPIO0_OSRL, 0x50055400);
57 out_be32((void*)GPIO0_OSRH, 0x55005000);
58 out_be32((void*)GPIO0_TSRL, 0x50055400);
59 out_be32((void*)GPIO0_TSRH, 0x55005000);
60 out_be32((void*)GPIO0_ISR1L, 0x50000000);
61 out_be32((void*)GPIO0_ISR1H, 0x00000000);
62 out_be32((void*)GPIO0_ISR2L, 0x00000000);
63 out_be32((void*)GPIO0_ISR2H, 0x00000000);
64 out_be32((void*)GPIO0_ISR3L, 0x00000000);
65 out_be32((void*)GPIO0_ISR3H, 0x00000000);
67 out_be32((void*)GPIO1_OR, 0x00000000);
68 out_be32((void*)GPIO1_TCR, 0xc2000000 |
69 CONFIG_SYS_GPIO1_IORSTN |
70 CONFIG_SYS_GPIO1_IORST2N |
71 CONFIG_SYS_GPIO1_LEDUSR1 |
72 CONFIG_SYS_GPIO1_LEDUSR2 |
73 CONFIG_SYS_GPIO1_LEDPOST |
74 CONFIG_SYS_GPIO1_LEDDU);
75 out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
76 out_be32((void*)GPIO1_OSRL, 0x0c280000);
77 out_be32((void*)GPIO1_OSRH, 0x00000000);
78 out_be32((void*)GPIO1_TSRL, 0xcc000000);
79 out_be32((void*)GPIO1_TSRH, 0x00000000);
80 out_be32((void*)GPIO1_ISR1L, 0x00005550);
81 out_be32((void*)GPIO1_ISR1H, 0x00000000);
82 out_be32((void*)GPIO1_ISR2L, 0x00050000);
83 out_be32((void*)GPIO1_ISR2H, 0x00000000);
84 out_be32((void*)GPIO1_ISR3L, 0x01400000);
85 out_be32((void*)GPIO1_ISR3H, 0x00000000);
88 * Setup the interrupt controller polarities, triggers, etc.
90 mtdcr(UIC0SR, 0xffffffff); /* clear all */
91 mtdcr(UIC0ER, 0x00000000); /* disable all */
92 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
93 mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
94 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
95 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
96 mtdcr(UIC0SR, 0xffffffff); /* clear all */
100 * bit30: ext. Irq 1: PLD : int 32+30
102 mtdcr(UIC1SR, 0xffffffff); /* clear all */
103 mtdcr(UIC1ER, 0x00000000); /* disable all */
104 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
105 mtdcr(UIC1PR, 0xfffffffd);
106 mtdcr(UIC1TR, 0x00000000);
107 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
108 mtdcr(UIC1SR, 0xffffffff); /* clear all */
112 * bit3: ext. Irq 2: DCF77 : int 64+3
114 mtdcr(UIC2SR, 0xffffffff); /* clear all */
115 mtdcr(UIC2ER, 0x00000000); /* disable all */
116 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
117 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
118 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
119 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
120 mtdcr(UIC2SR, 0xffffffff); /* clear all */
122 /* select Ethernet pins */
123 mfsdr(SDR0_PFC1, sdr0_pfc1);
124 mfsdr(SDR0_PFC2, sdr0_pfc2);
126 /* setup EMAC bridge interface */
127 if (board_revision() == 0) {
129 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
130 SDR0_PFC1_SELECT_CONFIG_1_2;
131 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
132 SDR0_PFC2_SELECT_CONFIG_1_2;
135 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
136 SDR0_PFC1_SELECT_CONFIG_6;
137 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
138 SDR0_PFC2_SELECT_CONFIG_6;
142 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
144 mtsdr(SDR0_PFC2, sdr0_pfc2);
145 mtsdr(SDR0_PFC1, sdr0_pfc1);
147 /* PCI arbiter enabled */
148 mfsdr(SDR0_PCI0, reg);
149 mtsdr(SDR0_PCI0, 0x80000000 | reg);
151 /* setup NAND FLASH */
152 mfsdr(SDR0_CUST0, sdr0_cust0);
153 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
154 SDR0_CUST0_NDFC_ENABLE |
155 SDR0_CUST0_NDFC_BW_8_BIT |
156 SDR0_CUST0_NDFC_ARE_MASK |
157 (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
158 (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
159 mtsdr(SDR0_CUST0, sdr0_cust0);
164 int misc_init_r(void)
169 unsigned long usb2d0cr = 0;
170 unsigned long usb2phy0cr, usb2h0cr = 0;
171 unsigned long sdr0_pfc1;
172 unsigned long sdr0_srst0, sdr0_srst1;
175 /* adjust flash start and offset */
176 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
177 gd->bd->bi_flashoffset = 0;
179 mtdcr(EBC0_CFGADDR, PB0CR);
180 pbcr = mfdcr(EBC0_CFGDATA);
181 size_val = ffs(gd->bd->bi_flashsize) - 21;
182 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
183 mtdcr(EBC0_CFGADDR, PB0CR);
184 mtdcr(EBC0_CFGDATA, pbcr);
187 * Re-check to get correct base address
189 flash_get_size(gd->bd->bi_flashstart, 0);
195 mfsdr(SDR0_PFC1, sdr0_pfc1);
196 mfsdr(SDR0_USB0, usb2d0cr);
197 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
198 mfsdr(SDR0_USB2H0CR, usb2h0cr);
200 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
201 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
202 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
203 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
204 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
205 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
206 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
207 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
208 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
209 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
211 /* An 8-bit/60MHz interface is the only possible alternative
212 when connecting the Device to the PHY */
213 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
214 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
216 /* To enable the USB 2.0 Device function through the UTMI interface */
217 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
219 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
220 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
222 mtsdr(SDR0_PFC1, sdr0_pfc1);
223 mtsdr(SDR0_USB0, usb2d0cr);
224 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
225 mtsdr(SDR0_USB2H0CR, usb2h0cr);
228 * Take USB out of reset:
229 * -Initial status = all cores are in reset
230 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
232 * -deassert reset to PHY
234 * -deassert reset to HOST
236 * -deassert all other resets
238 mfsdr(SDR0_SRST1, sdr0_srst1);
239 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
240 SDR0_SRST1_P4OPB0 | \
242 SDR0_SRST1_PLB42OPB1 | \
243 SDR0_SRST1_OPB2PLB40);
244 mtsdr(SDR0_SRST1, sdr0_srst1);
247 mfsdr(SDR0_SRST1, sdr0_srst1);
248 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
249 mtsdr(SDR0_SRST1, sdr0_srst1);
252 mfsdr(SDR0_SRST0, sdr0_srst0);
253 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
254 mtsdr(SDR0_SRST0, sdr0_srst0);
257 /* finally all the other resets */
258 mtsdr(SDR0_SRST1, 0x00000000);
259 mtsdr(SDR0_SRST0, 0x00000000);
261 printf("USB: Host(int phy)\n");
264 * Clear PLB4A0_ACR[WRP]
265 * This fix will make the MAL burst disabling patch for the Linux
266 * EMAC driver obsolete.
268 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
269 mtdcr(PLB4_ACR, reg);
273 * We have to wait at least 560ms until we may call usbhub_init
275 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
276 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
279 * flash USR1/2 LEDs (600ms)
280 * This results in the necessary delay from IORST# until
281 * calling usbhub_init will succeed
283 for (j = 0; j < 3; j++) {
284 out_be32((void*)GPIO1_OR,
285 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
286 CONFIG_SYS_GPIO1_LEDUSR1);
288 for (i = 0; i < 100; i++)
291 out_be32((void*)GPIO1_OR,
292 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
293 CONFIG_SYS_GPIO1_LEDUSR2);
295 for (i = 0; i < 100; i++)
299 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
300 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
311 int pld_revision(void)
313 out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
314 return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
317 int board_revision(void)
319 int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
320 >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
322 return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
323 ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
326 #if defined(CONFIG_SHOW_ACTIVITY)
327 void board_show_activity (ulong timestamp)
329 if ((timestamp % 100) == 0)
330 out_be32((void*)GPIO1_OR,
331 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
334 void show_activity(int arg)
337 #endif /* CONFIG_SHOW_ACTIVITY */
339 int du440_phy_addr(int devnum)
341 if (board_revision() == 0)
351 puts("Board: DU440");
353 if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
358 printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
359 board_revision(), pld_revision());
366 * This routine is called just prior to registering the hose and gives
367 * the board the opportunity to check things. Returning a value of zero
368 * indicates that things are bad & PCI initialization should be aborted.
370 * Different boards may wish to customize the pci controller structure
371 * (add regions, override default access routines, etc) or perform
372 * certain pre-initialization actions.
374 #if defined(CONFIG_PCI)
375 int pci_pre_init(struct pci_controller *hose)
380 * Set priority for all PLB3 devices to 0.
381 * Set PLB3 arbiter to fair mode.
383 mfsdr(SD0_AMP1, addr);
384 mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
385 addr = mfdcr(PLB3_ACR);
386 mtdcr(PLB3_ACR, addr | 0x80000000);
389 * Set priority for all PLB4 devices to 0.
391 mfsdr(SD0_AMP0, addr);
392 mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
393 addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
394 mtdcr(PLB4_ACR, addr);
397 * Set Nebula PLB4 arbiter to fair mode.
400 addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
401 addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
402 addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
403 addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
404 mtdcr(PLB0_ACR, addr);
407 addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
408 addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
409 addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
410 addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
411 mtdcr(PLB1_ACR, addr);
415 #endif /* defined(CONFIG_PCI) */
420 * The bootstrap configuration provides default settings for the pci
421 * inbound map (PIM). But the bootstrap config choices are limited and
422 * may not be sufficient for a given board.
424 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
425 void pci_target_init(struct pci_controller *hose)
428 * Set up Direct MMIO registers
431 * PowerPC440EPX PCI Master configuration.
432 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
433 * PLB address 0xA0000000-0xDFFFFFFF
434 * ==> PCI address 0xA0000000-0xDFFFFFFF
435 * Use byte reversed out routines to handle endianess.
436 * Make this region non-prefetchable.
438 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
439 /* - disabled b4 setting */
440 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
441 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
442 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
443 out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
444 /* and enable region */
446 out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
447 /* - disabled b4 setting */
448 out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
449 out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
450 out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
451 out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
452 /* and enable region */
454 out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
455 out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
456 out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
457 out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
460 * Set up Configuration registers
463 /* Program the board's subsystem id/vendor id */
464 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
465 PCI_VENDOR_ID_ESDGMBH);
466 pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
468 pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
470 /* Configure command register as bus master */
471 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
473 /* 240nS PCI clock */
474 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
476 /* No error reporting */
477 pci_write_config_word(0, PCI_ERREN, 0);
479 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
482 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
484 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
485 void pci_master_init(struct pci_controller *hose)
487 unsigned short temp_short;
490 * Write the PowerPC440 EP PCI Configuration regs.
491 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
492 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
494 pci_read_config_word(0, PCI_COMMAND, &temp_short);
495 pci_write_config_word(0, PCI_COMMAND,
496 temp_short | PCI_COMMAND_MASTER |
499 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
501 int last_stage_init(void)
505 /* everyting is ok: turn on POST-LED */
506 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
508 /* slowly blink on errors and finally keep LED off */
509 for (e = 0; e < du440_post_errors; e++) {
510 out_be32((void*)GPIO1_OR,
511 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
513 for (i = 0; i < 500; i++)
516 out_be32((void*)GPIO1_OR,
517 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
519 for (i = 0; i < 500; i++)
526 #if defined(CONFIG_I2C_MULTI_BUS)
528 * read field strength from I2C ADC
530 int dcf77_status(void)
536 oldbus = I2C_GET_BUS();
539 if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
544 mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
550 int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
554 unsigned long long t1, t2;
560 printf("signal=%d mV\n", mv);
562 printf("ERROR - no signal\n");
565 pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
567 pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
568 if (pin && !pinold) { /* bit start */
570 if (t2 && ((unsigned int)(t1 - t2) /
571 (bd->bi_procfreq / 1000) >= 1800))
572 printf("Start of minute\n");
576 if (t1 && !pin && pinold) { /* bit end */
577 printf("%5d\n", (unsigned int)(get_ticks() - t1) /
578 (bd->bi_procfreq / 1000));
587 dcf77, 1, 1, do_dcf77,
588 "Check DCF77 receiver",
593 * initialize USB hub via I2C1
595 int usbhub_init(void)
600 uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
601 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
607 oldbus = I2C_GET_BUS();
610 for (reg = 0; reg < sizeof(u); reg++)
611 if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
618 if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
623 printf("initialized\n");
625 printf("failed - cannot initialize USB hub\n");
631 int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
637 hubinit, 1, 1, do_hubinit,
638 "Initialize USB hub",
641 #endif /* CONFIG_I2C_MULTI_BUS */
643 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
644 int boot_eeprom_write (unsigned dev_addr,
649 unsigned end = offset + cnt;
653 #if defined(CONFIG_SYS_EEPROM_WREN)
654 eeprom_write_enable(dev_addr, 1);
657 * Write data until done or would cross a write page boundary.
658 * We must write the address again when changing pages
659 * because the address counter only increments within a page.
662 while (offset < end) {
668 blk_off = offset & 0xFF; /* block offset */
670 addr[0] = offset >> 8; /* block number */
671 addr[1] = blk_off; /* block offset */
673 addr[0] |= dev_addr; /* insert device address */
678 * For a FRAM device there is no limit on the number of the
679 * bytes that can be ccessed with the single read or write
682 #if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
684 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
685 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
687 maxlen = BOOT_EEPROM_PAGE_SIZE -
688 BOOT_EEPROM_PAGE_OFFSET(blk_off);
690 maxlen = 0x100 - blk_off;
692 if (maxlen > I2C_RXTX_LEN)
693 maxlen = I2C_RXTX_LEN;
698 if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
704 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
705 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
708 #if defined(CONFIG_SYS_EEPROM_WREN)
709 eeprom_write_enable(dev_addr, 0);
714 int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
719 if (!strcmp(argv[1], "533")) {
720 printf("Bootstrapping for 533MHz\n");
721 sdsdp[0] = 0x87788252;
722 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
723 sdsdp[1] = 0x095fa030;
724 sdsdp[2] = 0x40082350;
725 sdsdp[3] = 0x0d050000;
726 } else if (!strcmp(argv[1], "533-66")) {
727 printf("Bootstrapping for 533MHz (66MHz PCI)\n");
728 sdsdp[0] = 0x87788252;
729 /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
730 sdsdp[1] = 0x0957a030;
731 sdsdp[2] = 0x40082350;
732 sdsdp[3] = 0x0d050000;
733 } else if (!strcmp(argv[1], "667")) {
734 printf("Bootstrapping for 667MHz\n");
735 sdsdp[0] = 0x8778a256;
736 /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
737 sdsdp[1] = 0x0947a030;
738 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
739 * -> not working when overclocking 533MHz chips
740 * -> untested on 667MHz chips */
741 /* sdsdp[1]=0x095fa030; */
742 sdsdp[2] = 0x40082350;
743 sdsdp[3] = 0x0d050000;
744 } else if (!strcmp(argv[1], "667-166")) {
745 printf("Bootstrapping for 667-166MHz\n");
746 sdsdp[0] = 0x8778a252;
747 sdsdp[1] = 0x09d7a030;
748 sdsdp[2] = 0x40082350;
749 sdsdp[3] = 0x0d050000;
752 printf("Bootstrapping for 533MHz (default)\n");
753 sdsdp[0] = 0x87788252;
754 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
755 sdsdp[1] = 0x095fa030;
756 sdsdp[2] = 0x40082350;
757 sdsdp[3] = 0x0d050000;
760 printf("Writing boot EEPROM ...\n");
761 if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
762 0, (uchar*)sdsdp, 16) != 0)
763 printf("boot_eeprom_write failed\n");
765 printf("done (dump via 'i2c md 52 0.1 10')\n");
770 sbe, 2, 0, do_setup_boot_eeprom,
775 #if defined(CONFIG_SYS_EEPROM_WREN)
777 * Input: <dev_addr> I2C address of EEPROM device to enable.
778 * <state> -1: deliver current state
781 * Returns: -1: wrong device address
782 * 0: dis-/en- able done
783 * 0/1: current state if <state> was -1.
785 int eeprom_write_enable (unsigned dev_addr, int state)
787 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
788 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
793 /* Enable write access, clear bit GPIO_SINT2. */
794 out_be32((void*)GPIO0_OR,
795 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
799 /* Disable write access, set bit GPIO_SINT2. */
800 out_be32((void*)GPIO0_OR,
801 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
805 /* Read current status back. */
806 state = (0 == (in_be32((void*)GPIO0_OR) &
807 CONFIG_SYS_GPIO0_EP_EEP));
814 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
816 int query = argc == 1;
820 /* Query write access state. */
821 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
823 puts ("Query of write access state failed.\n");
825 printf ("Write access for device 0x%0x is %sabled.\n",
826 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
830 if ('0' == argv[1][0]) {
831 /* Disable write access. */
832 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
834 /* Enable write access. */
835 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
838 puts ("Setup of write access state failed.\n");
844 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
845 "Enable / disable / query EEPROM write access",
848 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
850 static int got_pldirq;
852 static int pld_interrupt(u32 arg)
854 int rc = -1; /* not for us */
855 u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
857 /* check for PLD interrupt */
858 if (status & PWR_INT_FLAG) {
860 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
862 got_pldirq = 1; /* trigger backend */
868 int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
872 /* clear any pending interrupt */
873 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
875 irq_install_handler(CPLD_IRQ,
876 (interrupt_handler_t *)pld_interrupt, 0);
878 printf("Waiting ...\n");
880 /* Abort if ctrl-c was pressed */
887 printf("Got interrupt!\n");
888 printf("Power %sready!\n",
889 in_8((void *)CONFIG_SYS_CPLD_BASE) &
890 PWR_RDY ? "":"NOT ");
893 irq_free_handler(CPLD_IRQ);
897 wpi, 1, 1, do_waitpwrirq,
898 "Wait for power change interrupt",
903 * initialize DVI panellink transmitter
910 uchar u[] = {0x08, 0x34,
918 oldbus = I2C_GET_BUS();
921 for (i = 0; i < sizeof(u); i += 2)
922 if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
928 printf("initialized\n");
930 printf("failed - cannot initialize DVI transmitter\n");
936 int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
942 dviinit, 1, 1, do_dviinit,
943 "Initialize DVI Panellink transmitter",
948 * TODO: 'time' command might be useful for others as well.
949 * Move to 'common' directory.
951 int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
953 unsigned long long start, end;
954 char c, cmd[CONFIG_SYS_CBSIZE];
959 for (i = 1; i < argc; i++) {
965 while ((c = *p++) != '\0') {
972 ret = run_command (cmd, 0);
975 printf("ticks=%ld\n", (ulong)(end - start));
976 us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
977 printf("usec=%ld\n", us);
982 time, CONFIG_SYS_MAXARGS, 1, do_time,
983 "run command and output execution time",
987 extern void video_hw_rectfill (
988 unsigned int bpp, /* bytes per pixel */
989 unsigned int dst_x, /* dest pos x */
990 unsigned int dst_y, /* dest pos y */
991 unsigned int dim_x, /* frame width */
992 unsigned int dim_y, /* frame height */
993 unsigned int color /* fill color */
998 * draw rectangles using pseudorandom number generator
999 * (see http://www.embedded.com/columns/technicalinsights/20900500)
1001 unsigned int rprime = 9972;
1002 static unsigned int r;
1003 static unsigned int Y;
1005 unsigned int prng(unsigned int max)
1007 if (r == 0 || r == 1 || r == -1)
1008 r = rprime; /* keep from getting stuck */
1010 r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
1011 Y = (r >> 16) % max; /* choose upper bits and reduce */
1015 int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
1018 unsigned int x, y, dx, dy;
1023 dx = prng(1280- x - 1);
1024 dy = prng(1024 - y - 1);
1025 color = prng(0x10000);
1026 video_hw_rectfill(2, x, y, dx, dy, color);
1032 gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,