3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/processor.h>
24 #include <asm/bitops.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
33 extern ulong flash_get_size (ulong base, int banknum);
35 int usbhub_init(void);
37 int eeprom_write_enable (unsigned dev_addr, int state);
38 int board_revision(void);
40 static int du440_post_errors;
42 int board_early_init_f(void)
45 u32 sdr0_pfc1, sdr0_pfc2;
48 mtdcr(ebccfga, xbcfg);
49 mtdcr(ebccfgd, 0xb8400000);
54 out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
55 out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
56 out_be32((void*)GPIO0_OSRL, 0x50055400);
57 out_be32((void*)GPIO0_OSRH, 0x550050aa);
58 out_be32((void*)GPIO0_TSRL, 0x50055400);
59 out_be32((void*)GPIO0_TSRH, 0x55005000);
60 out_be32((void*)GPIO0_ISR1L, 0x50000000);
61 out_be32((void*)GPIO0_ISR1H, 0x00000000);
62 out_be32((void*)GPIO0_ISR2L, 0x00000000);
63 out_be32((void*)GPIO0_ISR2H, 0x00000100);
64 out_be32((void*)GPIO0_ISR3L, 0x00000000);
65 out_be32((void*)GPIO0_ISR3H, 0x00000000);
67 out_be32((void*)GPIO1_OR, 0x00000000);
68 out_be32((void*)GPIO1_TCR, 0xc2000000 |
75 out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
76 out_be32((void*)GPIO1_OSRL, 0x5c280000);
77 out_be32((void*)GPIO1_OSRH, 0x00000000);
78 out_be32((void*)GPIO1_TSRL, 0x0c000000);
79 out_be32((void*)GPIO1_TSRH, 0x00000000);
80 out_be32((void*)GPIO1_ISR1L, 0x00005550);
81 out_be32((void*)GPIO1_ISR1H, 0x00000000);
82 out_be32((void*)GPIO1_ISR2L, 0x00050000);
83 out_be32((void*)GPIO1_ISR2H, 0x00000000);
84 out_be32((void*)GPIO1_ISR3L, 0x01400000);
85 out_be32((void*)GPIO1_ISR3H, 0x00000000);
88 * Setup the interrupt controller polarities, triggers, etc.
90 mtdcr(uic0sr, 0xffffffff); /* clear all */
91 mtdcr(uic0er, 0x00000000); /* disable all */
92 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
93 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
94 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
95 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
96 mtdcr(uic0sr, 0xffffffff); /* clear all */
100 * bit30: ext. Irq 1: PLD : int 32+30
102 mtdcr(uic1sr, 0xffffffff); /* clear all */
103 mtdcr(uic1er, 0x00000000); /* disable all */
104 mtdcr(uic1cr, 0x00000000); /* all non-critical */
105 mtdcr(uic1pr, 0xfffffffd);
106 mtdcr(uic1tr, 0x00000000);
107 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
108 mtdcr(uic1sr, 0xffffffff); /* clear all */
112 * bit3: ext. Irq 2: DCF77 : int 64+3
114 mtdcr(uic2sr, 0xffffffff); /* clear all */
115 mtdcr(uic2er, 0x00000000); /* disable all */
116 mtdcr(uic2cr, 0x00000000); /* all non-critical */
117 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
118 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
119 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
120 mtdcr(uic2sr, 0xffffffff); /* clear all */
122 /* select Ethernet pins */
123 mfsdr(SDR0_PFC1, sdr0_pfc1);
124 mfsdr(SDR0_PFC2, sdr0_pfc2);
126 /* setup EMAC bridge interface */
127 if (board_revision() == 0) {
129 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
130 SDR0_PFC1_SELECT_CONFIG_1_2;
131 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
132 SDR0_PFC2_SELECT_CONFIG_1_2;
135 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
136 SDR0_PFC1_SELECT_CONFIG_6;
137 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
138 SDR0_PFC2_SELECT_CONFIG_6;
142 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
144 mtsdr(SDR0_PFC2, sdr0_pfc2);
145 mtsdr(SDR0_PFC1, sdr0_pfc1);
147 /* PCI arbiter enabled */
148 mfsdr(sdr_pci0, reg);
149 mtsdr(sdr_pci0, 0x80000000 | reg);
151 /* setup NAND FLASH */
152 mfsdr(SDR0_CUST0, sdr0_cust0);
153 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
154 SDR0_CUST0_NDFC_ENABLE |
155 SDR0_CUST0_NDFC_BW_8_BIT |
156 SDR0_CUST0_NDFC_ARE_MASK |
157 (0x80000000 >> (28 + CFG_NAND0_CS)) |
158 (0x80000000 >> (28 + CFG_NAND1_CS));
159 mtsdr(SDR0_CUST0, sdr0_cust0);
164 int misc_init_r(void)
169 unsigned long usb2d0cr = 0;
170 unsigned long usb2phy0cr, usb2h0cr = 0;
171 unsigned long sdr0_pfc1;
174 /* adjust flash start and offset */
175 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
176 gd->bd->bi_flashoffset = 0;
178 mtdcr(ebccfga, pb0cr);
179 pbcr = mfdcr(ebccfgd);
180 size_val = ffs(gd->bd->bi_flashsize) - 21;
181 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
182 mtdcr(ebccfga, pb0cr);
183 mtdcr(ebccfgd, pbcr);
186 * Re-check to get correct base address
188 flash_get_size(gd->bd->bi_flashstart, 0);
194 mfsdr(SDR0_PFC1, sdr0_pfc1);
195 mfsdr(SDR0_USB0, usb2d0cr);
196 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
197 mfsdr(SDR0_USB2H0CR, usb2h0cr);
199 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
200 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
201 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
202 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
203 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
204 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
205 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
206 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
207 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
208 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
210 /* An 8-bit/60MHz interface is the only possible alternative
211 when connecting the Device to the PHY */
212 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
213 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
215 /* To enable the USB 2.0 Device function through the UTMI interface */
216 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
218 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
219 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
221 mtsdr(SDR0_PFC1, sdr0_pfc1);
222 mtsdr(SDR0_USB0, usb2d0cr);
223 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
224 mtsdr(SDR0_USB2H0CR, usb2h0cr);
228 mtsdr(SDR0_SRST1, 0x00000000);
230 mtsdr(SDR0_SRST0, 0x00000000);
232 printf("USB: Host(int phy)\n");
235 * Clear PLB4A0_ACR[WRP]
236 * This fix will make the MAL burst disabling patch for the Linux
237 * EMAC driver obsolete.
239 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
240 mtdcr(plb4_acr, reg);
244 * We have to wait at least 560ms until we may call usbhub_init
246 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
247 CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N);
250 * flash USR1/2 LEDs (600ms)
251 * This results in the necessary delay from IORST# until
252 * calling usbhub_init will succeed
254 for (j = 0; j < 3; j++) {
255 out_be32((void*)GPIO1_OR,
256 (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
259 for (i = 0; i < 100; i++)
262 out_be32((void*)GPIO1_OR,
263 (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
266 for (i = 0; i < 100; i++)
270 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
271 ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
282 int pld_revision(void)
284 out8(CFG_CPLD_BASE, 0x00);
285 return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
288 int board_revision(void)
290 int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
291 >> CFG_GPIO1_HWVER_SHIFT);
293 return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
294 ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
297 #if defined(CONFIG_SHOW_ACTIVITY)
298 void board_show_activity (ulong timestamp)
300 if ((timestamp % 100) == 0)
301 out_be32((void*)GPIO1_OR,
302 in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
305 void show_activity(int arg)
308 #endif /* CONFIG_SHOW_ACTIVITY */
310 int du440_phy_addr(int devnum)
312 if (board_revision() == 0)
322 puts("Board: DU440");
324 if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
329 printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
330 board_revision(), pld_revision());
337 * This routine is called just prior to registering the hose and gives
338 * the board the opportunity to check things. Returning a value of zero
339 * indicates that things are bad & PCI initialization should be aborted.
341 * Different boards may wish to customize the pci controller structure
342 * (add regions, override default access routines, etc) or perform
343 * certain pre-initialization actions.
345 #if defined(CONFIG_PCI)
346 int pci_pre_init(struct pci_controller *hose)
351 * Set priority for all PLB3 devices to 0.
352 * Set PLB3 arbiter to fair mode.
354 mfsdr(sdr_amp1, addr);
355 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
356 addr = mfdcr(plb3_acr);
357 mtdcr(plb3_acr, addr | 0x80000000);
360 * Set priority for all PLB4 devices to 0.
362 mfsdr(sdr_amp0, addr);
363 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
364 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
365 mtdcr(plb4_acr, addr);
368 * Set Nebula PLB4 arbiter to fair mode.
371 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
372 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
373 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
374 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
375 mtdcr(plb0_acr, addr);
378 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
379 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
380 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
381 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
382 mtdcr(plb1_acr, addr);
386 #endif /* defined(CONFIG_PCI) */
391 * The bootstrap configuration provides default settings for the pci
392 * inbound map (PIM). But the bootstrap config choices are limited and
393 * may not be sufficient for a given board.
395 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
396 void pci_target_init(struct pci_controller *hose)
399 * Set up Direct MMIO registers
402 * PowerPC440EPX PCI Master configuration.
403 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
404 * PLB address 0xA0000000-0xDFFFFFFF
405 * ==> PCI address 0xA0000000-0xDFFFFFFF
406 * Use byte reversed out routines to handle endianess.
407 * Make this region non-prefetchable.
409 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
410 /* - disabled b4 setting */
411 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
412 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
413 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
414 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
415 /* and enable region */
417 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
418 /* - disabled b4 setting */
419 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
420 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
421 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
422 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
423 /* and enable region */
425 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
426 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
427 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
428 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
431 * Set up Configuration registers
434 /* Program the board's subsystem id/vendor id */
435 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
436 PCI_VENDOR_ID_ESDGMBH);
437 pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
439 pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
441 /* Configure command register as bus master */
442 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
444 /* 240nS PCI clock */
445 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
447 /* No error reporting */
448 pci_write_config_word(0, PCI_ERREN, 0);
450 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
453 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
455 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
456 void pci_master_init(struct pci_controller *hose)
458 unsigned short temp_short;
461 * Write the PowerPC440 EP PCI Configuration regs.
462 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
463 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
465 pci_read_config_word(0, PCI_COMMAND, &temp_short);
466 pci_write_config_word(0, PCI_COMMAND,
467 temp_short | PCI_COMMAND_MASTER |
470 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
475 * This routine is called to determine if a pci scan should be
476 * performed. With various hardware environments (especially cPCI and
477 * PPMC) it's insufficient to depend on the state of the arbiter enable
478 * bit in the strap register, or generic host/adapter assumptions.
480 * Rather than hard-code a bad assumption in the general 440 code, the
481 * 440 pci code requires the board to decide at runtime.
483 * Return 0 for adapter mode, non-zero for host (monarch) mode.
485 #if defined(CONFIG_PCI)
486 int is_pci_host(struct pci_controller *hose)
488 /* always configured as host. */
491 #endif /* defined(CONFIG_PCI) */
493 int last_stage_init(void)
497 /* everyting is ok: turn on POST-LED */
498 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
500 /* slowly blink on errors and finally keep LED off */
501 for (e = 0; e < du440_post_errors; e++) {
502 out_be32((void*)GPIO1_OR,
503 in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
505 for (i = 0; i < 500; i++)
508 out_be32((void*)GPIO1_OR,
509 in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
511 for (i = 0; i < 500; i++)
518 #if defined(CONFIG_I2C_MULTI_BUS)
520 * read field strength from I2C ADC
522 int dcf77_status(void)
528 oldbus = I2C_GET_BUS();
531 if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
536 mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
542 int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
546 unsigned long long t1, t2;
552 printf("signal=%d mV\n", mv);
554 printf("ERROR - no signal\n");
557 pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
559 pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
560 if (pin && !pinold) { /* bit start */
562 if (t2 && ((unsigned int)(t1 - t2) /
563 (bd->bi_procfreq / 1000) >= 1800))
564 printf("Start of minute\n");
568 if (t1 && !pin && pinold) { /* bit end */
569 printf("%5d\n", (unsigned int)(get_ticks() - t1) /
570 (bd->bi_procfreq / 1000));
579 dcf77, 1, 1, do_dcf77,
580 "dcf77 - Check DCF77 receiver\n",
585 * initialize USB hub via I2C1
587 int usbhub_init(void)
592 uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
593 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
599 oldbus = I2C_GET_BUS();
602 for (reg = 0; reg < sizeof(u); reg++)
603 if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
610 if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
615 printf("initialized\n");
617 printf("failed - cannot initialize USB hub\n");
623 int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
629 hubinit, 1, 1, do_hubinit,
630 "hubinit - Initialize USB hub\n",
633 #endif /* CONFIG_I2C_MULTI_BUS */
635 #define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
636 int boot_eeprom_write (unsigned dev_addr,
641 unsigned end = offset + cnt;
645 #if defined(CFG_EEPROM_WREN)
646 eeprom_write_enable(dev_addr, 1);
649 * Write data until done or would cross a write page boundary.
650 * We must write the address again when changing pages
651 * because the address counter only increments within a page.
654 while (offset < end) {
660 blk_off = offset & 0xFF; /* block offset */
662 addr[0] = offset >> 8; /* block number */
663 addr[1] = blk_off; /* block offset */
665 addr[0] |= dev_addr; /* insert device address */
670 * For a FRAM device there is no limit on the number of the
671 * bytes that can be ccessed with the single read or write
674 #if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
676 #define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
677 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
679 maxlen = BOOT_EEPROM_PAGE_SIZE -
680 BOOT_EEPROM_PAGE_OFFSET(blk_off);
682 maxlen = 0x100 - blk_off;
684 if (maxlen > I2C_RXTX_LEN)
685 maxlen = I2C_RXTX_LEN;
690 if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
696 #if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
697 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
700 #if defined(CFG_EEPROM_WREN)
701 eeprom_write_enable(dev_addr, 0);
706 int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
711 if (!strcmp(argv[1], "533")) {
712 printf("Bootstrapping for 533MHz\n");
713 sdsdp[0] = 0x87788252;
714 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
715 sdsdp[1] = 0x095fa030;
716 sdsdp[2] = 0x40082350;
717 sdsdp[3] = 0x0d050000;
718 } else if (!strcmp(argv[1], "533-66")) {
719 printf("Bootstrapping for 533MHz (66MHz PCI)\n");
720 sdsdp[0] = 0x87788252;
721 /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
722 sdsdp[1] = 0x0957a030;
723 sdsdp[2] = 0x40082350;
724 sdsdp[3] = 0x0d050000;
725 } else if (!strcmp(argv[1], "667")) {
726 printf("Bootstrapping for 667MHz\n");
727 sdsdp[0] = 0x8778a256;
728 /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
729 sdsdp[1] = 0x0947a030;
730 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
731 * -> not working when overclocking 533MHz chips
732 * -> untested on 667MHz chips */
733 /* sdsdp[1]=0x095fa030; */
734 sdsdp[2] = 0x40082350;
735 sdsdp[3] = 0x0d050000;
738 printf("Bootstrapping for 533MHz (default)\n");
739 sdsdp[0] = 0x87788252;
740 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
741 sdsdp[1] = 0x095fa030;
742 sdsdp[2] = 0x40082350;
743 sdsdp[3] = 0x0d050000;
746 printf("Writing boot EEPROM ...\n");
747 if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
748 0, (uchar*)sdsdp, 16) != 0)
749 printf("boot_eeprom_write failed\n");
751 printf("done (dump via 'i2c md 52 0.1 10')\n");
756 sbe, 2, 0, do_setup_boot_eeprom,
757 "sbe - setup boot eeprom\n",
761 #if defined(CFG_EEPROM_WREN)
763 * Input: <dev_addr> I2C address of EEPROM device to enable.
764 * <state> -1: deliver current state
767 * Returns: -1: wrong device address
768 * 0: dis-/en- able done
769 * 0/1: current state if <state> was -1.
771 int eeprom_write_enable (unsigned dev_addr, int state)
773 if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
774 (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
779 /* Enable write access, clear bit GPIO_SINT2. */
780 out_be32((void*)GPIO0_OR,
781 in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
785 /* Disable write access, set bit GPIO_SINT2. */
786 out_be32((void*)GPIO0_OR,
787 in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
791 /* Read current status back. */
792 state = (0 == (in_be32((void*)GPIO0_OR) &
800 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
802 int query = argc == 1;
806 /* Query write access state. */
807 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
809 puts ("Query of write access state failed.\n");
811 printf ("Write access for device 0x%0x is %sabled.\n",
812 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
816 if ('0' == argv[1][0]) {
817 /* Disable write access. */
818 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
820 /* Enable write access. */
821 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
824 puts ("Setup of write access state failed.\n");
830 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
831 "eepwren - Enable / disable / query EEPROM write access\n",
833 #endif /* #if defined(CFG_EEPROM_WREN) */
835 static int got_pldirq;
837 static int pld_interrupt(u32 arg)
839 int rc = -1; /* not for us */
840 u8 status = in8(CFG_CPLD_BASE);
842 /* check for PLD interrupt */
843 if (status & PWR_INT_FLAG) {
845 out8(CFG_CPLD_BASE, 0);
847 got_pldirq = 1; /* trigger backend */
853 int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
857 /* clear any pending interrupt */
858 out8(CFG_CPLD_BASE, 0);
860 irq_install_handler(CPLD_IRQ,
861 (interrupt_handler_t *)pld_interrupt, 0);
863 printf("Waiting ...\n");
865 /* Abort if ctrl-c was pressed */
872 printf("Got interrupt!\n");
873 printf("Power %sready!\n",
874 in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
877 irq_free_handler(CPLD_IRQ);
881 wpi, 1, 1, do_waitpwrirq,
882 "wpi - Wait for power change interrupt\n",
887 * initialize DVI panellink transmitter
894 uchar u[] = {0x08, 0x34,
902 oldbus = I2C_GET_BUS();
905 for (i = 0; i < sizeof(u); i += 2)
906 if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
912 printf("initialized\n");
914 printf("failed - cannot initialize DVI transmitter\n");
920 int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
926 dviinit, 1, 1, do_dviinit,
927 "dviinit - Initialize DVI Panellink transmitter\n",
932 * TODO: 'time' command might be useful for others as well.
933 * Move to 'common' directory.
935 int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
937 unsigned long long start, end;
938 char c, cmd[CFG_CBSIZE];
943 for (i = 1; i < argc; i++) {
949 while ((c = *p++) != '\0') {
956 ret = run_command (cmd, 0);
959 printf("ticks=%d\n", (ulong)(end - start));
960 us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
961 printf("usec=%d\n", us);
966 time, CFG_MAXARGS, 1, do_time,
967 "time - run command and output execution time\n",
971 extern void video_hw_rectfill (
972 unsigned int bpp, /* bytes per pixel */
973 unsigned int dst_x, /* dest pos x */
974 unsigned int dst_y, /* dest pos y */
975 unsigned int dim_x, /* frame width */
976 unsigned int dim_y, /* frame height */
977 unsigned int color /* fill color */
982 * draw rectangles using pseudorandom number generator
983 * (see http://www.embedded.com/columns/technicalinsights/20900500)
985 unsigned int rprime = 9972;
986 static unsigned int r;
987 static unsigned int Y;
989 unsigned int prng(unsigned int max)
991 if (r == 0 || r == 1 || r == -1)
992 r = rprime; /* keep from getting stuck */
994 r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
995 Y = (r >> 16) % max; /* choose upper bits and reduce */
999 int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
1002 unsigned int x, y, dx, dy;
1007 dx = prng(1280- x - 1);
1008 dy = prng(1024 - y - 1);
1009 color = prng(0x10000);
1010 video_hw_rectfill(2, x, y, dx, dy, color);
1016 gfxdemo, CFG_MAXARGS, 1, do_gfxdemo,