2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
37 #ifdef CONFIG_VIDEO_SM501
39 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
40 (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
42 #ifdef CONFIG_VIDEO_SM501_8BPP
43 #error CONFIG_VIDEO_SM501_8BPP not supported.
44 #endif /* CONFIG_VIDEO_SM501_8BPP */
46 #ifdef CONFIG_VIDEO_SM501_16BPP
50 * 800x600 display B084SN03: PCLK = 40MHz
55 static const SMI_REGS init_regs_800x600 [] =
58 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
60 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
62 {0x00004, SWAP32(0x00000000)},
63 /* clocks for pm1... */
64 {0x00048, SWAP32(0x00021807)},
65 {0x0004C, SWAP32(0x221a0a01)},
66 {0x00054, SWAP32(0x00000001)},
67 /* clocks for pm0... */
68 {0x00040, SWAP32(0x00021807)},
69 {0x00044, SWAP32(0x221a0a01)},
70 {0x00054, SWAP32(0x00000000)},
72 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
73 /* panel control regs... */
74 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
75 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
76 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
77 {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
78 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
79 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
80 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
81 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
82 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
83 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
84 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
85 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
86 {0x80200, SWAP32(0x00010000)}, /* crt display control */
91 * 1024x768 display G150XG02: PCLK = 65MHz
96 static const SMI_REGS init_regs_1024x768 [] =
98 {0x00004, SWAP32(0x00000000)},
99 /* clocks for pm1... */
100 {0x00048, SWAP32(0x00021807)},
101 {0x0004C, SWAP32(0x011a0a01)},
102 {0x00054, SWAP32(0x00000001)},
103 /* clocks for pm0... */
104 {0x00040, SWAP32(0x00021807)},
105 {0x00044, SWAP32(0x011a0a01)},
106 {0x00054, SWAP32(0x00000000)},
108 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
109 /* panel control regs... */
110 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
111 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
112 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
113 {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
114 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
115 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
116 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
117 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
118 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
119 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
120 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
121 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
122 {0x80200, SWAP32(0x00010000)}, /* crt display control */
126 #endif /* CONFIG_VIDEO_SM501_16BPP */
128 #ifdef CONFIG_VIDEO_SM501_32BPP
132 * 800x600 display B084SN03: PCLK = 40MHz
137 static const SMI_REGS init_regs_800x600 [] =
139 #if 0 /* test-only */
140 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
142 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
144 {0x00004, SWAP32(0x00000000)},
145 /* clocks for pm1... */
146 {0x00048, SWAP32(0x00021807)},
147 {0x0004C, SWAP32(0x221a0a01)},
148 {0x00054, SWAP32(0x00000001)},
149 /* clocks for pm0... */
150 {0x00040, SWAP32(0x00021807)},
151 {0x00044, SWAP32(0x221a0a01)},
152 {0x00054, SWAP32(0x00000000)},
154 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
155 /* panel control regs... */
156 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
157 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
158 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
159 {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
160 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
161 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
162 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
163 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
164 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
165 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
166 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
167 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
168 {0x80200, SWAP32(0x00010000)}, /* crt display control */
173 * 1024x768 display G150XG02: PCLK = 65MHz
178 static const SMI_REGS init_regs_1024x768 [] =
180 {0x00004, SWAP32(0x00000000)},
181 /* clocks for pm1... */
182 {0x00048, SWAP32(0x00021807)},
183 {0x0004C, SWAP32(0x011a0a01)},
184 {0x00054, SWAP32(0x00000001)},
185 /* clocks for pm0... */
186 {0x00040, SWAP32(0x00021807)},
187 {0x00044, SWAP32(0x011a0a01)},
188 {0x00054, SWAP32(0x00000000)},
190 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
191 /* panel control regs... */
192 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
193 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
194 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
195 {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
196 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
197 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
198 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
199 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
200 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
201 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
202 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
203 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
204 {0x80200, SWAP32(0x00010000)}, /* crt display control */
208 #endif /* CONFIG_VIDEO_SM501_32BPP */
210 #endif /* CONFIG_VIDEO_SM501 */
216 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
217 extern void lxt971_no_sleep(void);
219 /* fpga configuration data - gzip compressed and generated by bin2c */
220 const unsigned char fpgadata[] =
222 #include "fpgadata.c"
226 * include common fpga code (for esd boards)
228 #include "../common/fpga.c"
232 int gunzip(void *, int, unsigned char *, unsigned long *);
235 /* logo bitmap data - gzip compressed and generated by bin2c */
236 unsigned char logo_bmp_320[] =
238 #include "logo_320_240_4bpp.c"
241 unsigned char logo_bmp_320_8bpp[] =
243 #include "logo_320_240_8bpp.c"
246 unsigned char logo_bmp_640[] =
248 #include "logo_640_480_24bpp.c"
251 unsigned char logo_bmp_1024[] =
253 #include "logo_1024_768_8bpp.c"
258 * include common lcd code (for esd boards)
260 #include "../common/lcd.c"
262 #include "../common/s1d13704_320_240_4bpp.h"
263 #include "../common/s1d13705_320_240_8bpp.h"
264 #include "../common/s1d13806_640_480_16bpp.h"
265 #include "../common/s1d13806_1024_768_8bpp.h"
269 * include common auto-update code (for esd boards)
271 #include "../common/auto_update.h"
273 au_image_t au_image[] = {
274 {"hh405/preinst.img", 0, -1, AU_SCRIPT},
275 {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
276 {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
277 {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
278 {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
279 {"hh405/postinst.img", 0, 0, AU_SCRIPT},
282 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
286 * Get version of HH405 board from GPIO's
288 int board_revision(void)
290 unsigned long osrh_reg;
291 unsigned long isr1h_reg;
292 unsigned long tcr_reg;
296 * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
298 osrh_reg = in32(GPIO0_OSRH);
299 isr1h_reg = in32(GPIO0_ISR1H);
300 tcr_reg = in32(GPIO0_TCR);
301 out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
302 out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
303 out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
305 udelay(1000); /* wait some time before reading input */
306 value = in32(GPIO0_IR) & 0x80400000; /* get config bits */
309 * Restore GPIO settings
311 out32(GPIO0_OSRH, osrh_reg); /* output select */
312 out32(GPIO0_ISR1H, isr1h_reg); /* input select */
313 out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
315 if (value & 0x80000000) {
316 /* Revision 1.0 or 1.1 detected */
319 if (value & 0x00400000) {
329 int board_early_init_f (void)
332 * IRQ 0-15 405GP internally generated; active high; level sensitive
333 * IRQ 16 405GP internally generated; active low; level sensitive
335 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
336 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
337 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
338 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
339 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
340 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
341 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
343 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
344 mtdcr(uicer, 0x00000000); /* disable all ints */
345 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
346 mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
347 mtdcr(uictr, 0x10000000); /* set int trigger levels */
348 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
349 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
352 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
354 mtebc (epcr, 0xa8400000); /* ebc always driven */
361 DECLARE_GLOBAL_DATA_PTR;
365 volatile unsigned short *fpga_ctrl =
366 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
367 volatile unsigned short *fpga_status =
368 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
370 if (gd->board_type >= 2) {
371 if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
372 if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
373 *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
375 for (i=0; i<300; i++)
378 *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
384 *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
385 *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
392 int misc_init_r (void)
394 DECLARE_GLOBAL_DATA_PTR;
396 volatile unsigned short *fpga_ctrl =
397 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
398 volatile unsigned short *lcd_contrast =
399 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
400 volatile unsigned short *lcd_backlight =
401 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
403 ulong len = sizeof(fpgadata);
408 unsigned long contrast0 = 0xffffffff;
410 dst = malloc(CFG_FPGA_MAX_SIZE);
411 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
412 printf ("GUNZIP ERROR - must RESET board to recover\n");
413 do_reset (NULL, 0, 0, NULL);
416 status = fpga_boot(dst, len);
418 printf("\nFPGA: Booting failed ");
420 case ERROR_FPGA_PRG_INIT_LOW:
421 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
423 case ERROR_FPGA_PRG_INIT_HIGH:
424 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
426 case ERROR_FPGA_PRG_DONE:
427 printf("(Timeout: DONE not high after programming FPGA)\n ");
431 /* display infos on fpgaimage */
433 for (i=0; i<4; i++) {
435 printf("FPGA: %s\n", &(dst[index+1]));
440 for (i=20; i>0; i--) {
441 printf("Rebooting in %2d seconds \r",i);
442 for (index=0;index<1000;index++)
446 do_reset(NULL, 0, 0, NULL);
451 /* display infos on fpgaimage */
453 for (i=0; i<4; i++) {
455 printf("%s ", &(dst[index+1]));
463 * Reset FPGA via FPGA_INIT pin
465 out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
466 out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
467 udelay(1000); /* wait 1ms */
468 out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
469 udelay(1000); /* wait 1ms */
472 * Write Board revision into FPGA
474 *fpga_ctrl |= gd->board_type & 0x0003;
477 * Setup and enable EEPROM write protection
479 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
482 * Set NAND-FLASH GPIO signals to default
484 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
485 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
488 * Reset touch-screen controller
490 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
492 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
495 * Enable power on PS/2 interface (with reset)
497 *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
500 *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
503 * Get contrast value from environment variable
505 str = getenv("contrast0");
507 contrast0 = simple_strtol(str, NULL, 16);
508 if (contrast0 > 255) {
509 printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
510 contrast0 = 0xffffffff;
515 * Init lcd interface and display logo
518 str = getenv("bd_type");
519 if (strcmp(str, "ppc230") == 0) {
521 * Switch backlight on
523 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
524 *lcd_backlight = 0x0000;
527 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
528 regs_13806_1024_768_8bpp,
529 sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
530 logo_bmp_1024, sizeof(logo_bmp_1024));
531 } else if (strcmp(str, "ppc220") == 0) {
533 * Switch backlight on
535 *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
536 *lcd_backlight = 0x0000;
539 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
540 regs_13806_640_480_16bpp,
541 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
542 logo_bmp_640, sizeof(logo_bmp_640));
543 } else if (strcmp(str, "ppc215") == 0) {
545 * Set default display contrast voltage
547 if (contrast0 == 0xffffffff) {
548 *lcd_contrast = 0x0082;
550 *lcd_contrast = contrast0;
552 *lcd_backlight = 0xffff;
554 * Switch backlight on
556 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
558 * Set lcd clock (small epson)
560 *fpga_ctrl |= LCD_CLK_06250;
561 udelay(100); /* wait for 100 us */
564 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
565 regs_13705_320_240_8bpp,
566 sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
567 logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
568 } else if (strcmp(str, "ppc210") == 0) {
570 * Set default display contrast voltage
572 if (contrast0 == 0xffffffff) {
573 *lcd_contrast = 0x0060;
575 *lcd_contrast = contrast0;
577 *lcd_backlight = 0xffff;
579 * Switch backlight on
581 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
583 * Set lcd clock (small epson), enable 1-wire interface
585 *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
588 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
589 regs_13704_320_240_4bpp,
590 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
591 logo_bmp_320, sizeof(logo_bmp_320));
592 #ifdef CONFIG_VIDEO_SM501
597 * Is SM501 connected (ppc221/ppc231)?
599 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
600 if (devbusfn != -1) {
601 puts("VGA: SM501 with 8 MB ");
602 if (strcmp(str, "ppc221") == 0) {
603 printf("(800*600, %dbpp)\n", BPP);
604 *lcd_backlight = 0x002d; /* max. allowed brightness */
605 } else if (strcmp(str, "ppc231") == 0) {
606 printf("(1024*768, %dbpp)\n", BPP);
607 *lcd_backlight = 0x0000;
609 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
613 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
616 #endif /* CONFIG_VIDEO_SM501 */
626 * Check Board Identity:
629 int checkboard (void)
631 DECLARE_GLOBAL_DATA_PTR;
634 int i = getenv_r ("serial#", str, sizeof(str));
639 puts ("### No HW ID - assuming HH405");
644 if (getenv_r("bd_type", str, sizeof(str)) != -1) {
647 puts(" (Missing bd_type!");
650 gd->board_type = board_revision();
651 printf(", Rev %ld.x)\n", gd->board_type);
657 long int initdram (int board_type)
661 mtdcr(memcfga, mem_mb0cf);
662 val = mfdcr(memcfgd);
665 printf("\nmb0cf=%x\n", val); /* test-only */
666 printf("strap=%x\n", mfdcr(strap)); /* test-only */
669 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
673 #ifdef CONFIG_IDE_RESET
674 void ide_set_reset(int on)
676 DECLARE_GLOBAL_DATA_PTR;
678 volatile unsigned short *fpga_mode =
679 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
680 volatile unsigned short *fpga_status =
681 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
683 if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
684 (gd->board_type < 2)) {
686 * Assert or deassert CompactFlash Reset Pin
688 if (on) { /* assert RESET */
690 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
691 } else { /* release RESET */
692 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
696 #endif /* CONFIG_IDE_RESET */
699 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
700 #include <linux/mtd/nand.h>
701 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
705 nand_probe(CFG_NAND_BASE);
706 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
707 print_size(nand_dev_desc[0].totlen, "\n");
713 #if defined(CFG_EEPROM_WREN)
714 /* Input: <dev_addr> I2C address of EEPROM device to enable.
715 * <state> -1: deliver current state
718 * Returns: -1: wrong device address
719 * 0: dis-/en- able done
720 * 0/1: current state if <state> was -1.
722 int eeprom_write_enable (unsigned dev_addr, int state)
724 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
729 /* Enable write access, clear bit GPIO_SINT2. */
730 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
734 /* Disable write access, set bit GPIO_SINT2. */
735 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
739 /* Read current status back. */
740 state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
747 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
749 int query = argc == 1;
753 /* Query write access state. */
754 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
756 puts ("Query of write access state failed.\n");
758 printf ("Write access for device 0x%0x is %sabled.\n",
759 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
763 if ('0' == argv[1][0]) {
764 /* Disable write access. */
765 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
767 /* Enable write access. */
768 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
771 puts ("Setup of write access state failed.\n");
778 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
779 "eepwren - Enable / disable / query EEPROM write access\n",
781 #endif /* #if defined(CFG_EEPROM_WREN) */
784 #ifdef CONFIG_VIDEO_SM501
785 #ifdef CONFIG_CONSOLE_EXTRA_INFO
787 * Return text to be printed besides the logo.
789 void video_get_info_str (int line_number, char *info)
791 DECLARE_GLOBAL_DATA_PTR;
795 int i = getenv_r("serial#", str2, sizeof(str));
797 if (line_number == 1) {
798 sprintf(str, " Board: ");
801 strcat(str, "### No HW ID - assuming HH405");
806 if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
810 strcat(str, " (Missing bd_type!");
813 sprintf(str2, ", Rev %ld.x)", gd->board_type);
820 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
823 * Returns SM501 register base address. First thing called in the driver.
825 unsigned int board_video_init (void)
831 * Is SM501 connected (ppc221/ppc231)?
833 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
834 if (devbusfn != -1) {
835 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
836 return (addr & 0xfffffffe);
843 * Returns SM501 framebuffer address
845 unsigned int board_video_get_fb (void)
851 * Is SM501 connected (ppc221/ppc231)?
853 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
854 if (devbusfn != -1) {
855 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
857 #ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
858 addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
867 * Called after initializing the SM501 and before clearing the screen.
869 void board_validate_screen (unsigned int base)
874 * Return a pointer to the initialization sequence.
876 const SMI_REGS *board_get_regs (void)
880 str = getenv("bd_type");
881 if (strcmp(str, "ppc221") == 0) {
882 return init_regs_800x600;
884 return init_regs_1024x768;
888 int board_get_width (void)
892 str = getenv("bd_type");
893 if (strcmp(str, "ppc221") == 0) {
900 int board_get_height (void)
904 str = getenv("bd_type");
905 if (strcmp(str, "ppc221") == 0) {
912 #endif /* CONFIG_VIDEO_SM501 */
917 #ifdef CONFIG_LXT971_NO_SLEEP
920 * Disable sleep mode in LXT971