2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 extern void lxt971_no_sleep(void);
33 int board_revision(void)
35 unsigned long osrl_reg;
36 unsigned long isr1l_reg;
37 unsigned long tcr_reg;
41 * Get version of HUB405 board from GPIO's
45 * Setup GPIO pin(s) (IRQ6/GPIO23)
47 osrl_reg = in32(GPIO0_OSRH);
48 isr1l_reg = in32(GPIO0_ISR1H);
49 tcr_reg = in32(GPIO0_TCR);
50 out32(GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */
51 out32(GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */
52 out32(GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */
54 udelay(1000); /* wait some time before reading input */
55 value = in32(GPIO0_IR) & 0x00000100; /* get config bits */
58 * Restore GPIO settings
60 out32(GPIO0_OSRH, osrl_reg); /* output select */
61 out32(GPIO0_ISR1H, isr1l_reg); /* input select */
62 out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
64 if (value & 0x00000100) {
65 /* Revision 1.1 or 1.2 detected */
74 int board_early_init_f (void)
77 * IRQ 0-15 405GP internally generated; active high; level sensitive
78 * IRQ 16 405GP internally generated; active low; level sensitive
80 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
81 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
82 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
83 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
84 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
85 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
86 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
88 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
89 mtdcr(uicer, 0x00000000); /* disable all ints */
90 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
91 mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
92 mtdcr(uictr, 0x10000000); /* set int trigger levels */
93 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
94 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
97 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
99 mtebc (epcr, 0xa8400000); /* ebc always driven */
105 int misc_init_f (void)
107 return 0; /* dummy implementation */
111 int misc_init_r (void)
113 DECLARE_GLOBAL_DATA_PTR;
115 volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
116 volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
117 volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
118 volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
119 volatile unsigned char *led_reg = (unsigned char *)((ulong)DUART0_BA + 0x20);
126 * Enable interrupts in exar duart mcr[3]
134 * Set RS232/RS422 control (RS232 = high on GPIO)
136 val = in32(GPIO0_OR);
137 val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232);
139 str = getenv("phys0");
140 if (!str || (str && (str[0] == '0')))
141 val |= CFG_UART2_RS232;
143 str = getenv("phys1");
144 if (!str || (str && (str[0] == '0')))
145 val |= CFG_UART3_RS232;
147 str = getenv("phys2");
148 if (!str || (str && (str[0] == '0')))
149 val |= CFG_UART4_RS232;
151 str = getenv("phys3");
152 if (!str || (str && (str[0] == '0')))
153 val |= CFG_UART5_RS232;
155 out32(GPIO0_OR, val);
158 * Set NAND-FLASH GPIO signals to default
160 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
161 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
164 * check board type and setup AP power
166 str = getenv("bd_type"); /* this is only set on non prototype hardware */
168 if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
169 unsigned char led_reg_default = 0;
170 str = getenv("ap_pwr");
171 if (!str || (str && (str[0] == '1')))
172 led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
177 for (flashcnt = 0; flashcnt < 3; flashcnt++) {
178 *led_reg = led_reg_default; /* LED_A..D off */
179 for (delay = 0; delay < 100; delay++)
181 *led_reg = led_reg_default | 0xf0; /* LED_A..D on */
182 for (delay = 0; delay < 50; delay++)
185 *led_reg = led_reg_default;
190 * Reset external DUARTs
192 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
193 udelay(10); /* wait 10us */
194 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
195 udelay(1000); /* wait 1ms */
198 * Store hardware revision in environment for further processing
200 sprintf(hw_rev, "1.%ld", gd->board_type);
201 setenv("hw_rev", hw_rev);
207 * Check Board Identity:
209 int checkboard (void)
211 DECLARE_GLOBAL_DATA_PTR;
214 int i = getenv_r ("serial#", str, sizeof(str));
219 puts ("### No HW ID - assuming HUB405");
224 if (getenv_r("bd_type", str, sizeof(str)) != -1) {
227 puts(" (Missing bd_type!");
230 gd->board_type = board_revision();
231 printf(", Rev 1.%ld)\n", gd->board_type);
234 * Disable sleep mode in LXT971
242 long int initdram (int board_type)
246 mtdcr(memcfga, mem_mb0cf);
247 val = mfdcr(memcfgd);
250 printf("\nmb0cf=%x\n", val); /* test-only */
251 printf("strap=%x\n", mfdcr(strap)); /* test-only */
254 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
260 /* TODO: XXX XXX XXX */
261 printf ("test: 16 MB - ok\n");
267 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
268 #include <linux/mtd/nand_legacy.h>
269 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
273 nand_probe(CFG_NAND_BASE);
274 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
275 print_size(nand_dev_desc[0].totlen, "\n");