2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2009-2011
7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
8 * esd electronic system design gmbh <www.esd.eu>
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_pmc.h>
19 #include <asm/arch/at91_rstc.h>
20 #include <asm/arch/at91_matrix.h>
21 #include <asm/arch/at91_pio.h>
22 #include <asm/arch/clk.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 * Miscelaneous platform dependent initialisations
31 static int hw_rev = -1; /* hardware revision */
38 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
39 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
40 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
41 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
49 #ifdef CONFIG_CMD_NAND
50 static void meesc_nand_hw_init(void)
53 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
54 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
57 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
58 writel(csa, &matrix->csa[0]);
60 /* Configure SMC CS3 for NAND/SmartMedia */
61 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
62 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
65 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
66 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
69 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
71 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
72 AT91_SMC_MODE_EXNW_DISABLE |
74 AT91_SMC_MODE_TDF_CYCLE(12),
77 /* Configure RDY/BSY */
78 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
80 /* Enable NandFlash */
81 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
83 #endif /* CONFIG_CMD_NAND */
86 static void meesc_macb_hw_init(void)
88 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
90 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
96 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
97 * controller debugging
98 * The ET1100 is located at physical address 0x70000000
99 * Its process memory is located at physical address 0x70001000
101 static void meesc_ethercat_hw_init(void)
103 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
105 /* Configure SMC EBI1_CS0 for EtherCAT */
106 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
107 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
109 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
110 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
112 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
115 * Configure behavior at external wait signal, byte-select mode, 16 bit
116 * data bus width, none data float wait states and TDF optimization
118 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
119 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
120 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
122 /* Configure RDY/BSY */
123 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
128 gd->ram_size = get_ram_size(
129 (void *)CONFIG_SYS_SDRAM_BASE,
130 CONFIG_SYS_SDRAM_SIZE);
134 int board_eth_init(bd_t *bis)
138 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
146 u_char hw_type; /* hardware type */
148 /* read the "Type" register of the ET1100 controller */
149 hw_type = readb(CONFIG_ET1100_BASE);
154 /* ET1100 present, arch number of MEESC-Board */
155 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
156 puts("Board: CAN-EtherCAT Gateway");
159 /* no ET1100 present, arch number of EtherCAN/2-Board */
160 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
161 puts("Board: EtherCAN/2 Gateway");
162 /* switch on LED1D */
163 at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
166 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
167 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
168 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
169 puts("Board: EtherCAN/2 Gateway");
172 if (getenv_f("serial#", str, sizeof(str)) > 0) {
176 printf("\nHardware-revision: 1.%d\n", get_hw_rev());
177 printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
181 #ifdef CONFIG_SERIAL_TAG
182 void get_board_serial(struct tag_serialnr *serialnr)
186 char *serial = getenv("serial#");
188 str = strchr(serial, '_');
189 if (str && (strlen(str) >= 4)) {
190 serialnr->high = (*(str + 1) << 8) | *(str + 2);
191 serialnr->low = simple_strtoul(str + 3, NULL, 16);
200 #ifdef CONFIG_REVISION_TAG
201 u32 get_board_rev(void)
203 return hw_rev | 0x100;
207 #ifdef CONFIG_MISC_INIT_R
208 int misc_init_r(void)
212 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
215 * Normally the processor clock has a divisor of 2.
216 * In some cases this this needs to be set to 4.
217 * Check the user has set environment mdiv to 4 to change the divisor.
219 if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
220 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
221 AT91SAM9_PMC_MDIV_4, &pmc->mckr);
222 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
224 /* Notify the user that the clock is not default */
225 printf("Setting master clock to %s MHz\n",
226 strmhz(buf, get_mck_clk_rate()));
231 #endif /* CONFIG_MISC_INIT_R */
233 int board_early_init_f(void)
235 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
237 /* enable all clocks */
238 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
239 (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
242 at91_seriald_hw_init();
249 /* initialize ET1100 Controller */
250 meesc_ethercat_hw_init();
252 /* adress of boot parameters */
253 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
255 #ifdef CONFIG_CMD_NAND
256 meesc_nand_hw_init();
258 #ifdef CONFIG_HAS_DATAFLASH
259 at91_spi0_hw_init(1 << 0);
262 meesc_macb_hw_init();
264 #ifdef CONFIG_AT91_CAN
267 #ifdef CONFIG_USB_OHCI_NEW