3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
31 /* ------------------------------------------------------------------------- */
33 int board_pre_init (void)
36 * IRQ 0-15 405GP internally generated; active high; level sensitive
37 * IRQ 16 405GP internally generated; active low; level sensitive
39 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
40 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
41 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
42 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
43 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
44 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
45 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
47 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
48 mtdcr (uicer, 0x00000000); /* disable all ints */
49 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
50 mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
51 mtdcr (uictr, 0x10000000); /* set int trigger levels */
52 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
53 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
56 * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
57 * transfers, set device-paced timeout to 256 cycles
59 mtebc (epcr, 0x20400000);
65 /* ------------------------------------------------------------------------- */
67 int misc_init_f (void)
69 return 0; /* dummy implementation */
74 * Check Board Identity:
79 unsigned char str[64];
80 int i = getenv_r ("serial#", str, sizeof (str));
86 puts ("### No HW ID - assuming OCRTC");
89 puts ("### No HW ID - assuming ORSG");
100 /* ------------------------------------------------------------------------- */
102 long int initdram (int board_type)
106 mtdcr (memcfga, mem_mb0cf);
107 val = mfdcr (memcfgd);
110 printf ("\nmb0cf=%x\n", val); /* test-only */
111 printf ("strap=%x\n", mfdcr (strap)); /* test-only */
114 return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17));
117 /* ------------------------------------------------------------------------- */
121 /* TODO: XXX XXX XXX */
122 printf ("test: 16 MB - ok\n");
127 /* ------------------------------------------------------------------------- */