3 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
4 * esd electronic system design gmbh <www.esd.eu>
6 * (C) Copyright 2007-2008
7 * Stelian Pop <stelian.pop@leadtechdesign.com>
8 * Lead Tech Design <www.leadtechdesign.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/at91sam9263.h>
31 #include <asm/arch/at91sam9_smc.h>
32 #include <asm/arch/at91_common.h>
33 #include <asm/arch/at91_pmc.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/at91_matrix.h>
36 #include <asm/arch/at91_pio.h>
37 #include <asm/arch/clk.h>
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/io.h>
40 #include <atmel_lcdc.h>
43 #ifdef CONFIG_LCD_INFO
48 DECLARE_GLOBAL_DATA_PTR;
51 * Miscelaneous platform dependent initialisations
54 static int hw_rev = -1; /* hardware revision */
61 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
62 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
63 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
64 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
72 #ifdef CONFIG_CMD_NAND
73 static void otc570_nand_hw_init(void)
76 at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
77 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
80 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
81 writel(csa, &matrix->csa[0]);
83 /* Configure SMC CS3 for NAND/SmartMedia */
84 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
85 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
88 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
89 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
92 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
94 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
95 AT91_SMC_MODE_EXNW_DISABLE |
97 AT91_SMC_MODE_TDF_CYCLE(2),
100 /* Configure RDY/BSY */
101 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
103 /* Enable NandFlash */
104 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
106 #endif /* CONFIG_CMD_NAND */
109 static void otc570_macb_hw_init(void)
111 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
113 writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
119 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
120 * controller debugging
121 * The ET1100 is located at physical address 0x70000000
122 * Its process memory is located at physical address 0x70001000
124 static void otc570_ethercat_hw_init(void)
126 at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE;
128 /* Configure SMC EBI1_CS0 for EtherCAT */
129 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
130 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
132 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
133 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
135 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
138 * Configure behavior at external wait signal, byte-select mode, 16 bit
139 * data bus width, none data float wait states and TDF optimization
141 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
142 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
143 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
145 /* Configure RDY/BSY */
146 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
150 /* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
151 vidinfo_t panel_info = {
155 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
156 ATMEL_LCDC_INVFRAME_INVERTED,
158 .vl_bpix = 3, /* Bits per pixel, 0 = 1bit, 3 = 8bit */
159 .vl_tft = 1, /* 0 = passive, 1 = TFT */
160 .vl_vsync_len = 1, /* Length of vertical sync in NOL */
161 .vl_upper_margin = 35, /* Idle lines at the frame start */
162 .vl_lower_margin = 5, /* Idle lines at the end of the frame */
163 .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
164 .vl_left_margin = 112, /* Idle cycles at the line beginning */
165 .vl_right_margin = 1, /* Idle cycles at the end of the line */
167 .mmio = AT91SAM9263_LCDC_BASE,
170 void lcd_enable(void)
172 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
175 void lcd_disable(void)
177 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
180 static void otc570_lcd_hw_init(void)
182 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
184 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
185 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
186 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
187 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
188 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
189 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
190 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
191 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
192 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
193 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
194 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
195 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
196 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
197 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
198 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
199 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
200 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
201 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
202 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
203 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
204 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
205 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
206 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
207 at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
209 writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
210 gd->fb_base = CONFIG_OTC570_LCD_BASE;
213 #ifdef CONFIG_LCD_INFO
214 void lcd_show_board_info(void)
216 ulong dram_size, nand_size;
221 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
222 dram_size += gd->bd->bi_dram[i].size;
224 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
225 nand_size += nand_info[i].size;
227 lcd_printf("\n%s\n", U_BOOT_VERSION);
228 lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME,
229 strmhz(temp, get_cpu_clk_rate()));
230 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
233 lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
234 lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
235 lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
237 #endif /* CONFIG_LCD_INFO */
238 #endif /* CONFIG_LCD */
242 gd->bd->bi_dram[0].start = PHYS_SDRAM;
243 gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
247 int board_eth_init(bd_t *bis)
251 rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
260 puts("Board: esd ARM9 HMI Panel - OTC570");
261 if (getenv_f("serial#", str, sizeof(str)) > 0) {
265 printf("\nHardware-revision: 1.%d\n", get_hw_rev());
266 printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
270 #ifdef CONFIG_SERIAL_TAG
271 void get_board_serial(struct tag_serialnr *serialnr)
275 char *serial = getenv("serial#");
277 str = strchr(serial, '_');
278 if (str && (strlen(str) >= 4)) {
279 serialnr->high = (*(str + 1) << 8) | *(str + 2);
280 serialnr->low = simple_strtoul(str + 3, NULL, 16);
289 #ifdef CONFIG_REVISION_TAG
290 u32 get_board_rev(void)
292 return hw_rev | 0x100;
296 #ifdef CONFIG_MISC_INIT_R
297 int misc_init_r(void)
300 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
302 at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
303 at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
304 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
305 writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
306 /* Set USART_MODE = 1 (RS485) */
307 writel(1, 0xFFF8C004);
311 if (getenv_f("usart0", str, sizeof(str)) == -1) {
312 printf("No entry - assuming 1-wire\n");
313 /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
314 at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
316 if (strcmp(str, "1-wire") == 0) {
318 at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
319 } else if (strcmp(str, "rs485") == 0) {
321 at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
323 printf("Wrong entry - assuming 1-wire ");
324 printf("(valid values are '1-wire' or 'rs485')\n");
325 at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
328 printf("Display memory address: 0x%08lX\n", gd->fb_base);
332 #endif /* CONFIG_MISC_INIT_R */
336 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
338 /* Peripheral Clock Enable Register */
339 writel( 1 << AT91SAM9263_ID_PIOA |
340 1 << AT91SAM9263_ID_PIOB |
341 1 << AT91SAM9263_ID_PIOCDE |
342 1 << AT91SAM9263_ID_TWI |
343 1 << AT91SAM9263_ID_SPI0 |
344 1 << AT91SAM9263_ID_LCDC |
345 1 << AT91SAM9263_ID_UHP,
348 /* arch number of OTC570-Board */
349 gd->bd->bi_arch_number = MACH_TYPE_OTC570;
351 /* adress of boot parameters */
352 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
354 at91_serial_hw_init();
355 #ifdef CONFIG_CMD_NAND
356 otc570_nand_hw_init();
358 otc570_ethercat_hw_init();
359 #ifdef CONFIG_HAS_DATAFLASH
360 at91_spi0_hw_init(1 << 0);
363 otc570_macb_hw_init();
365 #ifdef CONFIG_AT91_CAN
368 #ifdef CONFIG_USB_OHCI_NEW
372 otc570_lcd_hw_init();