2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
13 #include <asm/4xx_pci.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 unsigned long fpga_done_state(void);
22 unsigned long fpga_init_state(void);
28 /* predefine these here */
29 #define FPGA_DONE_STATE (fpga_done_state())
30 #define FPGA_INIT_STATE (fpga_init_state())
32 /* fpga configuration data - generated by bin2cc */
33 const unsigned char fpgadata[] =
39 * include common fpga code (for esd boards)
41 #include "../common/fpga.c"
43 #define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
44 #define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
46 #define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
47 #define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
50 int board_revision(void)
52 unsigned long CPC0_CR0Reg;
56 * Get version of PCI405 board from GPIO's
60 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
62 CPC0_CR0Reg = mfdcr(CPC0_CR0);
63 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
64 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
65 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
66 udelay(1000); /* wait some time before reading input */
67 value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
70 * Restore GPIO settings
72 mtdcr(CPC0_CR0, CPC0_CR0Reg);
76 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
79 /* CS2==0 && IRQ5==1 -> version 1.2 */
82 /* CS2==0 && IRQ5==0 -> version 1.3 */
84 #if 0 /* not yet manufactured ! */
86 /* CS2==1 && IRQ5==0 -> version 1.4 */
90 /* should not be reached! */
96 unsigned long fpga_done_state(void)
98 if (gd->board_type < 2) {
99 return FPGA_DONE_STATE_V11;
101 return FPGA_DONE_STATE_V12;
106 unsigned long fpga_init_state(void)
108 if (gd->board_type < 2) {
109 return FPGA_INIT_STATE_V11;
111 return FPGA_INIT_STATE_V12;
116 int board_early_init_f (void)
118 unsigned long CPC0_CR0Reg;
121 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
123 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
124 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
125 out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
126 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
129 * IRQ 0-15 405GP internally generated; active high; level sensitive
130 * IRQ 16 405GP internally generated; active low; level sensitive
132 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
133 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
134 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
135 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
136 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
137 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
138 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
140 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
141 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
142 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
143 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
144 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
145 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
146 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
149 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
151 CPC0_CR0Reg = mfdcr(CPC0_CR0);
152 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
155 * Setup GPIO pins (CS6+CS7 as GPIO)
157 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
160 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
162 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
167 int misc_init_r (void)
170 ulong len = sizeof(fpgadata);
178 * On PCI-405 the environment is saved in eeprom!
179 * FPGA can be gzip compressed (malloc) and booted this late.
182 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
183 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
184 printf ("GUNZIP ERROR - must RESET board to recover\n");
185 do_reset (NULL, 0, 0, NULL);
188 status = fpga_boot(dst, len);
190 printf("\nFPGA: Booting failed ");
192 case ERROR_FPGA_PRG_INIT_LOW:
193 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
195 case ERROR_FPGA_PRG_INIT_HIGH:
196 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
198 case ERROR_FPGA_PRG_DONE:
199 printf("(Timeout: DONE not high after programming FPGA)\n ");
203 /* display infos on fpgaimage */
205 for (i=0; i<4; i++) {
207 printf("FPGA: %s\n", &(dst[index+1]));
212 for (i=20; i>0; i--) {
213 printf("Rebooting in %2d seconds \r",i);
214 for (index=0;index<1000;index++)
218 do_reset(NULL, 0, 0, NULL);
223 /* display infos on fpgaimage */
225 for (i=0; i<4; i++) {
227 printf("%s ", &(dst[index+1]));
233 * Reset FPGA via FPGA_DATA pin
235 SET_FPGA(FPGA_PRG | FPGA_CLK);
236 udelay(1000); /* wait 1ms */
237 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
238 udelay(1000); /* wait 1ms */
241 * Check if magic for pci reconfig is written
243 magic = (unsigned int *)0x00000004;
244 if (*magic == PCI_RECONFIG_MAGIC) {
246 * Rewrite pci config regs (only after soft-reset with magic set)
248 ptr = (unsigned int *)PCI_REGS_ADDR;
249 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
250 puts("Restoring PCI Configurations Regs!\n");
251 ptr = (unsigned int *)PCI_REGS_ADDR + 1;
252 for (i=0; i<0x40; i+=4) {
253 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
256 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
258 *magic = 0; /* clear pci reconfig magic again */
262 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
264 #define PCI0_BRDGOPT1 0x4a
265 pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
268 * Enable fairness and high bus utilization
270 mtdcr(PLB0_ACR, 0x98000000);
278 * Check Board Identity:
280 int checkboard (void)
283 int i = getenv_f("serial#", str, sizeof(str));
288 puts ("### No HW ID - assuming PCI405");
293 gd->board_type = board_revision();
294 printf(" (Rev 1.%ld", gd->board_type);
296 if (gd->board_type >= 2) {
297 unsigned long CPC0_CR0Reg;
301 * Setup GPIO pins (Trace/GPIO1 to GPIO)
303 CPC0_CR0Reg = mfdcr(CPC0_CR0);
304 mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
305 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
306 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
307 udelay(1000); /* wait some time before reading input */
308 value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
310 puts(", 33 MHz PCI");
312 puts(", 66 MHz PCI");
321 /* ------------------------------------------------------------------------- */
322 #define UART1_MCR 0xef600404
328 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
329 } else if (wp == 0) {
330 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
332 if (in_8((void *)UART1_MCR) & 0x02) {
341 int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
345 if (argv[1][0] == '1') {
347 } else if (argv[1][0] == '0') {
353 printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
358 wpeeprom, 2, 1, do_wpeeprom,
359 "Check/Enable/Disable I2C EEPROM write protection",
361 " - check I2C EEPROM write protection state\n"
363 " - enable I2C EEPROM write protection\n"
365 " - disable I2C EEPROM write protection"