2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 #include <asm/4xx_pci.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 int gunzip(void *, int, unsigned char *, unsigned long *);
38 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
39 unsigned long fpga_done_state(void);
40 unsigned long fpga_init_state(void);
46 /* predefine these here */
47 #define FPGA_DONE_STATE (fpga_done_state())
48 #define FPGA_INIT_STATE (fpga_init_state())
50 /* fpga configuration data - generated by bin2cc */
51 const unsigned char fpgadata[] =
57 * include common fpga code (for esd boards)
59 #include "../common/fpga.c"
61 #define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
62 #define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
64 #define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
65 #define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
68 int board_revision(void)
70 unsigned long cntrl0Reg;
74 * Get version of PCI405 board from GPIO's
78 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
80 cntrl0Reg = mfdcr(cntrl0);
81 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
82 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
83 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
84 udelay(1000); /* wait some time before reading input */
85 value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
88 * Restore GPIO settings
90 mtdcr(cntrl0, cntrl0Reg);
94 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
97 /* CS2==0 && IRQ5==1 -> version 1.2 */
100 /* CS2==0 && IRQ5==0 -> version 1.3 */
102 #if 0 /* not yet manufactured ! */
104 /* CS2==1 && IRQ5==0 -> version 1.4 */
108 /* should not be reached! */
114 unsigned long fpga_done_state(void)
116 if (gd->board_type < 2) {
117 return FPGA_DONE_STATE_V11;
119 return FPGA_DONE_STATE_V12;
124 unsigned long fpga_init_state(void)
126 if (gd->board_type < 2) {
127 return FPGA_INIT_STATE_V11;
129 return FPGA_INIT_STATE_V12;
134 int board_early_init_f (void)
136 unsigned long cntrl0Reg;
139 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
141 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
142 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
143 out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
144 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
147 * IRQ 0-15 405GP internally generated; active high; level sensitive
148 * IRQ 16 405GP internally generated; active low; level sensitive
150 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
151 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
152 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
153 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
154 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
155 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
156 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
158 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
159 mtdcr(uicer, 0x00000000); /* disable all ints */
160 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
161 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
162 mtdcr(uictr, 0x10000000); /* set int trigger levels */
163 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
164 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
167 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
169 cntrl0Reg = mfdcr(cntrl0);
170 mtdcr(cntrl0, cntrl0Reg | 0x00008000);
173 * Setup GPIO pins (CS6+CS7 as GPIO)
175 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
178 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
180 mtebc (epcr, 0xa8400000); /* ebc always driven */
185 int misc_init_r (void)
188 ulong len = sizeof(fpgadata);
196 * On PCI-405 the environment is saved in eeprom!
197 * FPGA can be gzip compressed (malloc) and booted this late.
200 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
201 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
202 printf ("GUNZIP ERROR - must RESET board to recover\n");
203 do_reset (NULL, 0, 0, NULL);
206 status = fpga_boot(dst, len);
208 printf("\nFPGA: Booting failed ");
210 case ERROR_FPGA_PRG_INIT_LOW:
211 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
213 case ERROR_FPGA_PRG_INIT_HIGH:
214 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
216 case ERROR_FPGA_PRG_DONE:
217 printf("(Timeout: DONE not high after programming FPGA)\n ");
221 /* display infos on fpgaimage */
223 for (i=0; i<4; i++) {
225 printf("FPGA: %s\n", &(dst[index+1]));
230 for (i=20; i>0; i--) {
231 printf("Rebooting in %2d seconds \r",i);
232 for (index=0;index<1000;index++)
236 do_reset(NULL, 0, 0, NULL);
241 /* display infos on fpgaimage */
243 for (i=0; i<4; i++) {
245 printf("%s ", &(dst[index+1]));
251 * Reset FPGA via FPGA_DATA pin
253 SET_FPGA(FPGA_PRG | FPGA_CLK);
254 udelay(1000); /* wait 1ms */
255 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
256 udelay(1000); /* wait 1ms */
259 * Check if magic for pci reconfig is written
261 magic = (unsigned int *)0x00000004;
262 if (*magic == PCI_RECONFIG_MAGIC) {
264 * Rewrite pci config regs (only after soft-reset with magic set)
266 ptr = (unsigned int *)PCI_REGS_ADDR;
267 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
268 puts("Restoring PCI Configurations Regs!\n");
269 ptr = (unsigned int *)PCI_REGS_ADDR + 1;
270 for (i=0; i<0x40; i+=4) {
271 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
274 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
276 *magic = 0; /* clear pci reconfig magic again */
280 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
282 #define PCI0_BRDGOPT1 0x4a
283 pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
285 #define plb0_acr 0x87
287 * Enable fairness and high bus utilization
289 mtdcr(plb0_acr, 0x98000000);
297 * Check Board Identity:
299 int checkboard (void)
302 int i = getenv_r ("serial#", str, sizeof(str));
307 puts ("### No HW ID - assuming PCI405");
312 gd->board_type = board_revision();
313 printf(" (Rev 1.%ld", gd->board_type);
315 if (gd->board_type >= 2) {
316 unsigned long cntrl0Reg;
320 * Setup GPIO pins (Trace/GPIO1 to GPIO)
322 cntrl0Reg = mfdcr(cntrl0);
323 mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
324 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
325 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
326 udelay(1000); /* wait some time before reading input */
327 value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
329 puts(", 33 MHz PCI");
331 puts(", 66 MHz PCI");
340 /* ------------------------------------------------------------------------- */
341 #define UART1_MCR 0xef600404
347 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
348 } else if (wp == 0) {
349 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
351 if (in_8((void *)UART1_MCR) & 0x02) {
360 int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
364 if (argv[1][0] == '1') {
366 } else if (argv[1][0] == '0') {
372 printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
377 wpeeprom, 2, 1, do_wpeeprom,
378 "Check/Enable/Disable I2C EEPROM write protection",
380 " - check I2C EEPROM write protection state\n"
382 " - enable I2C EEPROM write protection\n"
384 " - disable I2C EEPROM write protection\n"