2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 #include <asm/4xx_pci.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 unsigned long fpga_done_state(void);
38 unsigned long fpga_init_state(void);
44 /* predefine these here */
45 #define FPGA_DONE_STATE (fpga_done_state())
46 #define FPGA_INIT_STATE (fpga_init_state())
48 /* fpga configuration data - generated by bin2cc */
49 const unsigned char fpgadata[] =
55 * include common fpga code (for esd boards)
57 #include "../common/fpga.c"
59 #define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
60 #define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
62 #define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
63 #define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
66 int board_revision(void)
68 unsigned long CPC0_CR0Reg;
72 * Get version of PCI405 board from GPIO's
76 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
78 CPC0_CR0Reg = mfdcr(CPC0_CR0);
79 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
80 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
81 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
82 udelay(1000); /* wait some time before reading input */
83 value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
86 * Restore GPIO settings
88 mtdcr(CPC0_CR0, CPC0_CR0Reg);
92 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
95 /* CS2==0 && IRQ5==1 -> version 1.2 */
98 /* CS2==0 && IRQ5==0 -> version 1.3 */
100 #if 0 /* not yet manufactured ! */
102 /* CS2==1 && IRQ5==0 -> version 1.4 */
106 /* should not be reached! */
112 unsigned long fpga_done_state(void)
114 if (gd->board_type < 2) {
115 return FPGA_DONE_STATE_V11;
117 return FPGA_DONE_STATE_V12;
122 unsigned long fpga_init_state(void)
124 if (gd->board_type < 2) {
125 return FPGA_INIT_STATE_V11;
127 return FPGA_INIT_STATE_V12;
132 int board_early_init_f (void)
134 unsigned long CPC0_CR0Reg;
137 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
139 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
140 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
141 out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
142 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
145 * IRQ 0-15 405GP internally generated; active high; level sensitive
146 * IRQ 16 405GP internally generated; active low; level sensitive
148 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
149 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
150 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
151 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
152 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
153 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
154 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
156 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
157 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
158 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
159 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
160 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
161 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
162 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
165 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
167 CPC0_CR0Reg = mfdcr(CPC0_CR0);
168 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
171 * Setup GPIO pins (CS6+CS7 as GPIO)
173 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
176 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
178 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
183 int misc_init_r (void)
186 ulong len = sizeof(fpgadata);
194 * On PCI-405 the environment is saved in eeprom!
195 * FPGA can be gzip compressed (malloc) and booted this late.
198 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
199 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
200 printf ("GUNZIP ERROR - must RESET board to recover\n");
201 do_reset (NULL, 0, 0, NULL);
204 status = fpga_boot(dst, len);
206 printf("\nFPGA: Booting failed ");
208 case ERROR_FPGA_PRG_INIT_LOW:
209 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
211 case ERROR_FPGA_PRG_INIT_HIGH:
212 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
214 case ERROR_FPGA_PRG_DONE:
215 printf("(Timeout: DONE not high after programming FPGA)\n ");
219 /* display infos on fpgaimage */
221 for (i=0; i<4; i++) {
223 printf("FPGA: %s\n", &(dst[index+1]));
228 for (i=20; i>0; i--) {
229 printf("Rebooting in %2d seconds \r",i);
230 for (index=0;index<1000;index++)
234 do_reset(NULL, 0, 0, NULL);
239 /* display infos on fpgaimage */
241 for (i=0; i<4; i++) {
243 printf("%s ", &(dst[index+1]));
249 * Reset FPGA via FPGA_DATA pin
251 SET_FPGA(FPGA_PRG | FPGA_CLK);
252 udelay(1000); /* wait 1ms */
253 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
254 udelay(1000); /* wait 1ms */
257 * Check if magic for pci reconfig is written
259 magic = (unsigned int *)0x00000004;
260 if (*magic == PCI_RECONFIG_MAGIC) {
262 * Rewrite pci config regs (only after soft-reset with magic set)
264 ptr = (unsigned int *)PCI_REGS_ADDR;
265 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
266 puts("Restoring PCI Configurations Regs!\n");
267 ptr = (unsigned int *)PCI_REGS_ADDR + 1;
268 for (i=0; i<0x40; i+=4) {
269 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
272 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
274 *magic = 0; /* clear pci reconfig magic again */
278 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
280 #define PCI0_BRDGOPT1 0x4a
281 pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
284 * Enable fairness and high bus utilization
286 mtdcr(PLB0_ACR, 0x98000000);
294 * Check Board Identity:
296 int checkboard (void)
299 int i = getenv_f("serial#", str, sizeof(str));
304 puts ("### No HW ID - assuming PCI405");
309 gd->board_type = board_revision();
310 printf(" (Rev 1.%ld", gd->board_type);
312 if (gd->board_type >= 2) {
313 unsigned long CPC0_CR0Reg;
317 * Setup GPIO pins (Trace/GPIO1 to GPIO)
319 CPC0_CR0Reg = mfdcr(CPC0_CR0);
320 mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
321 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
322 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
323 udelay(1000); /* wait some time before reading input */
324 value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
326 puts(", 33 MHz PCI");
328 puts(", 66 MHz PCI");
337 /* ------------------------------------------------------------------------- */
338 #define UART1_MCR 0xef600404
344 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
345 } else if (wp == 0) {
346 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
348 if (in_8((void *)UART1_MCR) & 0x02) {
357 int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
361 if (argv[1][0] == '1') {
363 } else if (argv[1][0] == '0') {
369 printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
374 wpeeprom, 2, 1, do_wpeeprom,
375 "Check/Enable/Disable I2C EEPROM write protection",
377 " - check I2C EEPROM write protection state\n"
379 " - enable I2C EEPROM write protection\n"
381 " - disable I2C EEPROM write protection"