2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 #include <asm/4xx_pci.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 int gunzip(void *, int, unsigned char *, unsigned long *);
37 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
38 unsigned long fpga_done_state(void);
39 unsigned long fpga_init_state(void);
45 /* predefine these here */
46 #define FPGA_DONE_STATE (fpga_done_state())
47 #define FPGA_INIT_STATE (fpga_init_state())
49 /* fpga configuration data - generated by bin2cc */
50 const unsigned char fpgadata[] =
56 * include common fpga code (for esd boards)
58 #include "../common/fpga.c"
60 #define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
61 #define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
63 #define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
64 #define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
67 int board_revision(void)
69 unsigned long cntrl0Reg;
73 * Get version of PCI405 board from GPIO's
77 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
79 cntrl0Reg = mfdcr(cntrl0);
80 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
81 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
82 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
83 udelay(1000); /* wait some time before reading input */
84 value = in32(GPIO0_IR) & 0x00100200; /* get config bits */
87 * Restore GPIO settings
89 mtdcr(cntrl0, cntrl0Reg);
93 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
96 /* CS2==0 && IRQ5==1 -> version 1.2 */
99 /* CS2==0 && IRQ5==0 -> version 1.3 */
101 #if 0 /* not yet manufactured ! */
103 /* CS2==1 && IRQ5==0 -> version 1.4 */
107 /* should not be reached! */
113 unsigned long fpga_done_state(void)
115 if (gd->board_type < 2) {
116 return FPGA_DONE_STATE_V11;
118 return FPGA_DONE_STATE_V12;
123 unsigned long fpga_init_state(void)
125 if (gd->board_type < 2) {
126 return FPGA_INIT_STATE_V11;
128 return FPGA_INIT_STATE_V12;
133 int board_early_init_f (void)
135 unsigned long cntrl0Reg;
138 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
140 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
141 out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
142 out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
143 out32(GPIO0_OR, 0); /* pull prg low */
146 * IRQ 0-15 405GP internally generated; active high; level sensitive
147 * IRQ 16 405GP internally generated; active low; level sensitive
149 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
150 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
151 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
152 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
153 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
154 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
155 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
157 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
158 mtdcr(uicer, 0x00000000); /* disable all ints */
159 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
160 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
161 mtdcr(uictr, 0x10000000); /* set int trigger levels */
162 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
163 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
166 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
168 cntrl0Reg = mfdcr(cntrl0);
169 mtdcr(cntrl0, cntrl0Reg | 0x00008000);
172 * Setup GPIO pins (CS6+CS7 as GPIO)
174 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
177 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
179 mtebc (epcr, 0xa8400000); /* ebc always driven */
185 /* ------------------------------------------------------------------------- */
187 int misc_init_f (void)
189 return 0; /* dummy implementation */
193 int misc_init_r (void)
196 ulong len = sizeof(fpgadata);
204 * On PCI-405 the environment is saved in eeprom!
205 * FPGA can be gzip compressed (malloc) and booted this late.
208 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
209 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
210 printf ("GUNZIP ERROR - must RESET board to recover\n");
211 do_reset (NULL, 0, 0, NULL);
214 status = fpga_boot(dst, len);
216 printf("\nFPGA: Booting failed ");
218 case ERROR_FPGA_PRG_INIT_LOW:
219 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
221 case ERROR_FPGA_PRG_INIT_HIGH:
222 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
224 case ERROR_FPGA_PRG_DONE:
225 printf("(Timeout: DONE not high after programming FPGA)\n ");
229 /* display infos on fpgaimage */
231 for (i=0; i<4; i++) {
233 printf("FPGA: %s\n", &(dst[index+1]));
238 for (i=20; i>0; i--) {
239 printf("Rebooting in %2d seconds \r",i);
240 for (index=0;index<1000;index++)
244 do_reset(NULL, 0, 0, NULL);
249 /* display infos on fpgaimage */
251 for (i=0; i<4; i++) {
253 printf("%s ", &(dst[index+1]));
259 * Reset FPGA via FPGA_DATA pin
261 SET_FPGA(FPGA_PRG | FPGA_CLK);
262 udelay(1000); /* wait 1ms */
263 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
264 udelay(1000); /* wait 1ms */
267 * Check if magic for pci reconfig is written
269 magic = (unsigned int *)0x00000004;
270 if (*magic == PCI_RECONFIG_MAGIC) {
272 * Rewrite pci config regs (only after soft-reset with magic set)
274 ptr = (unsigned int *)PCI_REGS_ADDR;
275 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
276 puts("Restoring PCI Configurations Regs!\n");
277 ptr = (unsigned int *)PCI_REGS_ADDR + 1;
278 for (i=0; i<0x40; i+=4) {
279 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
282 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
284 *magic = 0; /* clear pci reconfig magic again */
287 #if 1 /* test-only */
289 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
291 #define PCI0_BRDGOPT1 0x4a
292 pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
293 /* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */
295 #define plb0_acr 0x87
297 * Enable fairness and high bus utilization
299 mtdcr(plb0_acr, 0x98000000);
301 #if 0 /* test-only */
302 printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
303 /* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */
304 mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
306 /* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
315 * Check Board Identity:
318 int checkboard (void)
321 int i = getenv_r ("serial#", str, sizeof(str));
326 puts ("### No HW ID - assuming PCI405");
331 gd->board_type = board_revision();
332 printf(" (Rev 1.%ld", gd->board_type);
334 if (gd->board_type >= 2) {
335 unsigned long cntrl0Reg;
339 * Setup GPIO pins (Trace/GPIO1 to GPIO)
341 cntrl0Reg = mfdcr(cntrl0);
342 mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
343 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
344 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
345 udelay(1000); /* wait some time before reading input */
346 value = in32(GPIO0_IR) & 0x40000000; /* get config bits */
348 puts(", 33 MHz PCI");
350 puts(", 66 Mhz PCI");
359 /* ------------------------------------------------------------------------- */
363 volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
367 } else if (wp == 0) {
370 if (*uart1_mcr & 0x02) {
379 int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
383 if (argv[1][0] == '1') {
385 } else if (argv[1][0] == '0') {
391 printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
396 wpeeprom, 2, 1, do_wpeeprom,
397 "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n",
399 " - check I2C EEPROM write protection state\n"
401 " - enable I2C EEPROM write protection\n"
403 " - disable I2C EEPROM write protection\n"