1 /*------------------------------------------------------------------------------+ */
3 /* This source code is dual-licensed. You may use it under the terms */
4 /* of the GNU General Public License version 2, or under the license */
7 /* This source code has been made available to you by IBM on an AS-IS */
8 /* basis. Anyone receiving this source is licensed under IBM */
9 /* copyrights to use it in any way he or she deems fit, including */
10 /* copying it, modifying it, compiling it, and redistributing it either */
11 /* with or without modifications. No license under IBM patents or */
12 /* patent applications is to be implied by the copyright license. */
14 /* Any user of this software should understand that IBM cannot provide */
15 /* technical support for this software and will not be responsible for */
16 /* any consequences resulting from the use of this software. */
18 /* Any person who transfers this source code or any derivative work */
19 /* must include the IBM copyright notice, this paragraph, and the */
20 /* preceding two paragraphs in the transferred software. */
22 /* COPYRIGHT I B M CORPORATION 1995 */
23 /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
24 /*------------------------------------------------------------------------------- */
26 /*----------------------------------------------------------------------------- */
27 /* Function: ext_bus_cntlr_init */
28 /* Description: Initializes the External Bus Controller for the external */
29 /* peripherals. IMPORTANT: For pass1 this code must run from */
30 /* cache since you can not reliably change a peripheral banks */
31 /* timing register (pbxap) while running code from that bank. */
32 /* For ex., since we are running from ROM on bank 0, we can NOT */
33 /* execute the code that modifies bank 0 timings from ROM, so */
34 /* we run it from cache. */
35 /* Bank 0 - Flash and SRAM */
36 /* Bank 1 - NVRAM/RTC */
37 /* Bank 2 - Keyboard/Mouse controller */
38 /* Bank 3 - IR controller */
39 /* Bank 4 - not used */
40 /* Bank 5 - not used */
41 /* Bank 6 - not used */
42 /* Bank 7 - FPGA registers */
43 /*----------------------------------------------------------------------------- */
44 #include <asm/ppc4xx.h>
46 #include <ppc_asm.tmpl>
49 #include <asm/cache.h>
53 .globl write_without_sync
56 * Write one values to host via pci busmastering
57 * ptr = 0xc0000000 -> 0x01000000 (PCI)
70 * ptr = (volatile unsigned long *)addr;
77 * One pci config write
78 * ibmPciConfigWrite(0x2e, 2, 0x1234);
93 blr /* never reached !!!! */
95 .globl write_with_sync
98 * Write one values to host via pci busmastering
99 * ptr = 0xc0000000 -> 0x01000000 (PCI)
111 * Read one value back
112 * ptr = (volatile unsigned long *)addr;
119 * One pci config write
120 * ibmPciConfigWrite(0x2e, 2, 0x1234);
137 blr /* never reached !!!! */
139 .globl write_with_less_sync
140 write_with_less_sync:
142 * Write one values to host via pci busmastering
143 * ptr = 0xc0000000 -> 0x01000000 (PCI)
155 * Read one value back
156 * ptr = (volatile unsigned long *)addr;
163 * One pci config write
164 * ibmPciConfigWrite(0x2e, 2, 0x1234);
181 blr /* never reached !!!! */
183 .globl write_with_more_sync
184 write_with_more_sync:
186 * Write one values to host via pci busmastering
187 * ptr = 0xc0000000 -> 0x01000000 (PCI)
200 * Read one value back
201 * ptr = (volatile unsigned long *)addr;
209 * One pci config write
210 * ibmPciConfigWrite(0x2e, 2, 0x1234);
212 /* subsystem id (PCIC0_SBSYSVID)*/
227 blr /* never reached !!!! */