git.sur5r.net Git - u-boot/blob - board/esd/pci405/writeibm.S

   1 /*------------------------------------------------------------------------------+ */
   2 /* */
   3 /*       This source code has been made available to you by IBM on an AS-IS */
   4 /*       basis.  Anyone receiving this source is licensed under IBM */
   5 /*       copyrights to use it in any way he or she deems fit, including */
   6 /*       copying it, modifying it, compiling it, and redistributing it either */
   7 /*       with or without modifications.  No license under IBM patents or */
   8 /*       patent applications is to be implied by the copyright license. */
   9 /* */
  10 /*       Any user of this software should understand that IBM cannot provide */
  11 /*       technical support for this software and will not be responsible for */
  12 /*       any consequences resulting from the use of this software. */
  13 /* */
  14 /*       Any person who transfers this source code or any derivative work */
  15 /*       must include the IBM copyright notice, this paragraph, and the */
  16 /*       preceding two paragraphs in the transferred software. */
  17 /* */
  18 /*       COPYRIGHT   I B M   CORPORATION 1995 */
  19 /*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
  20 /*------------------------------------------------------------------------------- */
  21
  22 /*----------------------------------------------------------------------------- */
  23 /* Function:     ext_bus_cntlr_init */
  24 /* Description:  Initializes the External Bus Controller for the external */
  25 /*              peripherals. IMPORTANT: For pass1 this code must run from */
  26 /*              cache since you can not reliably change a peripheral banks */
  27 /*              timing register (pbxap) while running code from that bank. */
  28 /*              For ex., since we are running from ROM on bank 0, we can NOT */
  29 /*              execute the code that modifies bank 0 timings from ROM, so */
  30 /*              we run it from cache. */
  31 /*      Bank 0 - Flash and SRAM */
  32 /*      Bank 1 - NVRAM/RTC */
  33 /*      Bank 2 - Keyboard/Mouse controller */
  34 /*      Bank 3 - IR controller */
  35 /*      Bank 4 - not used */
  36 /*      Bank 5 - not used */
  37 /*      Bank 6 - not used */
  38 /*      Bank 7 - FPGA registers */
  39 /*----------------------------------------------------------------------------- */
  40 #include <ppc4xx.h>
  41
  42 #include <ppc_asm.tmpl>
  43 #include <ppc_defs.h>
  44
  45 #include <asm/cache.h>
  46 #include <asm/mmu.h>
  47
  48
  49         .globl  write_without_sync
  50 write_without_sync:
  51                 /*
  52                  * Write one values to host via pci busmastering
  53                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
  54                  * *ptr = 0x01234567;
  55                  */
  56         addi    r31,0,0
  57         lis     r31,0xc000
  58
  59 start1:
  60         lis     r0,0x0123
  61         ori     r0,r0,0x4567
  62         stw     r0,0(r31)
  63
  64                 /*
  65                  * Read one value back
  66                  * ptr = (volatile unsigned long *)addr;
  67                  * val = *ptr;
  68                  */
  69
  70         lwz     r0,0(r31)
  71
  72                 /*
  73                  * One pci config write
  74                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
  75                  */
  76                 /* subsystem id */
  77
  78
  79
  80         li      r4,0x002C
  81         oris    r4,r4,0x8000
  82         lis     r3,0xEEC0
  83         stwbrx  r4,0,r3
  84
  85         li      r5,0x1234
  86         ori     r3,r3,0x4
  87         stwbrx  r5,0,r3
  88
  89         b       start1
  90
  91         blr     /* never reached !!!! */
  92
  93
  94
  95         .globl  write_with_sync
  96 write_with_sync:
  97                 /*
  98                  * Write one values to host via pci busmastering
  99                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
 100                  * *ptr = 0x01234567;
 101                  */
 102         addi    r31,0,0
 103         lis     r31,0xc000
 104
 105 start2:
 106         lis     r0,0x0123
 107         ori     r0,r0,0x4567
 108         stw     r0,0(r31)
 109
 110                 /*
 111                  * Read one value back
 112                  * ptr = (volatile unsigned long *)addr;
 113                  * val = *ptr;
 114                  */
 115
 116         lwz     r0,0(r31)
 117
 118                 /*
 119                  * One pci config write
 120                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
 121                  */
 122                 /* subsystem id */
 123
 124
 125
 126         li      r4,0x002C
 127         oris    r4,r4,0x8000
 128         lis     r3,0xEEC0
 129         stwbrx  r4,0,r3
 130         sync
 131
 132         li      r5,0x1234
 133         ori     r3,r3,0x4
 134         stwbrx  r5,0,r3
 135         sync
 136
 137         b       start2
 138
 139         blr     /* never reached !!!! */
 140
 141
 142         .globl  write_with_less_sync
 143 write_with_less_sync:
 144                 /*
 145                  * Write one values to host via pci busmastering
 146                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
 147                  * *ptr = 0x01234567;
 148                  */
 149         addi    r31,0,0
 150         lis     r31,0xc000
 151
 152 start2b:
 153         lis     r0,0x0123
 154         ori     r0,r0,0x4567
 155         stw     r0,0(r31)
 156
 157                 /*
 158                  * Read one value back
 159                  * ptr = (volatile unsigned long *)addr;
 160                  * val = *ptr;
 161                  */
 162
 163         lwz     r0,0(r31)
 164
 165                 /*
 166                  * One pci config write
 167                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
 168                  */
 169                 /* subsystem id */
 170
 171
 172
 173         li      r4,0x002C
 174         oris    r4,r4,0x8000
 175         lis     r3,0xEEC0
 176         stwbrx  r4,0,r3
 177         sync
 178
 179         li      r5,0x1234
 180         ori     r3,r3,0x4
 181         stwbrx  r5,0,r3
 182 /*        sync */
 183
 184         b       start2b
 185
 186         blr     /* never reached !!!! */
 187
 188
 189         .globl  write_with_more_sync
 190 write_with_more_sync:
 191                 /*
 192                  * Write one values to host via pci busmastering
 193                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
 194                  * *ptr = 0x01234567;
 195                  */
 196         addi    r31,0,0
 197         lis     r31,0xc000
 198
 199 start3:
 200         lis     r0,0x0123
 201         ori     r0,r0,0x4567
 202         stw     r0,0(r31)
 203         sync
 204
 205                 /*
 206                  * Read one value back
 207                  * ptr = (volatile unsigned long *)addr;
 208                  * val = *ptr;
 209                  */
 210
 211         lwz     r0,0(r31)
 212         sync
 213
 214                 /*
 215                  * One pci config write
 216                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
 217                  */
 218                 /* subsystem id (PCIC0_SBSYSVID)*/
 219
 220
 221
 222         li      r4,0x002C
 223         oris    r4,r4,0x8000
 224         lis     r3,0xEEC0
 225         stwbrx  r4,0,r3
 226         sync
 227
 228         li      r5,0x1234
 229         ori     r3,r3,0x4
 230         stwbrx  r5,0,r3
 231         sync
 232
 233         b       start3
 234
 235         blr     /* never reached !!!! */