2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 extern void lxt971_no_sleep(void);
37 /* fpga configuration data - gzip compressed and generated by bin2c */
38 const unsigned char fpgadata[] =
44 * include common fpga code (for esd boards)
46 #include "../common/fpga.c"
49 * generate a short spike on the CAN tx line
50 * to bring the couplers in sync
52 void init_coupler(u32 addr)
54 struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
57 out_8(&ctrl->cr, CR_RR);
60 out_8(&ctrl->btr0, 0x00); /* btr setup is required */
61 out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
62 out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
63 OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
64 out_8(&ctrl->cr, 0x00);
73 out_8(&ctrl->cr, CR_RR);
76 int board_early_init_f(void)
79 * IRQ 0-15 405GP internally generated; active high; level sensitive
80 * IRQ 16 405GP internally generated; active low; level sensitive
82 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
83 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
84 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
85 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
86 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
87 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
88 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
90 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
91 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
92 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
93 mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
94 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
95 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
96 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
99 * EBC Configuration Register: set ready timeout to
100 * 512 ebc-clks -> ca. 15 us
102 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
107 int misc_init_r(void)
111 ulong len = sizeof(fpgadata);
116 /* adjust flash start and offset */
117 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
118 gd->bd->bi_flashoffset = 0;
120 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
121 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
122 (uchar *)fpgadata, &len) != 0) {
123 printf("GUNZIP ERROR - must RESET board to recover\n");
124 do_reset(NULL, 0, 0, NULL);
127 status = fpga_boot(dst, len);
129 printf("\nFPGA: Booting failed ");
131 case ERROR_FPGA_PRG_INIT_LOW:
132 printf("(Timeout: INIT not low "
133 "after asserting PROGRAM*)\n");
135 case ERROR_FPGA_PRG_INIT_HIGH:
136 printf("(Timeout: INIT not high "
137 "after deasserting PROGRAM*)\n");
139 case ERROR_FPGA_PRG_DONE:
140 printf("(Timeout: DONE not high "
141 "after programming FPGA)\n");
145 /* display infos on fpgaimage */
147 for (i=0; i<4; i++) {
149 printf("FPGA: %s\n", &(dst[index+1]));
154 for (i=20; i>0; i--) {
155 printf("Rebooting in %2d seconds \r",i);
156 for (index=0;index<1000;index++)
160 do_reset(NULL, 0, 0, NULL);
165 /* display infos on fpgaimage */
167 for (i=0; i<4; i++) {
169 printf("%s ", &(dst[index+1]));
177 * Reset FPGA via FPGA_DATA pin
179 SET_FPGA(FPGA_PRG | FPGA_CLK);
180 udelay(1000); /* wait 1ms */
181 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
182 udelay(1000); /* wait 1ms */
185 * Reset external DUARTs
187 out_be32((void*)GPIO0_OR,
188 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
190 out_be32((void*)GPIO0_OR,
191 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
195 * Set NAND-FLASH GPIO signals to default
197 out_be32((void*)GPIO0_OR,
198 in_be32((void*)GPIO0_OR) &
199 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
200 out_be32((void*)GPIO0_OR,
201 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
204 * Setup EEPROM write protection
206 out_be32((void*)GPIO0_OR,
207 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
208 out_be32((void*)GPIO0_TCR,
209 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
212 * Enable interrupts in exar duart mcr[3]
214 out_8((void *)DUART0_BA + 4, 0x08);
215 out_8((void *)DUART1_BA + 4, 0x08);
218 * Enable auto RS485 mode in 2nd external uart
220 out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
221 fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
222 fctr |= 0x08; /* enable RS485 mode */
223 out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
224 out_8((void *)DUART1_BA + 3, 0); /* write LCR */
227 * Init magnetic couplers
229 if (!getenv("noinitcoupler")) {
230 init_coupler(CAN0_BA);
231 init_coupler(CAN1_BA);
237 * Check Board Identity:
242 int i = getenv_f("serial#", str, sizeof(str));
247 puts("### No HW ID - assuming PLU405");
255 #ifdef CONFIG_IDE_RESET
256 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
257 void ide_set_reset(int on)
260 * Assert or deassert CompactFlash Reset Pin
262 if (on) { /* assert RESET */
263 out_be16((void *)FPGA_CTRL,
264 in_be16((void *)FPGA_CTRL) &
265 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
266 } else { /* release RESET */
267 out_be16((void *)FPGA_CTRL,
268 in_be16((void *)FPGA_CTRL) |
269 CONFIG_SYS_FPGA_CTRL_CF_RESET);
272 #endif /* CONFIG_IDE_RESET */
276 #ifdef CONFIG_LXT971_NO_SLEEP
279 * Disable sleep mode in LXT971
285 #if defined(CONFIG_SYS_EEPROM_WREN)
286 /* Input: <dev_addr> I2C address of EEPROM device to enable.
287 * <state> -1: deliver current state
290 * Returns: -1: wrong device address
291 * 0: dis-/en- able done
292 * 0/1: current state if <state> was -1.
294 int eeprom_write_enable(unsigned dev_addr, int state)
296 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
301 /* Enable write access, clear bit GPIO0. */
302 out_be32((void*)GPIO0_OR,
303 in_be32((void*)GPIO0_OR) &
304 ~CONFIG_SYS_EEPROM_WP);
308 /* Disable write access, set bit GPIO0. */
309 out_be32((void*)GPIO0_OR,
310 in_be32((void*)GPIO0_OR) |
311 CONFIG_SYS_EEPROM_WP);
315 /* Read current status back. */
316 state = ((in_be32((void*)GPIO0_OR) &
317 CONFIG_SYS_EEPROM_WP) == 0);
324 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
326 int query = argc == 1;
330 /* Query write access state. */
331 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
333 puts("Query of write access state failed.\n");
335 printf("Write access for device 0x%0x is %sabled.\n",
336 CONFIG_SYS_I2C_EEPROM_ADDR,
337 state ? "en" : "dis");
341 if (argv[1][0] == '0') {
342 /* Disable write access. */
343 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
346 /* Enable write access. */
347 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
351 puts("Setup of write access state failed.\n");
357 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
358 "Enable / disable / query EEPROM write access",
361 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */