2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
36 extern void lxt971_no_sleep(void);
38 /* fpga configuration data - gzip compressed and generated by bin2c */
39 const unsigned char fpgadata[] =
45 * include common fpga code (for esd boards)
47 #include "../common/fpga.c"
50 int gunzip(void *, int, unsigned char *, unsigned long *);
52 int board_early_init_f(void)
55 * IRQ 0-15 405GP internally generated; active high; level sensitive
56 * IRQ 16 405GP internally generated; active low; level sensitive
58 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
59 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
60 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
61 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
62 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
63 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
64 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
66 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
67 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
68 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
69 mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
70 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
71 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
72 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
75 * EBC Configuration Register: set ready timeout to
76 * 512 ebc-clks -> ca. 15 us
78 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
87 ulong len = sizeof(fpgadata);
92 /* adjust flash start and offset */
93 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
94 gd->bd->bi_flashoffset = 0;
96 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
97 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
98 (uchar *)fpgadata, &len) != 0) {
99 printf("GUNZIP ERROR - must RESET board to recover\n");
100 do_reset(NULL, 0, 0, NULL);
103 status = fpga_boot(dst, len);
105 printf("\nFPGA: Booting failed ");
107 case ERROR_FPGA_PRG_INIT_LOW:
108 printf("(Timeout: INIT not low "
109 "after asserting PROGRAM*)\n");
111 case ERROR_FPGA_PRG_INIT_HIGH:
112 printf("(Timeout: INIT not high "
113 "after deasserting PROGRAM*)\n");
115 case ERROR_FPGA_PRG_DONE:
116 printf("(Timeout: DONE not high "
117 "after programming FPGA)\n");
121 /* display infos on fpgaimage */
123 for (i=0; i<4; i++) {
125 printf("FPGA: %s\n", &(dst[index+1]));
130 for (i=20; i>0; i--) {
131 printf("Rebooting in %2d seconds \r",i);
132 for (index=0;index<1000;index++)
136 do_reset(NULL, 0, 0, NULL);
141 /* display infos on fpgaimage */
143 for (i=0; i<4; i++) {
145 printf("%s ", &(dst[index+1]));
153 * Reset FPGA via FPGA_DATA pin
155 SET_FPGA(FPGA_PRG | FPGA_CLK);
156 udelay(1000); /* wait 1ms */
157 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
158 udelay(1000); /* wait 1ms */
161 * Reset external DUARTs
163 out_be32((void*)GPIO0_OR,
164 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
166 out_be32((void*)GPIO0_OR,
167 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
171 * Set NAND-FLASH GPIO signals to default
173 out_be32((void*)GPIO0_OR,
174 in_be32((void*)GPIO0_OR) &
175 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
176 out_be32((void*)GPIO0_OR,
177 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
180 * Setup EEPROM write protection
182 out_be32((void*)GPIO0_OR,
183 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
184 out_be32((void*)GPIO0_TCR,
185 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
188 * Enable interrupts in exar duart mcr[3]
190 out_8((void *)DUART0_BA + 4, 0x08);
191 out_8((void *)DUART1_BA + 4, 0x08);
194 * Enable auto RS485 mode in 2nd external uart
196 out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
197 fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
198 fctr |= 0x08; /* enable RS485 mode */
199 out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
200 out_8((void *)DUART1_BA + 3, 0); /* write LCR */
203 * Init magnetic couplers
205 if (!getenv("noinitcoupler")) {
206 init_coupler(CAN0_BA);
207 init_coupler(CAN1_BA);
213 * Check Board Identity:
218 int i = getenv_r("serial#", str, sizeof(str));
223 puts("### No HW ID - assuming PLU405");
231 #ifdef CONFIG_IDE_RESET
232 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
233 void ide_set_reset(int on)
236 * Assert or deassert CompactFlash Reset Pin
238 if (on) { /* assert RESET */
239 out_be16((void *)FPGA_CTRL,
240 in_be16((void *)FPGA_CTRL) &
241 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
242 } else { /* release RESET */
243 out_be16((void *)FPGA_CTRL,
244 in_be16((void *)FPGA_CTRL) |
245 CONFIG_SYS_FPGA_CTRL_CF_RESET);
248 #endif /* CONFIG_IDE_RESET */
252 #ifdef CONFIG_LXT971_NO_SLEEP
255 * Disable sleep mode in LXT971
261 #if defined(CONFIG_SYS_EEPROM_WREN)
262 /* Input: <dev_addr> I2C address of EEPROM device to enable.
263 * <state> -1: deliver current state
266 * Returns: -1: wrong device address
267 * 0: dis-/en- able done
268 * 0/1: current state if <state> was -1.
270 int eeprom_write_enable(unsigned dev_addr, int state)
272 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
277 /* Enable write access, clear bit GPIO0. */
278 out_be32((void*)GPIO0_OR,
279 in_be32((void*)GPIO0_OR) &
280 ~CONFIG_SYS_EEPROM_WP);
284 /* Disable write access, set bit GPIO0. */
285 out_be32((void*)GPIO0_OR,
286 in_be32((void*)GPIO0_OR) |
287 CONFIG_SYS_EEPROM_WP);
291 /* Read current status back. */
292 state = ((in_be32((void*)GPIO0_OR) &
293 CONFIG_SYS_EEPROM_WP) == 0);
300 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
302 int query = argc == 1;
306 /* Query write access state. */
307 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
309 puts("Query of write access state failed.\n");
311 printf("Write access for device 0x%0x is %sabled.\n",
312 CONFIG_SYS_I2C_EEPROM_ADDR,
313 state ? "en" : "dis");
317 if (argv[1][0] == '0') {
318 /* Disable write access. */
319 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
322 /* Enable write access. */
323 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
327 puts("Setup of write access state failed.\n");
333 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
334 "Enable / disable / query EEPROM write access",
337 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */