git.sur5r.net Git - u-boot/blob - board/esd/plu405/plu405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29
  30 #undef FPGA_DEBUG
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  35 extern void lxt971_no_sleep(void);
  36
  37 /* fpga configuration data - gzip compressed and generated by bin2c */
  38 const unsigned char fpgadata[] =
  39 {
  40 #include "fpgadata.c"
  41 };
  42
  43 /*
  44  * include common fpga code (for esd boards)
  45  */
  46 #include "../common/fpga.c"
  47
  48 /* Prototypes */
  49 int gunzip(void *, int, unsigned char *, unsigned long *);
  50
  51 int board_early_init_f(void)
  52 {
  53         /*
  54          * IRQ 0-15  405GP internally generated; active high; level sensitive
  55          * IRQ 16    405GP internally generated; active low; level sensitive
  56          * IRQ 17-24 RESERVED
  57          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  58          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  59          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  60          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  61          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  62          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  63          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  64          */
  65         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  66         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  67         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  68         mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
  69         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  70         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
  71         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  72
  73         /*
  74          * EBC Configuration Register: set ready timeout to
  75          * 512 ebc-clks -> ca. 15 us
  76          */
  77         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
  78
  79         return 0;
  80 }
  81
  82 int misc_init_r(void)
  83 {
  84         unsigned char *dst;
  85         unsigned char fctr;
  86         ulong len = sizeof(fpgadata);
  87         int status;
  88         int index;
  89         int i;
  90
  91         /* adjust flash start and offset */
  92         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  93         gd->bd->bi_flashoffset = 0;
  94
  95         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
  96         if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
  97                    (uchar *)fpgadata, &len) != 0) {
  98                 printf("GUNZIP ERROR - must RESET board to recover\n");
  99                 do_reset(NULL, 0, 0, NULL);
 100         }
 101
 102         status = fpga_boot(dst, len);
 103         if (status != 0) {
 104                 printf("\nFPGA: Booting failed ");
 105                 switch (status) {
 106                 case ERROR_FPGA_PRG_INIT_LOW:
 107                         printf("(Timeout: INIT not low "
 108                                "after asserting PROGRAM*)\n");
 109                         break;
 110                 case ERROR_FPGA_PRG_INIT_HIGH:
 111                         printf("(Timeout: INIT not high "
 112                                "after deasserting PROGRAM*)\n");
 113                         break;
 114                 case ERROR_FPGA_PRG_DONE:
 115                         printf("(Timeout: DONE not high "
 116                                "after programming FPGA)\n");
 117                         break;
 118                 }
 119
 120                 /* display infos on fpgaimage */
 121                 index = 15;
 122                 for (i=0; i<4; i++) {
 123                         len = dst[index];
 124                         printf("FPGA: %s\n", &(dst[index+1]));
 125                         index += len+3;
 126                 }
 127                 putc ('\n');
 128                 /* delayed reboot */
 129                 for (i=20; i>0; i--) {
 130                         printf("Rebooting in %2d seconds \r",i);
 131                         for (index=0;index<1000;index++)
 132                                 udelay(1000);
 133                 }
 134                 putc('\n');
 135                 do_reset(NULL, 0, 0, NULL);
 136         }
 137
 138         puts("FPGA:  ");
 139
 140         /* display infos on fpgaimage */
 141         index = 15;
 142         for (i=0; i<4; i++) {
 143                 len = dst[index];
 144                 printf("%s ", &(dst[index+1]));
 145                 index += len+3;
 146         }
 147         putc('\n');
 148
 149         free(dst);
 150
 151         /*
 152          * Reset FPGA via FPGA_DATA pin
 153          */
 154         SET_FPGA(FPGA_PRG | FPGA_CLK);
 155         udelay(1000); /* wait 1ms */
 156         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 157         udelay(1000); /* wait 1ms */
 158
 159         /*
 160          * Reset external DUARTs
 161          */
 162         out_be32((void*)GPIO0_OR,
 163                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
 164         udelay(10);
 165         out_be32((void*)GPIO0_OR,
 166                  in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
 167         udelay(1000);
 168
 169         /*
 170          * Set NAND-FLASH GPIO signals to default
 171          */
 172         out_be32((void*)GPIO0_OR,
 173                  in_be32((void*)GPIO0_OR) &
 174                  ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
 175         out_be32((void*)GPIO0_OR,
 176                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 177
 178         /*
 179          * Setup EEPROM write protection
 180          */
 181         out_be32((void*)GPIO0_OR,
 182                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 183         out_be32((void*)GPIO0_TCR,
 184                  in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 185
 186         /*
 187          * Enable interrupts in exar duart mcr[3]
 188          */
 189         out_8((void *)DUART0_BA + 4, 0x08);
 190         out_8((void *)DUART1_BA + 4, 0x08);
 191
 192         /*
 193          * Enable auto RS485 mode in 2nd external uart
 194          */
 195         out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
 196         fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
 197         fctr |= 0x08;                       /* enable RS485 mode */
 198         out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
 199         out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
 200
 201         return 0;
 202 }
 203
 204 /*
 205  * Check Board Identity:
 206  */
 207 int checkboard(void)
 208 {
 209         char str[64];
 210         int i = getenv_r("serial#", str, sizeof(str));
 211
 212         puts("Board: ");
 213
 214         if (i == -1)
 215                 puts("### No HW ID - assuming PLU405");
 216         else
 217                 puts(str);
 218
 219         putc('\n');
 220         return 0;
 221 }
 222
 223 #ifdef CONFIG_IDE_RESET
 224 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 225 void ide_set_reset(int on)
 226 {
 227         /*
 228          * Assert or deassert CompactFlash Reset Pin
 229          */
 230         if (on) {               /* assert RESET */
 231                 out_be16((void *)FPGA_CTRL,
 232                          in_be16((void *)FPGA_CTRL) &
 233                          ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 234         } else {                /* release RESET */
 235                 out_be16((void *)FPGA_CTRL,
 236                          in_be16((void *)FPGA_CTRL) |
 237                          CONFIG_SYS_FPGA_CTRL_CF_RESET);
 238         }
 239 }
 240 #endif /* CONFIG_IDE_RESET */
 241
 242 void reset_phy(void)
 243 {
 244 #ifdef CONFIG_LXT971_NO_SLEEP
 245
 246         /*
 247          * Disable sleep mode in LXT971
 248          */
 249         lxt971_no_sleep();
 250 #endif
 251 }
 252
 253 #if defined(CONFIG_SYS_EEPROM_WREN)
 254 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 255  *             <state> -1: deliver current state
 256  *                      0: disable write
 257  *                      1: enable write
 258  *  Returns:           -1: wrong device address
 259  *                      0: dis-/en- able done
 260  *                    0/1: current state if <state> was -1.
 261  */
 262 int eeprom_write_enable(unsigned dev_addr, int state)
 263 {
 264         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 265                 return -1;
 266         } else {
 267                 switch (state) {
 268                 case 1:
 269                         /* Enable write access, clear bit GPIO0. */
 270                         out_be32((void*)GPIO0_OR,
 271                                  in_be32((void*)GPIO0_OR) &
 272                                  ~CONFIG_SYS_EEPROM_WP);
 273                         state = 0;
 274                         break;
 275                 case 0:
 276                         /* Disable write access, set bit GPIO0. */
 277                         out_be32((void*)GPIO0_OR,
 278                                  in_be32((void*)GPIO0_OR) |
 279                                  CONFIG_SYS_EEPROM_WP);
 280                         state = 0;
 281                         break;
 282                 default:
 283                         /* Read current status back. */
 284                         state = ((in_be32((void*)GPIO0_OR) &
 285                                        CONFIG_SYS_EEPROM_WP) == 0);
 286                         break;
 287                 }
 288         }
 289         return state;
 290 }
 291
 292 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 293 {
 294         int query = argc == 1;
 295         int state = 0;
 296
 297         if (query) {
 298                 /* Query write access state. */
 299                 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 300                 if (state < 0) {
 301                         puts("Query of write access state failed.\n");
 302                 } else {
 303                         printf("Write access for device 0x%0x is %sabled.\n",
 304                                CONFIG_SYS_I2C_EEPROM_ADDR,
 305                                state ? "en" : "dis");
 306                         state = 0;
 307                 }
 308         } else {
 309                 if (argv[1][0] == '0') {
 310                         /* Disable write access. */
 311                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 312                                                     0);
 313                 } else {
 314                         /* Enable write access. */
 315                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 316                                                     1);
 317                 }
 318                 if (state < 0)
 319                         puts("Setup of write access state failed.\n");
 320         }
 321
 322         return state;
 323 }
 324
 325 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 326         "Enable / disable / query EEPROM write access",
 327         ""
 328 );
 329 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */