2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
35 extern void lxt971_no_sleep(void);
37 /* fpga configuration data - gzip compressed and generated by bin2c */
38 const unsigned char fpgadata[] =
44 * include common fpga code (for esd boards)
46 #include "../common/fpga.c"
49 * include common auto-update code (for esd boards)
51 #include "../common/auto_update.h"
53 au_image_t au_image[] = {
54 {"plu405/preinst.img", 0, -1, AU_SCRIPT},
55 {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
56 {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
57 {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
58 {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
59 {"plu405/postinst.img", 0, 0, AU_SCRIPT},
62 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
65 int gunzip(void *, int, unsigned char *, unsigned long *);
67 int board_early_init_f(void)
70 * IRQ 0-15 405GP internally generated; active high; level sensitive
71 * IRQ 16 405GP internally generated; active low; level sensitive
73 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
74 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
75 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
76 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
77 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
78 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
79 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
81 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
82 mtdcr(uicer, 0x00000000); /* disable all ints */
83 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
84 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
85 mtdcr(uictr, 0x10000000); /* set int trigger levels */
86 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
87 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
90 * EBC Configuration Register: set ready timeout to
91 * 512 ebc-clks -> ca. 15 us
93 mtebc(epcr, 0xa8400000); /* ebc always driven */
102 ulong len = sizeof(fpgadata);
107 /* adjust flash start and offset */
108 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
109 gd->bd->bi_flashoffset = 0;
111 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
112 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
113 (uchar *)fpgadata, &len) != 0) {
114 printf("GUNZIP ERROR - must RESET board to recover\n");
115 do_reset(NULL, 0, 0, NULL);
118 status = fpga_boot(dst, len);
120 printf("\nFPGA: Booting failed ");
122 case ERROR_FPGA_PRG_INIT_LOW:
123 printf("(Timeout: INIT not low "
124 "after asserting PROGRAM*)\n");
126 case ERROR_FPGA_PRG_INIT_HIGH:
127 printf("(Timeout: INIT not high "
128 "after deasserting PROGRAM*)\n");
130 case ERROR_FPGA_PRG_DONE:
131 printf("(Timeout: DONE not high "
132 "after programming FPGA)\n");
136 /* display infos on fpgaimage */
138 for (i=0; i<4; i++) {
140 printf("FPGA: %s\n", &(dst[index+1]));
145 for (i=20; i>0; i--) {
146 printf("Rebooting in %2d seconds \r",i);
147 for (index=0;index<1000;index++)
151 do_reset(NULL, 0, 0, NULL);
156 /* display infos on fpgaimage */
158 for (i=0; i<4; i++) {
160 printf("%s ", &(dst[index+1]));
168 * Reset FPGA via FPGA_DATA pin
170 SET_FPGA(FPGA_PRG | FPGA_CLK);
171 udelay(1000); /* wait 1ms */
172 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
173 udelay(1000); /* wait 1ms */
176 * Reset external DUARTs
178 out_be32((void*)GPIO0_OR,
179 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
181 out_be32((void*)GPIO0_OR,
182 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
186 * Set NAND-FLASH GPIO signals to default
188 out_be32((void*)GPIO0_OR,
189 in_be32((void*)GPIO0_OR) &
190 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
191 out_be32((void*)GPIO0_OR,
192 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
195 * Setup EEPROM write protection
197 out_be32((void*)GPIO0_OR,
198 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
199 out_be32((void*)GPIO0_TCR,
200 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
203 * Enable interrupts in exar duart mcr[3]
205 out_8((void *)DUART0_BA + 4, 0x08);
206 out_8((void *)DUART1_BA + 4, 0x08);
209 * Enable auto RS485 mode in 2nd external uart
211 out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
212 fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
213 fctr |= 0x08; /* enable RS485 mode */
214 out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
215 out_8((void *)DUART1_BA + 3, 0); /* write LCR */
221 * Check Board Identity:
226 int i = getenv_r("serial#", str, sizeof(str));
231 puts("### No HW ID - assuming PLU405");
239 #ifdef CONFIG_IDE_RESET
240 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
241 void ide_set_reset(int on)
244 * Assert or deassert CompactFlash Reset Pin
246 if (on) { /* assert RESET */
247 out_be16((void *)FPGA_CTRL,
248 in_be16((void *)FPGA_CTRL) &
249 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
250 } else { /* release RESET */
251 out_be16((void *)FPGA_CTRL,
252 in_be16((void *)FPGA_CTRL) |
253 CONFIG_SYS_FPGA_CTRL_CF_RESET);
256 #endif /* CONFIG_IDE_RESET */
260 #ifdef CONFIG_LXT971_NO_SLEEP
263 * Disable sleep mode in LXT971
269 #if defined(CONFIG_SYS_EEPROM_WREN)
270 /* Input: <dev_addr> I2C address of EEPROM device to enable.
271 * <state> -1: deliver current state
274 * Returns: -1: wrong device address
275 * 0: dis-/en- able done
276 * 0/1: current state if <state> was -1.
278 int eeprom_write_enable(unsigned dev_addr, int state)
280 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
285 /* Enable write access, clear bit GPIO0. */
286 out_be32((void*)GPIO0_OR,
287 in_be32((void*)GPIO0_OR) &
288 ~CONFIG_SYS_EEPROM_WP);
292 /* Disable write access, set bit GPIO0. */
293 out_be32((void*)GPIO0_OR,
294 in_be32((void*)GPIO0_OR) |
295 CONFIG_SYS_EEPROM_WP);
299 /* Read current status back. */
300 state = ((in_be32((void*)GPIO0_OR) &
301 CONFIG_SYS_EEPROM_WP) == 0);
308 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
310 int query = argc == 1;
314 /* Query write access state. */
315 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
317 puts("Query of write access state failed.\n");
319 printf("Write access for device 0x%0x is %sabled.\n",
320 CONFIG_SYS_I2C_EEPROM_ADDR,
321 state ? "en" : "dis");
325 if (argv[1][0] == '0') {
326 /* Disable write access. */
327 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
330 /* Enable write access. */
331 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
335 puts("Setup of write access state failed.\n");
341 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
342 "Enable / disable / query EEPROM write access",
345 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */