3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
11 #include <asm/processor.h>
13 #include <asm/ppc4xx-gpio.h>
14 #include <asm/4xx_pci.h>
19 * PMC405-DE cpld registers
20 * - all registers are 8 bit
21 * - all registers are on 32 bit addesses
23 struct pmc405de_cpld {
24 /* cpld design version */
28 /* misc. status lines */
34 * gate bit(s) must be written with '1' to
41 #define CPLD_VERSION_MASK 0x0f
42 #define CPLD_CONTROL_POSTLED_N 0x01
43 #define CPLD_CONTROL_POSTLED_GATE 0x02
44 #define CPLD_CONTROL_RESETOUT_N 0x40
45 #define CPLD_CONTROL_RESETOUT_N_GATE 0x80
47 DECLARE_GLOBAL_DATA_PTR;
49 extern void __ft_board_setup(void *blob, bd_t *bd);
50 extern void pll_write(u32 a, u32 b);
52 static int wait_for_pci_ready_done;
54 static int is_monarch(void);
55 static int pci_is_66mhz(void);
56 static int board_revision(void);
57 static int cpld_revision(void);
58 static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
60 int board_early_init_f(void)
65 * check M66EN and patch PLB:PCI divider for 66MHz PCI
67 * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
68 * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
69 * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
70 * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
72 * calling upd_plb_pci_div() may end in calling pll_write() which will
73 * do a chip reset and never return.
75 pllmr0 = mfdcr(CPC0_PLLMR0);
76 pllmr1 = mfdcr(CPC0_PLLMR1);
78 if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
79 /* fCPU=333MHz, fPLB=111MHz */
81 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
83 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
85 /* fCPU=133|266MHz, fPLB=133MHz */
87 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
89 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
93 * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
94 * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
95 * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
96 * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
97 * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
98 * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
99 * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
101 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
102 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
103 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
104 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
105 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
106 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */
107 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
110 * EBC Configuration Register:
111 * - set ready timeout to 512 ebc-clks -> ca. 15 us
112 * - EBC lines are always driven
114 mtebc(EBC0_CFG, 0xa8400000);
119 static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
121 if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
122 pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
125 int misc_init_r(void)
128 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
129 struct pmc405de_cpld *cpld =
130 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
133 /* PCI configuration done: release EREADY */
134 setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
135 setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
138 /* turn off POST LED */
139 out_8(&cpld->control,
140 CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
142 /* turn on LEDs: RUN, A, B */
143 clrbits_be32(&gpio0->or,
144 CONFIG_SYS_GPIO_LEDRUN_N |
145 CONFIG_SYS_GPIO_LEDA_N |
146 CONFIG_SYS_GPIO_LEDB_N);
148 for (i=0; i < 200; i++)
151 /* turn off LEDs: A, B */
152 setbits_be32(&gpio0->or,
153 CONFIG_SYS_GPIO_LEDA_N |
154 CONFIG_SYS_GPIO_LEDB_N);
159 static int is_monarch(void)
161 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
162 return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
165 static int pci_is_66mhz(void)
167 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
168 return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
171 static int board_revision(void)
173 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
174 return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
175 CONFIG_SYS_GPIO_HWREV_SHIFT);
178 static int cpld_revision(void)
180 struct pmc405de_cpld *cpld =
181 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
182 return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
186 * Check Board Identity
190 puts("Board: esd GmbH - PMC-CPU/405-DE");
192 gd->board_type = board_revision();
193 printf(", Rev 1.%ld, ", gd->board_type);
198 printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
199 pci_is_66mhz() ? "66" : "33", cpld_revision());
205 static void wait_for_pci_ready(void)
207 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
209 char *s = getenv("pcidelay");
212 if (wait_for_pci_ready_done)
216 * We have our own handling of the pcidelay variable.
217 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
218 * and adapter devices. For adapter devices we do not
222 int ms = simple_strtoul(s, NULL, 10);
223 printf("PCI: Waiting for %d ms\n", ms);
228 if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
229 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
235 if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
242 wait_for_pci_ready_done = 1;
246 * Overwrite weak is_pci_host()
248 * This routine is called to determine if a pci scan should be
249 * performed. With various hardware environments (especially cPCI and
250 * PPMC) it's insufficient to depend on the state of the arbiter enable
251 * bit in the strap register, or generic host/adapter assumptions.
253 * Return 0 for adapter mode, non-zero for host (monarch) mode.
255 int is_pci_host(struct pci_controller *hose)
261 * Overwrite PCI identification when running in
263 * This should be moved into pci_target_init()
264 * when it is sometimes available for 405 CPUs
266 pci_write_config_word(PCIDEVID_405GP,
268 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
269 pci_write_config_word(PCIDEVID_405GP,
271 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
274 s = getenv("pciscan");
277 wait_for_pci_ready();
283 if (!strcmp(s, "yes"))
291 * Overwrite weak pci_pre_init()
293 * The default implementation enables the 405EP
294 * internal PCI arbiter. We do not want that
297 int pci_pre_init(struct pci_controller *hose)
302 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
303 int ft_board_setup(void *blob, bd_t *bd)
307 __ft_board_setup(blob, bd);
310 * Disable PCI in non-monarch mode.
313 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
314 "disabled", sizeof("disabled"), 1);
316 printf("Unable to update property status in PCI node, "
324 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
326 #if defined(CONFIG_SYS_EEPROM_WREN)
327 /* Input: <dev_addr> I2C address of EEPROM device to enable.
328 * <state> -1: deliver current state
331 * Returns: -1: wrong device address
332 * 0: dis-/en- able done
333 * 0/1: current state if <state> was -1.
335 int eeprom_write_enable(unsigned dev_addr, int state)
337 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
339 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
344 /* Enable write access, clear bit GPIO0. */
345 clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
349 /* Disable write access, set bit GPIO0. */
350 setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
354 /* Read current status back. */
355 state = (0 == (in_be32(&gpio0->or) &
356 CONFIG_SYS_GPIO_EEPROM_WP));
363 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
365 int query = argc == 1;
369 /* Query write access state. */
370 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
372 puts("Query of write access state failed.\n");
374 printf("Write access for device 0x%0x is %sabled.\n",
375 CONFIG_SYS_I2C_EEPROM_ADDR,
376 state ? "en" : "dis");
380 if ('0' == argv[1][0]) {
381 /* Disable write access. */
382 state = eeprom_write_enable(
383 CONFIG_SYS_I2C_EEPROM_ADDR, 0);
385 /* Enable write access. */
386 state = eeprom_write_enable(
387 CONFIG_SYS_I2C_EEPROM_ADDR, 1);
390 puts ("Setup of write access state failed.\n");
396 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
397 "Enable / disable / query EEPROM write access",
400 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
402 #if defined(CONFIG_PRAM)
403 #include <environment.h>
405 int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
407 u32 pram, nextbase, base;
414 pram = simple_strtoul(v, NULL, 10);
416 printf("Error: pram undefined. Please define pram in KiB\n");
420 base = gd->bd->bi_memsize;
421 #if defined(CONFIG_LOGBUFFER)
422 base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
425 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
427 param = base - (pram << 10);
428 printf("PARAM: @%08x\n", param);
429 debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
431 /* clear entire PA ram */
432 memset((void*)param, 0, (pram << 10));
434 /* reserve 4k for pointer field */
435 nextbase = base - 4096;
436 lptr = (ulong*)(base);
439 * *(--lptr) = item_size;
440 * *(--lptr) = base - item_base = distance from field top;
443 /* env is first (4k aligned) */
444 nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
445 memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
446 *(--lptr) = CONFIG_ENV_SIZE; /* size */
447 *(--lptr) = base - nextbase; /* offset | type=0 */
450 *(--lptr) = nextbase - param; /* size */
451 *(--lptr) = (base - param) | 126; /* offset | type=126 */
453 /* terminate pointer field */
454 *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
455 *(--lptr) = 0; /* offset=0 -> terminator */
459 painit, 1, 1, do_painit,
460 "prepare PciAccess system",
463 #endif /* CONFIG_PRAM */
465 int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
467 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
468 setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
472 selfreset, 1, 1, do_selfreset,
473 "assert self-reset# signal",
477 int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
479 struct pmc405de_cpld *cpld =
480 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
483 if (argv[1][0] == '0') {
485 printf("PMC-RESETOUT# asserted\n");
486 out_8(&cpld->control,
487 CPLD_CONTROL_RESETOUT_N_GATE);
490 printf("PMC-RESETOUT# deasserted\n");
491 out_8(&cpld->control,
492 CPLD_CONTROL_RESETOUT_N |
493 CPLD_CONTROL_RESETOUT_N_GATE);
496 printf("PMC-RESETOUT# is %s\n",
497 (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
498 "inactive" : "active");
503 resetout, 2, 1, do_resetout,
504 "assert PMC-RESETOUT# signal",