2 * (C) Copyright 2007-2008
3 * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/cache.h>
12 #include <asm/processor.h>
13 #if defined(CONFIG_LOGBUFFER)
20 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
21 uchar *buffer, unsigned cnt);
22 int eeprom_write_enable(unsigned dev_addr, int state);
24 DECLARE_GLOBAL_DATA_PTR;
26 #if defined(CONFIG_CMD_BSP)
28 static int got_fifoirq;
31 int fpga_interrupt(u32 arg)
33 pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
34 int rc = -1; /* not for us */
35 u32 status = FPGA_IN32(&fpga->status);
37 /* check for interrupt from fifo module */
38 if (status & STATUS_FIFO_ISF) {
39 /* disable this int source */
40 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
42 got_fifoirq = 1; /* trigger backend */
45 if (status & STATUS_HOST_ISF) {
46 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
54 int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
56 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
60 FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
61 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
63 irq_install_handler(IRQ0_FPGA,
64 (interrupt_handler_t *)fpga_interrupt,
67 FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
70 /* Abort if ctrl-c was pressed */
77 printf("Got interrupt!\n");
79 FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
80 irq_free_handler(IRQ0_FPGA);
84 waithci, 1, 1, do_waithci,
85 "Wait for host control interrupt",
89 void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
93 while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
94 printf("%5d %d %3d %08x",
95 (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
96 FPGA_IN32(&fpga->fifo[f].data));
97 if (ctrl & FIFO_OVERFLOW) {
98 printf(" OVERFLOW\n");
99 FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
105 int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
107 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
111 char str[] = "\\|/-";
118 /* print all fifos status information */
119 printf("fifo level status\n");
120 printf("______________________________\n");
121 for (i=0; i<FIFO_COUNT; i++) {
122 ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
123 printf(" %d %3d %s%s%s %s\n",
124 i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
125 ctrl & FIFO_FULL ? "FULL " : "",
126 ctrl & FIFO_EMPTY ? "EMPTY " : "",
127 ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
128 ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
133 /* completely read out fifo 'n' */
134 if (!strcmp(argv[1],"read")) {
135 printf(" # fifo level data\n");
136 printf("______________________________\n");
138 for (i=0; i<FIFO_COUNT; i++)
139 dump_fifo(fpga, i, &n);
141 } else if (!strcmp(argv[1],"wait")) {
144 irq_install_handler(IRQ0_FPGA,
145 (interrupt_handler_t *)fpga_interrupt,
148 printf(" # fifo level data\n");
149 printf("______________________________\n");
151 /* enable all fifo interrupts */
152 FPGA_OUT32(&fpga->hostctrl,
153 HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
154 for (i=0; i<FIFO_COUNT; i++) {
155 /* enable interrupts from all fifos */
156 FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
161 while (!got_fifoirq) {
163 if (!(count % 100)) {
165 putc(0x08); /* backspace */
166 putc(str[count2 % 4]);
169 /* Abort if ctrl-c was pressed */
170 if ((abort = ctrlc())) {
179 /* simple fifo backend */
181 for (i=0; i<FIFO_COUNT; i++)
182 dump_fifo(fpga, i, &n);
185 /* unmask global fifo irq */
186 FPGA_OUT32(&fpga->hostctrl,
187 HOSTCTRL_FIFOIE_GATE |
188 HOSTCTRL_FIFOIE_FLAG);
192 /* disable all fifo interrupts */
193 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
194 for (i=0; i<FIFO_COUNT; i++)
195 FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
197 irq_free_handler(IRQ0_FPGA);
200 printf("Usage:\nfifo %s\n", cmdtp->help);
207 if (!strcmp(argv[1],"write")) {
208 /* get fifo number or fifo address */
209 f = simple_strtoul(argv[2], NULL, 16);
212 data = simple_strtoul(argv[3], NULL, 16);
214 /* get optional count parameter */
217 n = (int)simple_strtoul(argv[4], NULL, 10);
219 if (f < FIFO_COUNT) {
220 printf("writing %d x %08x to fifo %d\n",
223 FPGA_OUT32(&fpga->fifo[f].data, data);
225 printf("writing %d x %08x to fifo port at "
229 out_be32((void *)f, data);
232 printf("Usage:\nfifo %s\n", cmdtp->help);
238 printf("Usage:\nfifo %s\n", cmdtp->help);
245 "Fifo module operations",
247 "fifo write fifo(0..3) data [cnt=1]\n"
248 "fifo write address(>=4) data [cnt=1]\n"
249 " - without arguments: print all fifo's status\n"
250 " - with 'wait' argument: interrupt driven read from all fifos\n"
251 " - with 'read' argument: read current contents from all fifos\n"
252 " - with 'write' argument: write 'data' 'cnt' times to "
253 "'fifo' or 'address'"
256 int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
263 printf("Usage:\nsbe %s\n", cmdtp->help);
268 if (!strcmp(argv[1], "400")) {
269 /* PLB=133MHz, PLB/PCI=3 */
270 printf("Bootstrapping for 400MHz\n");
275 } else if (!strcmp(argv[1], "533")) {
276 /* PLB=133MHz, PLB/PCI=3 */
277 printf("Bootstrapping for 533MHz\n");
282 } else if (!strcmp(argv[1], "667")) {
283 /* PLB=133MHz, PLB/PCI=3 */
284 printf("Bootstrapping for 667MHz\n");
290 printf("Usage:\nsbe %s\n", cmdtp->help);
299 else if (argv[2][0]=='0')
306 delay = simple_strtoul(argv[3], NULL, 10);
312 printf("Writing boot EEPROM ...\n");
313 if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
314 0, (uchar*)sdsdp, count) != 0)
315 printf("bootstrap_eeprom_write failed\n");
317 printf("done (dump via 'i2c md 52 0.1 14')\n");
322 sbe, 4, 0, do_setup_bootstrap_eeprom,
323 "setup bootstrap eeprom",
324 "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
327 #if defined(CONFIG_PRAM)
328 #include <environment.h>
332 int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
334 u32 pram, nextbase, base;
345 pram = simple_strtoul(v, NULL, 10);
347 printf("Error: pram undefined. Please define pram in KiB\n");
351 base = (u32)gd->ram_size;
352 #if defined(CONFIG_LOGBUFFER)
353 base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
356 * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
358 param = base - (pram << 10);
359 printf("PARAM: @%08x\n", param);
360 debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
362 /* clear entire PA ram */
363 memset((void*)param, 0, (pram << 10));
365 /* reserve 4k for pointer field */
366 nextbase = base - 4096;
367 lptr = (ulong*)(base);
370 * *(--lptr) = item_size;
371 * *(--lptr) = base - item_base = distance from field top;
374 /* env is first (4k aligned) */
375 nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
376 envp = (env_t *)nextbase;
377 res = (char *)envp->data;
378 len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
380 error("Cannot export environment: errno = %d\n", errno);
383 envp->crc = crc32(0, envp->data, ENV_SIZE);
385 *(--lptr) = CONFIG_ENV_SIZE; /* size */
386 *(--lptr) = base - nextbase; /* offset | type=0 */
389 *(--lptr) = nextbase - param; /* size */
390 *(--lptr) = (base - param) | 126; /* offset | type=126 */
392 /* terminate pointer field */
393 *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
394 *(--lptr) = 0; /* offset=0 -> terminator */
398 painit, 1, 1, do_painit,
399 "prepare PciAccess system",
402 #endif /* CONFIG_PRAM */
404 int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
406 in_be32((void*)CONFIG_SYS_RESET_BASE);
410 selfreset, 1, 1, do_selfreset,
411 "assert self-reset# signal",
415 int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
417 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
419 /* requiers bootet FPGA and PLD_IOEN_N active */
420 if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
421 printf("Error: resetout requires a bootet FPGA\n");
426 if (argv[1][0] == '0') {
428 printf("PMC-RESETOUT# asserted\n");
429 FPGA_OUT32(&fpga->hostctrl,
430 HOSTCTRL_PMCRSTOUT_GATE);
433 printf("PMC-RESETOUT# deasserted\n");
434 FPGA_OUT32(&fpga->hostctrl,
435 HOSTCTRL_PMCRSTOUT_GATE |
436 HOSTCTRL_PMCRSTOUT_FLAG);
439 printf("PMC-RESETOUT# is %s\n",
440 FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
441 "inactive" : "active");
447 resetout, 2, 1, do_resetout,
448 "assert PMC-RESETOUT# signal",
452 int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
455 printf("This command is only supported in non-monarch mode\n");
460 if (argv[1][0] == '0') {
462 printf("inta# asserted\n");
463 out_be32((void*)GPIO1_TCR,
464 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
467 printf("inta# deasserted\n");
468 out_be32((void*)GPIO1_TCR,
469 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
472 printf("inta# is %s\n",
473 in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
474 "active" : "inactive");
480 "Assert/Deassert or query INTA# state in non-monarch mode",
485 int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
490 pciaddr = simple_strtoul(argv[1], NULL, 16);
492 pciaddr &= 0xf0000000;
494 /* map PCI address at 0xc0000000 in PLB space */
496 /* PMM1 Mask/Attribute - disabled b4 setting */
497 out32r(PCIL0_PMM1MA, 0x00000000);
498 /* PMM1 Local Address */
499 out32r(PCIL0_PMM1LA, 0xc0000000);
500 /* PMM1 PCI Low Address */
501 out32r(PCIL0_PMM1PCILA, pciaddr);
502 /* PMM1 PCI High Address */
503 out32r(PCIL0_PMM1PCIHA, 0x00000000);
504 /* 256MB + No prefetching, and enable region */
505 out32r(PCIL0_PMM1MA, 0xf0000001);
507 printf("Usage:\npmm %s\n", cmdtp->help);
513 "Setup pmm[1] registers",
514 "<pciaddr> (pciaddr will be aligned to 256MB)"
517 #if defined(CONFIG_SYS_EEPROM_WREN)
518 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
520 int query = argc == 1;
524 /* Query write access state. */
525 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
527 puts("Query of write access state failed.\n");
529 printf("Write access for device 0x%0x is %sabled.\n",
530 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
534 if ('0' == argv[1][0]) {
535 /* Disable write access. */
536 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
538 /* Enable write access. */
539 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
542 puts("Setup of write access state failed.\n");
548 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
549 "Enable / disable / query EEPROM write access",
552 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
554 #endif /* CONFIG_CMD_BSP */