3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /*-----------------------------------------------------------------------
31 #define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
32 #define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */
33 #define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */
34 #define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */
35 #define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */
36 #define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */
37 #define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */
39 #define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */
40 #define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */
41 #define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
42 #define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
43 #define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
44 #define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */
46 /* FPGA programming pin configuration */
47 #define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
48 #define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
49 #define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
50 #define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */
51 #define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
52 #define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
54 /*-----------------------------------------------------------------------
57 #define FPGA_BA CFG_FPGA_BASE0
58 #define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
59 #define FPGA_IN32(p) in_be32((void*)(p))
60 #define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
61 #define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
63 struct pmc440_fifo_s {
68 /* fifo ctrl register */
69 #define FIFO_IE (1 << 15)
70 #define FIFO_OVERFLOW (1 << 10)
71 #define FIFO_EMPTY (1 << 9)
72 #define FIFO_FULL (1 << 8)
73 #define FIFO_LEVEL_MASK 0x000000ff
77 struct pmc440_fpga_s {
81 u32 pad1[0x40 / sizeof(u32) - 3];
82 u32 irig_time; /* offset: 0x0040 */
86 u32 irig_rx_time; /* offset: 0x0050 */
88 u32 hostctrl; /* offset: 0x0060 */
89 u32 pad4[0x20 / sizeof(u32) - 1];
90 struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
93 typedef struct pmc440_fpga_s pmc440_fpga_t;
96 #define CTRL_HOST_IE (1 << 8)
99 #define RESET_EN (1 << 31)
100 #define CLOCK_EN (1 << 30)
101 #define RESET_OUT (1 << 19)
102 #define CLOCK_OUT (1 << 22)
103 #define RESET_OUT (1 << 19)
104 #define IRIGB_R_OUT (1 << 14)
107 /* status register */
108 #define STATUS_VERSION_SHIFT 24
109 #define STATUS_VERSION_MASK 0xff000000
110 #define STATUS_HWREV_SHIFT 20
111 #define STATUS_HWREV_MASK 0x00f00000
113 #define STATUS_CAN_ISF (1 << 11)
114 #define STATUS_CSTM_ISF (1 << 10)
115 #define STATUS_FIFO_ISF (1 << 9)
116 #define STATUS_HOST_ISF (1 << 8)
120 #define RESET_IN (1 << 0)
121 #define CLOCK_IN (1 << 1)
122 #define IRIGB_R_IN (1 << 5)
125 /* hostctrl register */
126 #define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
127 #define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
128 #define HOSTCTRL_CSTM1IE_GATE (1 << 7)
129 #define HOSTCTRL_CSTM1IW_FLAG (1 << 6)
130 #define HOSTCTRL_CSTM0IE_GATE (1 << 5)
131 #define HOSTCTRL_CSTM0IW_FLAG (1 << 4)
132 #define HOSTCTRL_FIFOIE_GATE (1 << 3)
133 #define HOSTCTRL_FIFOIE_FLAG (1 << 2)
134 #define HOSTCTRL_HCINT_GATE (1 << 1)
135 #define HOSTCTRL_HCINT_FLAG (1 << 0)
137 #define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000)
138 #define NGCC_CTRL_FPGARST_N (1 << 2)
140 /*-----------------------------------------------------------------------
141 * FPGA to PPC interrupt
143 #define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
144 #define IRQ1_FPGA (32+30) /* UIC1 - custom module */
145 #define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */
146 #define IRQ_ETH0 (64+ 4) /* UIC2 */
147 #define IRQ_ETH1 ( 27) /* UIC0 */
148 #define IRQ_RTC (64+ 0) /* UIC2 */
149 #define IRQ_PCIA (64+ 1) /* UIC2 */
150 #define IRQ_PCIB (32+18) /* UIC1 */
151 #define IRQ_PCIC (32+19) /* UIC1 */
152 #define IRQ_PCID (32+20) /* UIC1 */
154 #endif /* __PMC440_H__ */