3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
6 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
7 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
8 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
9 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
10 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
12 * (C) Copyright 2006-2007
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* define DEBUG for debug output */
35 #include <asm/processor.h>
40 extern int denali_wait_for_dlllock(void);
41 extern void denali_core_search_data_eye(void);
49 struct sdram_conf_s sdram_conf[] = {
50 {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
51 {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
52 {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
56 * initdram -- 440EPx's DDR controller is a DENALI Core
58 int initdram_by_rb(int rows, int banks)
60 ulong speed = get_bus_freq(0);
62 mtsdram(DDR0_02, 0x00000000);
64 mtsdram(DDR0_00, 0x0000190A);
65 mtsdram(DDR0_01, 0x01000000);
66 mtsdram(DDR0_03, 0x02030602);
67 mtsdram(DDR0_04, 0x0A020200);
68 mtsdram(DDR0_05, 0x02020308);
69 mtsdram(DDR0_06, 0x0102C812);
70 mtsdram(DDR0_07, 0x000D0100);
71 mtsdram(DDR0_08, 0x02430001);
72 mtsdram(DDR0_09, 0x00011D5F);
73 mtsdram(DDR0_10, 0x00000100);
74 mtsdram(DDR0_11, 0x0027C800);
75 mtsdram(DDR0_12, 0x00000003);
76 mtsdram(DDR0_14, 0x00000000);
77 mtsdram(DDR0_17, 0x19000000);
78 mtsdram(DDR0_18, 0x19191919);
79 mtsdram(DDR0_19, 0x19191919);
80 mtsdram(DDR0_20, 0x0B0B0B0B);
81 mtsdram(DDR0_21, 0x0B0B0B0B);
82 mtsdram(DDR0_22, 0x00267F0B);
83 mtsdram(DDR0_23, 0x00000000);
84 mtsdram(DDR0_24, 0x01010002);
85 if (speed > 133333334)
86 mtsdram(DDR0_26, 0x5B26050C);
88 mtsdram(DDR0_26, 0x5B260408);
89 mtsdram(DDR0_27, 0x0000682B);
90 mtsdram(DDR0_28, 0x00000000);
91 mtsdram(DDR0_31, 0x00000000);
94 DDR0_42_ADDR_PINS_DECODE(14 - rows) |
97 DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
100 mtsdram(DDR0_44, 0x00000003);
101 mtsdram(DDR0_02, 0x00000001);
103 denali_wait_for_dlllock();
105 #ifdef CONFIG_DDR_DATA_EYE
107 * Perform data eye search if requested.
109 denali_core_search_data_eye();
112 * Clear possible errors resulting from data-eye-search.
113 * If not done, then we could get an interrupt later on when
114 * exceptions are enabled.
116 set_mcsr(get_mcsr());
121 phys_size_t initdram(int board_type)
126 /* go through supported memory configurations */
127 for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
128 size = sdram_conf[n].size;
130 /* program TLB entries */
131 program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
137 initdram_by_rb(sdram_conf[n].rows,
138 sdram_conf[n].banks);
140 /* check for suitable configuration */
141 if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
144 /* delete TLB entries */
145 remove_tlb(CONFIG_SYS_SDRAM_BASE, size);