2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
35 /* fpga configuration data - gzip compressed and generated by bin2c */
36 const unsigned char fpgadata[] =
42 * include common fpga code (for esd boards)
44 #include "../common/fpga.c"
47 int board_early_init_f (void)
50 * IRQ 0-15 405GP internally generated; active high; level sensitive
51 * IRQ 16 405GP internally generated; active low; level sensitive
53 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
54 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
55 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
56 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
57 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
58 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
59 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
61 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
62 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
63 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
64 mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
65 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
66 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
67 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
70 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
72 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
77 int misc_init_r (void)
80 ulong len = sizeof(fpgadata);
85 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
86 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
87 printf ("GUNZIP ERROR - must RESET board to recover\n");
88 do_reset (NULL, 0, 0, NULL);
91 status = fpga_boot(dst, len);
93 printf("\nFPGA: Booting failed ");
95 case ERROR_FPGA_PRG_INIT_LOW:
96 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
98 case ERROR_FPGA_PRG_INIT_HIGH:
99 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
101 case ERROR_FPGA_PRG_DONE:
102 printf("(Timeout: DONE not high after programming FPGA)\n ");
106 /* display infos on fpgaimage */
108 for (i=0; i<4; i++) {
110 printf("FPGA: %s\n", &(dst[index+1]));
115 for (i=20; i>0; i--) {
116 printf("Rebooting in %2d seconds \r",i);
117 for (index=0;index<1000;index++)
121 do_reset(NULL, 0, 0, NULL);
126 /* display infos on fpgaimage */
128 for (i=0; i<4; i++) {
130 printf("%s ", &(dst[index+1]));
138 * Reset FPGA via FPGA_DATA pin
140 SET_FPGA(FPGA_PRG | FPGA_CLK);
141 udelay(1000); /* wait 1ms */
142 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
143 udelay(1000); /* wait 1ms */
146 * Reset external DUARTs
148 out_be32((void *)GPIO0_OR,
149 in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
150 udelay(10); /* wait 10us */
151 out_be32((void *)GPIO0_OR,
152 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
153 udelay(1000); /* wait 1ms */
156 * Enable interrupts in exar duart mcr[3]
158 out_8((void *)(DUART0_BA + 4), 0x08);
159 out_8((void *)(DUART1_BA + 4), 0x08);
160 out_8((void *)(DUART2_BA + 4), 0x08);
161 out_8((void *)(DUART3_BA + 4), 0x08);
168 * Check Board Identity:
171 int checkboard (void)
174 int i = getenv_f("serial#", str, sizeof(str));
179 puts ("### No HW ID - assuming WUH405");