3 * Stefano Babic DENX Software Engineering sbabic@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not write to the Free Software
20 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
23 * Refer doc/README.imximage for more details about how-to configure
24 * and create imximage boot image
26 * The syntax is taken as close as possible with the kwbimage
33 * Boot Device : one of
34 * spi, sd (the board has no nand neither onenand)
39 * Device Configuration Data (DCD)
41 * Each entry must have the format:
42 * Addr-type Address Value
45 * Addr-type register length (1,2 or 4 bytes)
46 * Address absolute address of the register
47 * value value to be stored in the register
49 /* IOMUX for RAM only */
50 DATA 4 0x53fa8554 0x300020
51 DATA 4 0x53fa8560 0x300020
52 DATA 4 0x53fa8594 0x300020
53 DATA 4 0x53fa8584 0x300020
54 DATA 4 0x53fa8558 0x300040
55 DATA 4 0x53fa8568 0x300040
56 DATA 4 0x53fa8590 0x300040
57 DATA 4 0x53fa857c 0x300040
58 DATA 4 0x53fa8564 0x300040
59 DATA 4 0x53fa8580 0x300040
60 DATA 4 0x53fa8570 0x300220
61 DATA 4 0x53fa8578 0x300220
62 DATA 4 0x53fa872c 0x300000
63 DATA 4 0x53fa8728 0x300000
64 DATA 4 0x53fa871c 0x300000
65 DATA 4 0x53fa8718 0x300000
66 DATA 4 0x53fa8574 0x300020
67 DATA 4 0x53fa8588 0x300020
70 DATA 4 0x53fa856c 0x300040
71 DATA 4 0x53fa86f0 0x300000
72 DATA 4 0x53fa8720 0x300000
76 DATA 4 0x53fa8724 0x4000000
79 DATA 4 0x63fd9088 0x40404040
80 DATA 4 0x63fd9090 0x40404040
81 DATA 4 0x63fd907C 0x01420143
82 DATA 4 0x63fd9080 0x01450146
83 DATA 4 0x63fd9018 0x00111740
84 DATA 4 0x63fd9000 0x84190000
87 DATA 4 0x63fd900C 0x9f5152e3
88 DATA 4 0x63fd9010 0xb68e8a63
89 DATA 4 0x63fd9014 0x01ff00db
91 /* Read/Write command delay */
92 DATA 4 0x63fd902c 0x000026d2
94 /* Out of reset delays */
95 DATA 4 0x63fd9030 0x00ff0e21
97 /* ESDCTL ODT timing control */
98 DATA 4 0x63fd9008 0x12273030
100 /* ESDCTL power down control */
101 DATA 4 0x63fd9004 0x0002002d
103 /* Set registers in DDR memory chips */
104 DATA 4 0x63fd901c 0x00008032
105 DATA 4 0x63fd901c 0x00008033
106 DATA 4 0x63fd901c 0x00028031
107 DATA 4 0x63fd901c 0x052080b0
108 DATA 4 0x63fd901c 0x04008040
110 /* ESDCTL refresh control */
111 DATA 4 0x63fd9020 0x00005800
113 /* PHY ZQ HW control */
114 DATA 4 0x63fd9040 0x05380003
116 /* PHY ODT control */
117 DATA 4 0x63fd9058 0x00022222
120 DATA 4 0x63fd901c 0x00000000