2 * Copyright (C) 2009 Renesas Solutions Corp.
3 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 * board/espt/lowlevel_init.S
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
12 #include <asm/macro.h>
21 write32 WDTCSR_A, WDTCSR_D
23 write32 WDTST_A, WDTST_D
25 write32 WDTBST_A, WDTBST_D
27 write32 CCR_A, CCR_CACHE_ICI_D
29 write32 MMUCR_A, MMU_CONTROL_TI_D
31 write32 MSTPCR0_A, MSTPCR0_D
33 write32 MSTPCR1_A, MSTPCR1_D
35 write32 RAMCR_A, RAMCR_D
38 * Setting infomation from
39 * original ESPT-GIGA bootloader register
41 write32 MMSEL_A, MMSEL_D
50 write32 CS0BCR_A, CS0BCR_D
52 write32 CS0WCR_A, CS0WCR_D
58 /* set DDR-SDRAM dummy read */
59 write32 MMSEL_A, MMSEL_D
61 write32 MMSEL_A, CS0_A
63 /* set DDR-SDRAM bus/endian etc */
64 write32 MIM_U_A, MIM_U_D
66 write32 MIM_L_A, MIM_L_D0
68 write32 SDR_L_A, SDR_L_A_D0
70 write32 STR_L_A, STR_L_A_D0
72 /* DDR-SDRAM access control */
73 write32 MIM_L_A, MIM_L_D1
75 write32 SCR_L_A, SCR_L_A_D0
77 write32 SCR_L_A, SCR_L_A_D1
79 write32 EMRS_A, EMRS_D
81 write32 MRS1_A, MRS1_D
83 write32 MIM_U_A, MIM_U_D
85 write32 MIM_L_A, MIM_L_A_D2
87 write32 SCR_L_A, SCR_L_A_D2
89 write32 SCR_L_A, SCR_L_A_D2
91 write32 MRS2_A, MRS2_D
97 write16 PSEL0_A, PSEL0_D
99 write16 PSEL1_A, PSEL1_D
101 write16 PSEL2_A, PSEL2_D
103 write16 PSEL3_A, PSEL3_D
105 write16 PSEL4_A, PSEL4_D
107 write8 PADR_A, PADR_D
109 write16 PACR_A, PACR_D
111 write8 PBDR_A, PBDR_D
113 write16 PBCR_A, PBCR_D
115 write8 PCDR_A, PCDR_D
117 write16 PCCR_A, PCCR_D
119 write8 PDDR_A, PDDR_D
121 write16 PDCR_A, PDCR_D
123 write16 PECR_A, PECR_D
125 write16 PFCR_A, PFCR_D
127 write16 PGCR_A, PGCR_D
129 write16 PHCR_A, PHCR_D
131 write16 PICR_A, PICR_D
133 write8 PJDR_A, PJDR_D
135 write16 PJCR_A, PJCR_D
140 write8 PKDR_A, PKDR_D
142 write16 PKCR_A, PKCR_D
144 write16 PLCR_A, PLCR_D
146 write16 PMCR_A, PMCR_D
148 write16 PNCR_A, PNCR_D
150 write16 POCR_A, POCR_D
154 write32 ICR0_A, ICR0_D
156 write32 ICR1_A, ICR1_D
159 write32 USB_USBHSC_A, USB_USBHSC_D
161 write32 CCR_A, CCR_CACHE_D_2
168 /* GPIO Crontrol Register */
169 PACR_A: .long 0xFFEF0000
170 PBCR_A: .long 0xFFEF0002
171 PCCR_A: .long 0xFFEF0004
172 PDCR_A: .long 0xFFEF0006
173 PECR_A: .long 0xFFEF0008
174 PFCR_A: .long 0xFFEF000A
175 PGCR_A: .long 0xFFEF000C
176 PHCR_A: .long 0xFFEF000E
177 PICR_A: .long 0xFFEF0010
178 PJCR_A: .long 0xFFEF0012
179 PKCR_A: .long 0xFFEF0014
180 PLCR_A: .long 0xFFEF0016
181 PMCR_A: .long 0xFFEF0018
182 PNCR_A: .long 0xFFEF001A
183 POCR_A: .long 0xFFEF001C
185 /* GPIO Data Register */
186 PADR_A: .long 0xFFEF0020
187 PBDR_A: .long 0xFFEF0022
188 PCDR_A: .long 0xFFEF0024
189 PDDR_A: .long 0xFFEF0026
190 PJDR_A: .long 0xFFEF0032
191 PKDR_A: .long 0xFFEF0034
194 PADR_D: .long 0x00000000
197 PBDR_D: .long 0x00000000
200 PCDR_D: .long 0x00000000
203 PDDR_D: .long 0x00000000
210 PJDR_D: .long 0x00000006
213 PKDR_D: .long 0x00000000
222 PSEL0_A: .long 0xFFEF0070
223 PSEL1_A: .long 0xFFEF0072
224 PSEL2_A: .long 0xFFEF0074
225 PSEL3_A: .long 0xFFEF0076
226 PSEL4_A: .long 0xFFEF0078
227 PSEL0_D: .word 0x0001
228 PSEL1_D: .word 0x2400
229 PSEL2_D: .word 0x0000
230 PSEL3_D: .word 0x2421
231 PSEL4_D: .word 0x0000
234 MMSEL_A: .long 0xFE600020
235 BCR_A: .long 0xFF801000
236 CS0BCR_A: .long 0xFF802000
237 CS0WCR_A: .long 0xFF802008
238 ICR0_A: .long 0xFFD00000
239 ICR1_A: .long 0xFFD0001C
241 MMSEL_D: .long 0xA5A50000
242 BCR_D: .long 0x05000000
243 CS0BCR_D: .long 0x232306F0
244 CS0WCR_D: .long 0x00011104
245 ICR0_D: .long 0x80C00000
246 ICR1_D: .long 0x00020000
249 WDTST_A: .long 0xFFCC0000
250 WDTCSR_A: .long 0xFFCC0004
251 WDTBST_A: .long 0xFFCC0008
253 WDTST_D: .long 0x5A000FFF
254 WDTCSR_D: .long 0xA5000000
255 WDTBST_D: .long 0x55000000
258 CCR_A: .long 0xFF00001C
259 MMUCR_A: .long 0xFF000010
260 RAMCR_A: .long 0xFF000074
263 CCR_CACHE_ICI_D:.long 0x00000800
264 CCR_CACHE_D_2: .long 0x00000103
265 MMU_CONTROL_TI_D:.long 0x00000004
266 RAMCR_D: .long 0x00000200
268 /* Low power mode control Address */
269 MSTPCR0_A: .long 0xFFC80030
270 MSTPCR1_A: .long 0xFFC80038
271 /* Low power mode control Data */
272 MSTPCR0_D: .long 0x00000000
273 MSTPCR1_D: .long 0x00000000
275 REPEAT0_R3: .long 0x00002000
276 REPEAT_R3: .long 0x00000200
277 CS0_A: .long 0xA8000000
279 MIM_U_A: .long 0xFE800008
280 MIM_L_A: .long 0xFE80000C
281 SCR_U_A: .long 0xFE800010
282 SCR_L_A: .long 0xFE800014
283 STR_U_A: .long 0xFE800018
284 STR_L_A: .long 0xFE80001C
285 SDR_U_A: .long 0xFE800030
286 SDR_L_A: .long 0xFE800034
287 EMRS_A: .long 0xFE902000
288 MRS1_A: .long 0xFE900B08
289 MRS2_A: .long 0xFE900308
291 MIM_U_D: .long 0x00000000
292 MIM_L_D0: .long 0x04100008
293 MIM_L_D1: .long 0x02EE0009
294 MIM_L_D2: .long 0x02EE0209
296 SDR_L_A_D0: .long 0x00000300
297 STR_L_A_D0: .long 0x00010040
298 MIM_L_A_D1: .long 0x04100009
299 SCR_L_A_D0: .long 0x00000003
300 SCR_L_A_D1: .long 0x00000002
301 MIM_L_A_D2: .long 0x04100209
302 SCR_L_A_D2: .long 0x00000004
304 SCR_L_NORMAL: .long 0x00000000
305 SCR_L_NOP: .long 0x00000001
306 SCR_L_PALL: .long 0x00000002
307 SCR_L_CKE_EN: .long 0x00000003
308 SCR_L_CBR: .long 0x00000004
310 STR_L_D: .long 0x000F3980
311 SDR_L_D: .long 0x00000400
312 EMRS_D: .long 0x00000000
313 MRS1_D: .long 0x00000000
314 MRS2_D: .long 0x00000000
317 USB_USBHSC_A: .long 0xFFEC80F0
318 USB_USBHSC_D: .long 0x00000000