2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
7 * (C) Copyright 2009-2011
8 * Eric Benard <eric@eukrea.com>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/at91sam9260.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_matrix.h>
19 #include <asm/arch/at91_pmc.h>
20 #include <asm/arch/at91_rstc.h>
21 #include <asm/arch/at91_pio.h>
22 #include <asm/arch/clk.h>
23 #include <asm/arch/hardware.h>
24 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
29 DECLARE_GLOBAL_DATA_PTR;
31 /* ------------------------------------------------------------------------- */
33 * Miscelaneous platform dependent initialisations
36 #ifdef CONFIG_CMD_NAND
37 static void cpu9260_nand_hw_init(void)
40 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
41 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
42 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
45 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
46 writel(csa, &matrix->csa);
48 /* Configure SMC CS3 for NAND/SmartMedia */
49 #if defined(CONFIG_CPU9G20)
50 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
51 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
53 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
54 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
56 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
59 AT91_SMC_MODE_EXNW_DISABLE |
61 AT91_SMC_MODE_TDF_CYCLE(3),
63 #elif defined(CONFIG_CPU9260)
64 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
65 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
67 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
68 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
70 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
72 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
73 AT91_SMC_MODE_EXNW_DISABLE |
75 AT91_SMC_MODE_TDF_CYCLE(2),
79 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
81 /* Configure RDY/BSY */
82 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
84 /* Enable NandFlash */
85 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
90 static void cpu9260_macb_hw_init(void)
93 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
94 at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
97 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
99 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
101 rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
103 /* Need to reset PHY -> 500ms reset */
104 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
105 AT91_RSTC_MR_URSTEN, &rstc->mr);
107 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
109 /* Wait for end hardware reset */
110 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
113 /* Restore NRST value */
114 writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
120 int board_early_init_f(void)
122 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
124 writel((1 << ATMEL_ID_PIOA) |
125 (1 << ATMEL_ID_PIOB) |
126 (1 << ATMEL_ID_PIOC),
129 at91_seriald_hw_init();
137 /* arch number of the board */
138 #if defined(CONFIG_CPU9G20)
139 gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
140 #elif defined(CONFIG_CPU9260)
141 gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
144 /* adress of boot parameters */
145 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
147 #ifdef CONFIG_CMD_NAND
148 cpu9260_nand_hw_init();
151 cpu9260_macb_hw_init();
153 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
154 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
161 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
162 CONFIG_SYS_SDRAM_SIZE);
166 int board_eth_init(bd_t *bis)
170 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);