git.sur5r.net Git - u-boot/blob - board/eukrea/cpu9260/cpu9260.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * (C) Copyright 2009-2011
   8  * Eric Benard <eric@eukrea.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/at91sam9260.h>
  16 #include <asm/arch/at91sam9_smc.h>
  17 #include <asm/arch/at91_common.h>
  18 #include <asm/arch/at91_matrix.h>
  19 #include <asm/arch/at91_pmc.h>
  20 #include <asm/arch/at91_pio.h>
  21 #include <asm/arch/clk.h>
  22 #include <asm/arch/hardware.h>
  23 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  24 #include <net.h>
  25 #endif
  26 #include <netdev.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34
  35 #ifdef CONFIG_CMD_NAND
  36 static void cpu9260_nand_hw_init(void)
  37 {
  38         unsigned long csa;
  39         at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
  40         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  41         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  42
  43         /* Enable CS3 */
  44         csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
  45         writel(csa, &matrix->csa);
  46
  47         /* Configure SMC CS3 for NAND/SmartMedia */
  48 #if defined(CONFIG_CPU9G20)
  49         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  50                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  51                 &smc->cs[3].setup);
  52         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
  53                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  54                 &smc->cs[3].pulse);
  55         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  56                 &smc->cs[3].cycle);
  57         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  58                 AT91_SMC_MODE_EXNW_DISABLE |
  59                 AT91_SMC_MODE_DBW_8 |
  60                 AT91_SMC_MODE_TDF_CYCLE(3),
  61                 &smc->cs[3].mode);
  62 #elif defined(CONFIG_CPU9260)
  63         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  64                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  65                 &smc->cs[3].setup);
  66         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  67                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  68                 &smc->cs[3].pulse);
  69         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  70                 &smc->cs[3].cycle);
  71         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  72                 AT91_SMC_MODE_EXNW_DISABLE |
  73                 AT91_SMC_MODE_DBW_8 |
  74                 AT91_SMC_MODE_TDF_CYCLE(2),
  75                 &smc->cs[3].mode);
  76 #endif
  77
  78         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  79
  80         /* Configure RDY/BSY */
  81         at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  82
  83         /* Enable NandFlash */
  84         at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  85 }
  86 #endif
  87
  88 #ifdef CONFIG_MACB
  89 static void cpu9260_macb_hw_init(void)
  90 {
  91         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  92
  93         /* Enable clock */
  94         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  95
  96         at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
  97
  98         at91_phy_reset();
  99
 100         at91_macb_hw_init();
 101 }
 102 #endif
 103
 104 int board_early_init_f(void)
 105 {
 106         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 107
 108         writel((1 << ATMEL_ID_PIOA) |
 109                 (1 << ATMEL_ID_PIOB) |
 110                 (1 << ATMEL_ID_PIOC),
 111                 &pmc->pcer);
 112
 113         at91_seriald_hw_init();
 114
 115         return 0;
 116 }
 117
 118
 119 int board_init(void)
 120 {
 121         /* arch number of the board */
 122 #if defined(CONFIG_CPU9G20)
 123         gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
 124 #elif defined(CONFIG_CPU9260)
 125         gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
 126 #endif
 127
 128         /* adress of boot parameters */
 129         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 130
 131 #ifdef CONFIG_CMD_NAND
 132         cpu9260_nand_hw_init();
 133 #endif
 134 #ifdef CONFIG_MACB
 135         cpu9260_macb_hw_init();
 136 #endif
 137 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
 138         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
 139 #endif
 140         return 0;
 141 }
 142
 143 int dram_init(void)
 144 {
 145         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 146                         CONFIG_SYS_SDRAM_SIZE);
 147         return 0;
 148 }
 149
 150 int board_eth_init(bd_t *bis)
 151 {
 152         int rc = 0;
 153 #ifdef CONFIG_MACB
 154         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);
 155 #endif
 156         return rc;
 157 }