3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* sdram_init.c - automatic memory sizing */
12 #include <galileo/memory.h>
13 #include <galileo/pci.h>
14 #include <galileo/gt64260R.h>
16 #include <linux/compiler.h>
23 DECLARE_GLOBAL_DATA_PTR;
36 /* structure to store the relevant information about an sdram bank */
37 typedef struct sdram_info {
39 uchar registered, ecc;
44 int size; /* detected size, not from I2C but from dram_size() */
48 void dump_dimm_info (struct sdram_info *d)
50 static const char *ecc_legend[] = { "", " Parity", " ECC" };
52 printf ("dimm%s %sDRAM: %dMibytes:\n",
54 d->registered ? "R" : "", (d->size >> 20));
55 printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
56 d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
62 memory_map_bank (unsigned int bankNo,
63 unsigned int bankBase, unsigned int bankLength)
67 printf ("mapping bank %d at %08x - %08x\n",
68 bankNo, bankBase, bankBase + bankLength - 1);
70 printf ("unmapping bank %d\n", bankNo);
74 memoryMapBank (bankNo, bankBase, bankLength);
81 memory_map_bank_pci (unsigned int bankNo,
82 unsigned int bankBase, unsigned int bankLength)
86 for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
91 READ_LINE_AGGRESSIVE_PREFETCH |
92 READ_MULTI_AGGRESSIVE_PREFETCH |
93 MAX_BURST_4 | PCI_NO_SWAP;
95 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
97 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
100 pciSetRegionFeatures (host, bankNo, features, bankBase,
107 /* ------------------------------------------------------------------------- */
109 /* much of this code is based on (or is) the code in the pip405 port */
110 /* thanks go to the authors of said port - Josh */
114 * translate ns.ns/10 coding of SPD timing values
115 * into 10 ps unit values
117 static inline unsigned short NS10to10PS (unsigned char spd_byte)
119 unsigned short ns, ns10;
121 /* isolate upper nibble */
122 ns = (spd_byte >> 4) & 0x0F;
123 /* isolate lower nibble */
124 ns10 = (spd_byte & 0x0F);
126 return (ns * 100 + ns10 * 10);
130 * translate ns coding of SPD timing values
131 * into 10 ps unit values
133 static inline unsigned short NSto10PS (unsigned char spd_byte)
135 return (spd_byte * 100);
138 #ifdef CONFIG_ZUMA_V2
139 static int check_dimm (uchar slot, sdram_info_t * info)
141 /* assume 2 dimms, 2 banks each 256M - we dont have an
142 * dimm i2c so rely on the detection routines later */
144 memset (info, 0, sizeof (*info));
147 info->banks = 2; /* Detect later */
148 info->registered = 0;
149 info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
150 but doesn't matter, both do same
151 thing in setup_sdram() */
153 info->tras_clocks = 5;
156 info->ecc = 0; /* Detect later */
157 #endif /* CONFIG_ECC */
161 #elif defined(CONFIG_P3G4)
163 static int check_dimm (uchar slot, sdram_info_t * info)
165 memset (info, 0, sizeof (*info));
172 info->registered = 0;
175 info->tras_clocks = 6;
183 #else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
185 /* This code reads the SPD chip on the sdram and populates
186 * the array which is passed in with the relevant information */
187 static int check_dimm (uchar slot, sdram_info_t * info)
189 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
191 uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
193 uchar trp_clocks, trcd_clocks;
198 tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
200 #ifdef CONFIG_EVB64260_750CX
202 printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
203 printf (" called with slot=%d insetad!\n", slot);
207 DP (puts ("before i2c read\n"));
209 ret = i2c_read (addr, 0, 128, data, 0);
211 DP (puts ("after i2c read\n"));
213 /* zero all the values */
214 memset (info, 0, sizeof (*info));
217 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
221 /* first, do some sanity checks */
222 if (data[2] != 0x4) {
223 printf ("Not SDRAM in slot %d\n", slot);
227 /* get various information */
230 info->banks = data[5];
231 sdram_banks = data[17];
232 width = data[13] & 0x7f;
235 ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
237 /* check if the memory is registered */
238 if (data[21] & (BIT1 | BIT4))
239 info->registered = 1;
242 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
243 info->ecc = (data[11] & 2) >> 1;
246 /* bit 1 is CL2, bit 2 is CL3 */
247 supp_cal = (data[18] & 0x6) >> 1;
249 /* compute the relevant clock values */
250 trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
251 trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
252 info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
254 DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
255 trp_clocks, trcd_clocks, info->tras_clocks));
257 /* try a CAS latency of 3 first... */
260 if (NS10to10PS (data[9]) <= tmemclk)
266 if (NS10to10PS (data[23]) <= tmemclk)
270 DP (printf ("cal_val = %d\n", cal_val));
272 /* bummer, did't work... */
274 DP (printf ("Couldn't find a good CAS latency\n"));
278 /* get the largest delay -- these values need to all be the same
280 info->tpar = cal_val;
281 if (trp_clocks > info->tpar)
282 info->tpar = trp_clocks;
283 if (trcd_clocks > info->tpar)
284 info->tpar = trcd_clocks;
286 DP (printf ("tpar set to: %d\n", info->tpar));
288 #ifdef CONFIG_SYS_BROKEN_CL2
289 if (info->tpar == 2) {
291 DP (printf ("tpar fixed-up to: %d\n", info->tpar));
294 /* compute the module DRB size */
296 (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
298 DP (printf ("drb_size set to: %d\n", info->drb_size));
300 /* find the burst len */
301 info->burst_len = data[16] & 0xf;
302 if ((info->burst_len & 8) == 8) {
304 } else if ((info->burst_len & 4) == 4) {
313 #endif /* ! CONFIG_ZUMA_V2 */
315 static int setup_sdram_common (sdram_info_t info[2])
318 int tpar = 2, tras_clocks = 5, registered = 1;
319 __maybe_unused int ecc = 2;
321 if (!info[0].banks && !info[1].banks)
325 if (info[0].tpar > tpar)
327 if (info[0].tras_clocks > tras_clocks)
328 tras_clocks = info[0].tras_clocks;
329 if (!info[0].registered)
331 if (info[0].ecc != 2)
336 if (info[1].tpar > tpar)
338 if (info[1].tras_clocks > tras_clocks)
339 tras_clocks = info[1].tras_clocks;
340 if (!info[1].registered)
342 if (info[1].ecc != 2)
346 /* SDRAM configuration */
347 tmp = GTREGREAD (SDRAM_CONFIGURATION);
349 /* Turn on physical interleave if both DIMMs
350 * have even numbers of banks. */
351 if ((info[0].banks == 0 || info[0].banks == 2) &&
352 (info[1].banks == 0 || info[1].banks == 2)) {
353 /* physical interleave on */
356 /* physical interleave off */
360 tmp |= (registered << 17);
362 /* Use buffer 1 to return read data to the CPU
366 GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
367 DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
370 tmp = (((tpar == 3) ? 2 : 1) |
371 (((tpar == 3) ? 2 : 1) << 2) |
372 (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
378 #endif /* CONFIG_ECC */
380 GT_REG_WRITE (SDRAM_TIMING, tmp);
381 DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
382 GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
384 /* SDRAM address decode register */
385 /* program this with the default value */
386 GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
387 DP (printf ("SDRAM decode: %08x\n",
388 GTREGREAD (SDRAM_ADDRESS_DECODE)));
393 /* sets up the GT properly with information passed in */
394 static int setup_sdram (sdram_info_t * info)
398 __maybe_unused ulong check;
401 /* sanity checking */
405 /* ---------------------------- */
406 /* Program the GT with the discovered data */
408 /* bank parameters */
409 tmp = (0xf << 16); /* leave all virt bank pages open */
411 DP (printf ("drb_size: %d\n", info->drb_size));
412 switch (info->drb_size) {
425 printf ("Error in dram size calculation\n");
429 /* SDRAM bank parameters */
430 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
431 GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
432 GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
434 ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
435 info->slot * 2, (info->slot * 2) + 1, tmp));
437 /* set the SDRAM configuration for each bank */
438 for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
439 DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
442 memory_map_bank (i, 0, GB / 4);
445 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
446 check = GTREGREAD (SDRAM_OPERATION_MODE);
451 /* wait for the command to complete */
452 while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
454 /* switch back to normal operation mode */
455 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
456 check = GTREGREAD (SDRAM_OPERATION_MODE);
459 memory_map_bank (i, 0, 0);
460 DP (printf ("*** MRS cycle for bank %d done ***\n", i));
467 * Check memory range for valid RAM. A simple memory test determines
468 * the actually available RAM size between addresses `base' and
469 * `base + maxsize'. Some (not all) hardware errors are detected:
470 * - short between address lines
471 * - short between data lines
473 static long int dram_size (long int *base, long int maxsize)
475 volatile long int *addr, *b = base;
476 long int cnt, val, save1, save2;
478 #define STARTVAL (1<<20) /* start test at 1M */
479 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
481 addr = base + cnt; /* pointer arith! */
483 save1 = *addr; /* save contents of addr */
484 save2 = *b; /* save contents of base */
486 *addr = cnt; /* write cnt to addr */
487 *b = 0; /* put null at base */
489 /* check at base address */
491 *addr = save1; /* restore *addr */
492 *b = save2; /* restore *b */
495 val = *addr; /* read *addr */
501 /* fix boundary condition.. STARTVAL means zero */
502 if (cnt == STARTVAL / sizeof (long))
504 return (cnt * sizeof (long));
510 /* ------------------------------------------------------------------------- */
512 /* U-Boot interface function to SDRAM init - this is where all the
513 * controlling logic happens */
514 phys_size_t initdram (int board_type)
516 ulong checkbank[4] = {[0 ... 3] = 0 };
520 sdram_info_t dimm_info[2];
523 /* first, use the SPD to get info about the SDRAM */
525 /* check the NHR bit and skip mem init if it's already done */
526 nhr = get_hid0 () & (1 << 16);
529 printf ("Skipping SDRAM setup due to NHR bit being set\n");
532 check_dimm (0, &dimm_info[0]);
535 #ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
536 check_dimm (1, &dimm_info[1]);
537 #else /* CONFIG_EVB64260_750CX */
538 memset (&dimm_info[1], 0, sizeof (sdram_info_t));
541 /* unmap all banks */
542 memory_map_bank (0, 0, 0);
543 memory_map_bank (1, 0, 0);
544 memory_map_bank (2, 0, 0);
545 memory_map_bank (3, 0, 0);
547 /* Now, program the GT with the correct values */
548 if (setup_sdram_common (dimm_info)) {
549 printf ("Setup common failed.\n");
552 if (setup_sdram (&dimm_info[0])) {
553 printf ("Setup for DIMM1 failed.\n");
556 if (setup_sdram (&dimm_info[1])) {
557 printf ("Setup for DIMM2 failed.\n");
560 /* set the NHR bit */
561 set_hid0 (get_hid0 () | (1 << 16));
563 /* next, size the SDRAM banks */
566 if (dimm_info[0].banks > 0)
568 if (dimm_info[0].banks > 1)
570 if (dimm_info[0].banks > 2)
571 printf ("Error, SPD claims DIMM1 has >2 banks\n");
573 if (dimm_info[1].banks > 0)
575 if (dimm_info[1].banks > 1)
577 if (dimm_info[1].banks > 2)
578 printf ("Error, SPD claims DIMM2 has >2 banks\n");
580 /* Generic dram sizer: works even if we don't have i2c DIMMs,
581 * as long as the timing settings are more or less correct */
584 * pass 1: size all the banks, using first bat (0-256M)
585 * limitation: we only support 256M per bank due to
586 * us only having 1 BAT for all DRAM
588 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
589 /* skip over banks that are not populated */
590 if (!checkbank[bank_no])
593 DP (printf ("checking bank %d\n", bank_no));
595 memory_map_bank (bank_no, 0, GB / 4);
596 checkbank[bank_no] = dram_size (NULL, GB / 4);
597 memory_map_bank (bank_no, 0, 0);
599 DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
603 * pass 2: contiguously map each bank into physical address
606 dimm_info[0].banks = dimm_info[1].banks = 0;
607 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
608 if (!checkbank[bank_no])
611 dimm_info[bank_no / 2].banks++;
612 dimm_info[bank_no / 2].size += checkbank[bank_no];
614 memory_map_bank (bank_no, total, checkbank[bank_no]);
616 memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
618 total += checkbank[bank_no];
622 #ifdef CONFIG_ZUMA_V2
624 * We always enable ECC when bank 2 and 3 are unpopulated
625 * If we 2 or 3 are populated, we CAN'T support ECC.
626 * (Zuma boards only support ECC in banks 0 and 1; assume that
627 * in that configuration, ECC chips are mounted, even for stacked
630 if (checkbank[2] == 0 && checkbank[3] == 0) {
631 dimm_info[0].ecc = 2;
632 GT_REG_WRITE (SDRAM_TIMING,
633 GTREGREAD (SDRAM_TIMING) | (1 << 13));
634 /* TODO: do we have to run MRS cycles again? */
636 #endif /* CONFIG_ZUMA_V2 */
638 if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
641 #endif /* CONFIG_ECC */
644 dump_dimm_info (&dimm_info[0]);
645 dump_dimm_info (&dimm_info[1]);
647 /* TODO: return at MOST 256M? */
648 /* return total > GB/4 ? GB/4 : total; */