3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* ------------------------------------------------------------------------- */
31 #define _NOT_USED_ 0xFFFFFFFF
33 #if defined(CONFIG_DRAM_50MHZ)
35 const uint dram_60ns[] =
36 { 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
37 0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff,
38 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
39 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
40 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
41 0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff,
42 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
43 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
44 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
45 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
46 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
47 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
48 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
49 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
50 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
51 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
53 const uint dram_70ns[] =
54 { 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
55 0x00ffcc00, 0x37ffcc47, 0xffffffff, 0xffffffff,
56 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
57 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
58 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
59 0x00ffec00, 0x3fffec47, 0xffffffff, 0xffffffff,
60 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
61 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
62 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
63 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
64 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
65 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
66 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
67 0x7fffcc06, 0xffffcc85, 0xffffcc05, 0xffffffff,
68 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
69 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
71 const uint edo_60ns[] =
72 { 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
73 0x00f3ec00, 0x37f7ec47, 0xffffffff, 0xffffffff,
74 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
75 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
76 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
77 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
78 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
79 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
80 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
81 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
82 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
83 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
84 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
85 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
86 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
87 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
89 const uint edo_70ns[] =
90 { 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
91 0x00f3cc00, 0x37f7cc47, 0xffffffff, 0xffffffff,
92 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
93 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
94 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
95 0x33f7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
96 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
97 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
98 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
99 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
100 0x0cafcc00, 0x33bfcc47, 0xffffffff, 0xffffffff,
101 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
102 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
103 0x7fffcc04, 0xffffcc86, 0xffffcc05, 0xffffffff,
104 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
105 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
107 #elif defined(CONFIG_DRAM_25MHZ)
111 const uint dram_60ns[] =
112 { 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, 0xffffffff,
113 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
114 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
115 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
116 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
117 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
118 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
119 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
120 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
121 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
122 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
123 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
124 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
125 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
126 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
127 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
129 const uint dram_70ns[] =
130 { 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
131 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
132 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
133 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
134 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
135 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
136 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
137 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
138 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
139 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
140 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
141 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
142 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
143 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
144 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
145 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
147 const uint edo_60ns[] =
148 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
149 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
150 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
151 0x08f3cc00, 0x3ff7cc47, 0xffffffff, 0xffffffff,
152 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
153 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
154 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
155 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
156 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
157 0x08afcc48, 0x39bfcc47, 0xffffffff, 0xffffffff,
158 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
159 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
160 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
161 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
162 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
163 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
165 const uint edo_70ns[] =
166 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
167 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
168 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
169 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
170 0x3ff7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
171 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
172 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
173 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
174 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
175 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
176 0x37bfcc47, 0xffffffff, 0xffffffff, 0xffffffff,
177 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
178 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
179 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
180 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
181 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
185 #error dram not correct defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
188 /* ------------------------------------------------------------------------- */
192 * Check Board Identity:
195 int checkboard (void)
202 k = (*((uint *)BCSR3) >> 24) & 0x3f;
216 printf("unknown board (0x%02x)\n", k);
233 puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
248 k = (((*((uint *)BCSR3) >> 23) & 1) << 3)
249 | (((*((uint *)BCSR3) >> 19) & 1) << 2)
250 | (((*((uint *)BCSR3) >> 16) & 3));
254 puts ("ENG or PILOT\n");
258 printf("unknown (0x%x)\n", k);
263 #endif /* CONFIG_FADS */
268 k = (((*((uint *)BCSR3) >> 23) & 1) << 3)
269 | (((*((uint *)BCSR3) >> 19) & 1) << 2)
270 | (((*((uint *)BCSR3) >> 16) & 3));
273 case 0x00 : puts ("ENG - this board sucks, check the errata, not supported\n");
275 case 0x01 : puts ("PILOT - warning, read errata \n"); break;
276 case 0x02 : puts ("A - warning, read errata \n"); break;
277 case 0x03 : puts ("B \n"); break;
278 default : printf ("unknown revision (0x%x)\n", k); return -1;
282 #endif /* CONFIG_ADS */
286 /* ------------------------------------------------------------------------- */
287 int _draminit(uint base, uint noMbytes, uint edo, uint delay)
289 volatile immap_t *immap = (immap_t *)CFG_IMMR;
290 volatile memctl8xx_t *memctl = &immap->im_memctl;
300 upmconfig(UPMA, (uint *) edo_70ns, sizeof(edo_70ns)/sizeof(uint));
304 upmconfig(UPMA, (uint *) dram_70ns, sizeof(dram_70ns)/sizeof(uint));
314 upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
318 upmconfig(UPMA, (uint *) dram_60ns, sizeof(dram_60ns)/sizeof(uint));
328 memctl->memc_mptpr = 0x0400; /* divide by 16 */
333 case 8: /* 8 Mbyte uses both CS3 and CS2 */
335 memctl->memc_mamr = 0x13a01114;
336 memctl->memc_or3 = 0xffc00800;
337 memctl->memc_br3 = 0x00400081 + base;
338 memctl->memc_or2 = 0xffc00800;
342 case 4: /* 4 Mbyte uses only CS2 */
344 memctl->memc_mamr = 0x13a01114;
345 memctl->memc_or2 = 0xffc00800;
349 case 32: /* 32 Mbyte uses both CS3 and CS2 */
351 memctl->memc_mamr = 0x13b01114;
352 memctl->memc_or3 = 0xff000800;
353 memctl->memc_br3 = 0x01000081 + base;
354 memctl->memc_or2 = 0xff000800;
358 case 16: /* 16 Mbyte uses only CS2 */
361 memctl->memc_mamr = 0x60b21114;
363 memctl->memc_mamr = 0x13b01114;
365 memctl->memc_or2 = 0xff000800;
373 memctl->memc_br2 = 0x81 + base; /* use upma */
377 /* ------------------------------------------------------------------------- */
379 void _dramdisable(void)
381 volatile immap_t *immap = (immap_t *)CFG_IMMR;
382 volatile memctl8xx_t *memctl = &immap->im_memctl;
384 memctl->memc_br2 = 0x00000000;
385 memctl->memc_br3 = 0x00000000;
387 /* maybe we should turn off upma here or something */
390 #if defined(CONFIG_SDRAM_100MHZ)
392 /* ------------------------------------------------------------------------- */
393 /* sdram table by Dan Malek */
395 /* This has the stretched early timing so the 50 MHz
396 * processor can make the 100 MHz timing. This will
397 * work at all processor speeds.
400 #define SDRAM_MPTPRVALUE 0x0400
402 #define SDRAM_MBMRVALUE0 0xc3802114 /* (16-14) 50 MHz */
403 #define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
405 #define SDRAM_OR4VALUE 0xffc00a00
406 #define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */
408 #define SDRAM_MARVALUE 0x88
410 #define SDRAM_MCRVALUE0 0x80808111 /* run pattern 0x11 */
411 #define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0
414 const uint sdram_table[] =
416 /* single read. (offset 0 in upm RAM) */
417 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
418 0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff,
420 /* burst read. (offset 8 in upm RAM) */
421 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
422 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
423 0x1ff77c45, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
424 0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,
426 /* single write. (offset 18 in upm RAM) */
427 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
428 0x1ff77c45, 0xffffffff, 0xffffffff, 0xffffffff,
430 /* burst write. (offset 20 in upm RAM) */
431 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
432 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
433 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
434 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
436 /* refresh. (offset 30 in upm RAM) */
437 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
438 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
439 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
441 /* exception. (offset 3c in upm RAM) */
442 0xeffffc06, 0x1ffffc07, 0xffffffff, 0xffffffff };
444 #elif defined(CONFIG_SDRAM_50MHZ)
446 /* ------------------------------------------------------------------------- */
447 /* sdram table stolen from the fads manual */
448 /* for chip MB811171622A-100 */
450 /* this table is for 32-50MHz operation */
452 #define _not_used_ 0xffffffff
454 #define SDRAM_MPTPRVALUE 0x0400
456 #define SDRAM_MBMRVALUE0 0x80802114 /* refresh at 32MHz */
457 #define SDRAM_MBMRVALUE1 0x80802118
459 #define SDRAM_OR4VALUE 0xffc00a00
460 #define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */
462 #define SDRAM_MARVALUE 0x88
464 #define SDRAM_MCRVALUE0 0x80808105
465 #define SDRAM_MCRVALUE1 0x80808130
467 const uint sdram_table[] =
469 /* single read. (offset 0 in upm RAM) */
470 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
473 /* MRS initialization (offset 5) */
475 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
477 /* burst read. (offset 8 in upm RAM) */
478 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
479 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
480 _not_used_, _not_used_, _not_used_, _not_used_,
481 _not_used_, _not_used_, _not_used_, _not_used_,
483 /* single write. (offset 18 in upm RAM) */
484 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
485 _not_used_, _not_used_, _not_used_, _not_used_,
487 /* burst write. (offset 20 in upm RAM) */
488 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
489 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
490 _not_used_, _not_used_, _not_used_, _not_used_,
491 _not_used_, _not_used_, _not_used_, _not_used_,
493 /* refresh. (offset 30 in upm RAM) */
494 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
495 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
496 _not_used_, _not_used_, _not_used_, _not_used_,
498 /* exception. (offset 3c in upm RAM) */
499 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
501 /* ------------------------------------------------------------------------- */
503 #error SDRAM not correctly configured
506 int _initsdram(uint base, uint noMbytes)
508 volatile immap_t *immap = (immap_t *)CFG_IMMR;
509 volatile memctl8xx_t *memctl = &immap->im_memctl;
516 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
518 memctl->memc_mptpr = SDRAM_MPTPRVALUE;
520 /* Configure the refresh (mostly). This needs to be
521 * based upon processor clock speed and optimized to provide
522 * the highest level of performance. For multiple banks,
523 * this time has to be divided by the number of banks.
524 * Although it is not clear anywhere, it appears the
525 * refresh steps through the chip selects for this UPM
526 * on each refresh cycle.
527 * We have to be careful changing
528 * UPM registers after we ask it to run these commands.
531 memctl->memc_mbmr = SDRAM_MBMRVALUE0;
532 memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */
536 /* Now run the precharge/nop/mrs commands.
539 memctl->memc_mcr = 0x80808111; /* run pattern 0x11 */
543 /* Run 8 refresh cycles */
545 memctl->memc_mcr = SDRAM_MCRVALUE0;
549 memctl->memc_mbmr = SDRAM_MBMRVALUE1;
550 memctl->memc_mcr = SDRAM_MCRVALUE1;
554 memctl->memc_mbmr = SDRAM_MBMRVALUE0;
556 memctl->memc_or4 = SDRAM_OR4VALUE;
557 memctl->memc_br4 = SDRAM_BR4VALUE | base;
562 /* ------------------------------------------------------------------------- */
564 void _sdramdisable(void)
566 volatile immap_t *immap = (immap_t *)CFG_IMMR;
567 volatile memctl8xx_t *memctl = &immap->im_memctl;
569 memctl->memc_br4 = 0x00000000;
571 /* maybe we should turn off upmb here or something */
574 /* ------------------------------------------------------------------------- */
576 int initsdram(uint base, uint *noMbytes)
580 *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
581 /* _fads_sdraminit needs access to sdram */
584 if(!_initsdram(base, m))
591 *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
599 long int initdram (int board_type)
602 /* ADS: has no SDRAM, so start DRAM at 0 */
603 uint base = (unsigned long)0x0;
605 /* FADS: has 4MB SDRAM, put DRAM above it */
606 uint base = (unsigned long)0x00400000;
610 k = (*((uint *)BCSR2) >> 23) & 0x0f;
616 /* "MCM36100 / MT8D132X" */
621 /* "MCM36800 / MT16D832X" */
625 /* "MCM36400 / MT8D432X" */
629 /* "MCM36200 / MT16D832X ?" */
647 printf("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
652 /* the FADS is missing this bit, all rams treated as non-edo */
655 s = (*((uint *)BCSR2) >> 27) & 0x01;
658 if(!_draminit(base, m, s, k))
663 *((uint *)BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
666 if (!initsdram(0x00000000, &sdramsz)) {
668 printf("(%u MB SDRAM) ", sdramsz);
672 /********************************
673 *DRAM ERROR, HALT PROCESSOR
674 *********************************/
687 /********************************
688 *DRAM ERROR, HALT PROCESSOR
689 *********************************/
696 /* ------------------------------------------------------------------------- */
700 /* TODO: XXX XXX XXX */
701 printf ("test: 16 MB - ok\n");
707 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
709 #ifdef CFG_PCMCIA_MEM_ADDR
710 volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
713 int pcmcia_init(void)
715 volatile pcmconf8xx_t *pcmp;
716 uint v, slota, slotb;
719 ** Enable the PCMCIA for a Flash card.
721 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
724 pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
725 pcmp->pcmc_por0 = 0xc00ff05d;
728 /* Set all slots to zero by default. */
729 pcmp->pcmc_pgcra = 0;
730 pcmp->pcmc_pgcrb = 0;
732 pcmp->pcmc_pgcra = 0x40;
735 pcmp->pcmc_pgcrb = 0x40;
738 /* enable PCMCIA buffers */
739 *((uint *)BCSR1) &= ~BCSR1_PCCEN;
741 /* Check if any PCMCIA card is plugged in. */
743 slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
744 slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
746 if (!(slota || slotb))
748 printf("No card present\n");
750 pcmp->pcmc_pgcra = 0;
753 pcmp->pcmc_pgcrb = 0;
758 printf("Card present (");
762 /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
764 ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
768 #if defined(CONFIG_MPC860)
769 switch( (pcmp->pcmc_pipr >> 30) & 3 )
770 #elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
771 switch( (pcmp->pcmc_pipr >> 14) & 3 )
781 v = 3; /* User lower voltage if supported! */
787 printf("5V, 3V and x.xV");
789 v = 3; /* User lower voltage if supported! */
799 printf("; using 3V");
801 ** Enable 3 volt Vcc.
803 *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
804 *((uint *)BCSR1) |= BCSR1_PCCVCC0;
808 printf("; using 5V");
811 ** Enable 5 volt Vcc.
813 *((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
817 ** Enable 5 volt Vcc.
819 *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
820 *((uint *)BCSR1) |= BCSR1_PCCVCC1;
825 *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */
827 printf("; unknown voltage");
831 /* disable pcmcia reset after a while */
836 pcmp->pcmc_pgcra = 0;
838 pcmp->pcmc_pgcrb = 0;
841 /* If you using a real hd you should give a short
843 #ifdef CONFIG_DISK_SPINUP_TIME
844 udelay(CONFIG_DISK_SPINUP_TIME);
850 #endif /* CFG_CMD_PCMCIA */
852 /* ------------------------------------------------------------------------- */
854 #ifdef CFG_PC_IDE_RESET
856 void ide_set_reset(int on)
858 volatile immap_t *immr = (immap_t *)CFG_IMMR;
861 * Configure PC for IDE Reset Pin
863 if (on) { /* assert RESET */
864 immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
865 } else { /* release RESET */
866 immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
869 /* program port pin as GPIO output */
870 immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
871 immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
872 immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
875 #endif /* CFG_PC_IDE_RESET */
876 /* ------------------------------------------------------------------------- */