2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
10 * This header file contains values common to all FADS family boards.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /****************************************************************************
32 * Flash Memory Map as used by U-Boot:
34 * Start Address Length
35 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
36 * | | 0xFE00_0100 Reset Vector
40 * +-----------------------+ 0xFE04_0000 (sector border)
43 * | U-Boot environment |
46 * +=======================+ 0xFE08_0000 (sector border) -----------------
47 * | Available | | Applications
50 *****************************************************************************/
53 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
58 #undef CONFIG_BOOTARGS
59 #define CONFIG_BOOTCOMMAND \
61 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
65 #undef CONFIG_WATCHDOG /* watchdog disabled */
66 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
69 * New MPC86xADS and Duet provide two Ethernet connectivity options:
70 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
71 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
72 * got FEC so FEC is the default.
75 #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
76 #define CONFIG_FEC_ENET /* Use FEC ethernet */
77 #else /* Old ADS has not got FEC option */
78 #define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
79 #undef CONFIG_FEC_ENET /* No FEC ethernet */
80 #endif /* !CONFIG_ADS */
82 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
83 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
86 #ifdef CONFIG_FEC_ENET
87 #define CFG_DISCOVER_PHY
90 #ifndef CONFIG_COMMANDS
91 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
99 #endif /* !CONFIG_COMMANDS */
101 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
102 #include <cmd_confdefs.h>
105 * Miscellaneous configurable options
107 #undef CFG_LONGHELP /* undef to save memory */
108 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
109 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
110 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
112 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
114 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
115 #define CFG_MAXARGS 16 /* max number of command args */
116 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
118 #define CFG_LOAD_ADDR 0x00100000
120 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
122 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
125 * Low Level Configuration Settings
126 * (address mappings, register initial values, etc.)
127 * You should know what you are doing if you make changes here.
129 /*-----------------------------------------------------------------------
130 * Internal Memory Mapped Register
132 #define CFG_IMMR 0xFF000000
134 /*-----------------------------------------------------------------------
135 * Definitions for initial stack pointer and data area (in DPRAM)
137 #define CFG_INIT_RAM_ADDR CFG_IMMR
138 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
139 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
140 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
141 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
143 /*-----------------------------------------------------------------------
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
146 * Please note that CFG_SDRAM_BASE _must_ start at 0
148 #define CFG_SDRAM_BASE 0x00000000
149 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
150 #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
151 #elif defined(CONFIG_FADS) /* Old/new FADS */
152 #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
154 #define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
157 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
159 #define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
161 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
162 #endif /* CFG_SDRAM_SIZE */
165 * For booting Linux, the board info and command line data
166 * have to be in the first 8 MB of memory, since this is
167 * the maximum mapped by the Linux kernel during initialization.
169 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
171 #define CFG_MONITOR_BASE TEXT_BASE
172 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
175 #define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
177 #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
178 #endif /* CONFIG_BZIP2 */
180 /*-----------------------------------------------------------------------
183 #define CFG_FLASH_BASE CFG_MONITOR_BASE
184 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
186 #define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
187 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
189 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
190 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
192 #define CFG_ENV_IS_IN_FLASH 1
193 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
194 #define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
195 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
197 #define CFG_DIRECT_FLASH_TFTP
199 #if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
205 /* No command line, one static partition, whole device */
206 #undef CONFIG_JFFS2_CMDLINE
207 #define CONFIG_JFFS2_DEV "nor0"
208 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
209 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
211 /* mtdparts command line support */
212 /* Note: fake mtd_id used, no linux mtd map file */
214 #define CONFIG_JFFS2_CMDLINE
215 #define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
216 #define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
219 #define CFG_JFFS2_SORT_FRAGMENTS
220 #endif /* CFG_CMD_JFFS2 */
222 /*-----------------------------------------------------------------------
223 * Cache Configuration
225 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
226 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
227 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
230 /*-----------------------------------------------------------------------
233 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
234 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
235 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
236 #define CFG_I2C_SLAVE 0x7F
239 /*-----------------------------------------------------------------------
240 * SYPCR - System Protection Control 11-9
241 * SYPCR can only be written once after reset!
242 *-----------------------------------------------------------------------
243 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
245 #if defined(CONFIG_WATCHDOG)
246 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
247 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
249 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
252 /*-----------------------------------------------------------------------
253 * SIUMCR - SIU Module Configuration 11-6
254 *-----------------------------------------------------------------------
255 * PCMCIA config., multi-function pin tri-state
257 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
259 /*-----------------------------------------------------------------------
260 * TBSCR - Time Base Status and Control 11-26
261 *-----------------------------------------------------------------------
262 * Clear Reference Interrupt Status, Timebase freezing enabled
264 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
266 /*-----------------------------------------------------------------------
267 * PISCR - Periodic Interrupt Status and Control 11-31
268 *-----------------------------------------------------------------------
269 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
271 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
273 /*-----------------------------------------------------------------------
274 * SCCR - System Clock and reset Control Register 15-27
275 *-----------------------------------------------------------------------
276 * Set clock output, timebase and RTC source and divider,
277 * power management and some other internal clocks
279 #define SCCR_MASK SCCR_EBDF11
280 #define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
282 /*-----------------------------------------------------------------------
283 * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
284 *-----------------------------------------------------------------------
285 * set the PLL, the low-power modes and the reset control
288 #define CFG_PLPRCR PLPRCR_TEXPS
291 /*-----------------------------------------------------------------------
293 *-----------------------------------------------------------------------
298 /* Because of the way the 860 starts up and assigns CS0 the
299 * entire address space, we have to set the memory controller
300 * differently. Normally, you write the option register
301 * first, and then enable the chip select by writing the
302 * base register. For CS0, you must write the base register
303 * first, followed by the option register.
307 * Init Memory Controller:
312 /* the other CS:s are determined by looking at parameters in BCSRx */
314 #define BCSR_ADDR ((uint) 0xFF080000)
316 #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
318 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
319 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
321 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
322 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
324 /* BCSRx - Board Control and Status Registers */
325 #define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
326 #define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V)
329 * Internal Definitions
333 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
334 #define BOOTFLAG_WARM 0x02 /* Software reboot */
336 /* values according to the manual */
338 #define PCMCIA_MEM_ADDR ((uint)0xFF020000)
339 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
341 #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
342 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
343 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
344 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
345 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
348 * (F)ADS bitvalues by Helmut Buchsbaum
350 * See User's Manual for a proper
351 * description of the following structures
354 #define BCSR0_ERB ((uint)0x80000000)
355 #define BCSR0_IP ((uint)0x40000000)
356 #define BCSR0_BDIS ((uint)0x10000000)
357 #define BCSR0_BPS_MASK ((uint)0x0C000000)
358 #define BCSR0_ISB_MASK ((uint)0x01800000)
359 #define BCSR0_DBGC_MASK ((uint)0x00600000)
360 #define BCSR0_DBPC_MASK ((uint)0x00180000)
361 #define BCSR0_EBDF_MASK ((uint)0x00060000)
363 #define BCSR1_FLASH_EN ((uint)0x80000000)
364 #define BCSR1_DRAM_EN ((uint)0x40000000)
365 #define BCSR1_ETHEN ((uint)0x20000000)
366 #define BCSR1_IRDEN ((uint)0x10000000)
367 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
368 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
369 #define BCSR1_BCSR_EN ((uint)0x02000000)
370 #define BCSR1_RS232EN_1 ((uint)0x01000000)
371 #define BCSR1_PCCEN ((uint)0x00800000)
372 #define BCSR1_PCCVCC0 ((uint)0x00400000)
373 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
374 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
375 #define BCSR1_RS232EN_2 ((uint)0x00040000)
376 #define BCSR1_SDRAM_EN ((uint)0x00020000)
377 #define BCSR1_PCCVCC1 ((uint)0x00010000)
379 #define BCSR1_PCCVCCON BCSR1_PCCVCC0
381 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
382 #define BCSR2_FLASH_PD_SHIFT 28
383 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
384 #define BCSR2_DRAM_PD_SHIFT 23
385 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
386 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
388 #define BCSR3_DBID_MASK ((ushort)0x3800)
389 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
390 #define BCSR3_BREVNR0 ((ushort)0x0080)
391 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
392 #define BCSR3_BREVN1 ((ushort)0x0008)
393 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
395 #define BCSR4_ETHLOOP ((uint)0x80000000)
396 #define BCSR4_TFPLDL ((uint)0x40000000)
397 #define BCSR4_TPSQEL ((uint)0x20000000)
398 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
399 #define BCSR4_FETH_EN ((uint)0x08000000)
400 #define BCSR4_FETHCFG0 ((uint)0x04000000)
401 #define BCSR4_FETHFDE ((uint)0x02000000)
402 #define BCSR4_FETHCFG1 ((uint)0x00400000)
403 #define BCSR4_FETHRST ((uint)0x00200000)
406 #define BCSR4_USB_EN ((uint)0x08000000)
407 #endif /* CONFIG_MPC823 */
408 #ifdef CONFIG_MPC860SAR
409 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
410 #endif /* CONFIG_MPC860SAR */
411 #ifdef CONFIG_MPC860T
412 #define BCSR4_FETH_EN ((uint)0x08000000)
413 #endif /* CONFIG_MPC860T */
415 #define BCSR4_USB_SPEED ((uint)0x04000000)
416 #endif /* CONFIG_MPC823 */
417 #ifdef CONFIG_MPC860T
418 #define BCSR4_FETHCFG0 ((uint)0x04000000)
419 #endif /* CONFIG_MPC860T */
421 #define BCSR4_VCCO ((uint)0x02000000)
422 #endif /* CONFIG_MPC823 */
423 #ifdef CONFIG_MPC860T
424 #define BCSR4_FETHFDE ((uint)0x02000000)
425 #endif /* CONFIG_MPC860T */
427 #define BCSR4_VIDEO_ON ((uint)0x00800000)
428 #endif /* CONFIG_MPC823 */
430 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
431 #endif /* CONFIG_MPC823 */
432 #ifdef CONFIG_MPC860T
433 #define BCSR4_FETHCFG1 ((uint)0x00400000)
434 #endif /* CONFIG_MPC860T */
436 #define BCSR4_VIDEO_RST ((uint)0x00200000)
437 #endif /* CONFIG_MPC823 */
438 #ifdef CONFIG_MPC860T
439 #define BCSR4_FETHRST ((uint)0x00200000)
440 #endif /* CONFIG_MPC860T */
442 #define BCSR4_MODEM_EN ((uint)0x00100000)
443 #endif /* CONFIG_MPC823 */
445 #define BCSR4_DATA_VOICE ((uint)0x00080000)
446 #endif /* CONFIG_MPC823 */
448 #define BCSR4_DATA_VOICE ((uint)0x00080000)
449 #endif /* CONFIG_MPC850 */
451 /* BSCR5 exists on MPC86xADS and Duet ADS only */
453 #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
455 #define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
457 #define BCSR5_MII2_EN 0x40
458 #define BCSR5_MII2_RST 0x20
459 #define BCSR5_T1_RST 0x10
460 #define BCSR5_ATM155_RST 0x08
461 #define BCSR5_ATM25_RST 0x04
462 #define BCSR5_MII1_EN 0x02
463 #define BCSR5_MII1_RST 0x01
465 /* We don't use the 8259.
467 #define NR_8259_INTS 0
471 #define _MACH_8xx (_MACH_fads)
473 /*-----------------------------------------------------------------------
475 *-----------------------------------------------------------------------
477 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
478 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
479 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
480 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
481 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
482 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
483 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
484 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
486 /*-----------------------------------------------------------------------
488 *-----------------------------------------------------------------------
490 #define CONFIG_MAC_PARTITION 1
491 #define CONFIG_DOS_PARTITION 1
492 #define CONFIG_ISO_PARTITION 1
495 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
496 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
497 #undef CONFIG_IDE_LED /* LED for ide not supported */
498 #undef CONFIG_IDE_RESET /* reset for ide not supported */
500 #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
501 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
503 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
504 #define CFG_ATA_IDE0_OFFSET 0x0000
506 /* Offset for data I/O */
507 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
508 /* Offset for normal register accesses */
509 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
510 /* Offset for alternate registers */
511 #define CFG_ATA_ALT_OFFSET 0x0000
513 #define CONFIG_DISK_SPINUP_TIME 1000000
514 #undef CONFIG_DISK_SPINUP_TIME /* usinĀ“ Compact Flash */