2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <asm/macro.h>
24 #include <asm/arch/ftsdmc020.h>
27 * parameters for the SDRAM controller
29 #define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
30 #define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
31 #define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
32 #define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
33 #define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
35 #define TP0_D CONFIG_SYS_FTSDMC020_TP0
36 #define TP1_D CONFIG_SYS_FTSDMC020_TP1
37 #define CR_D1 FTSDMC020_CR_IPREC
38 #define CR_D2 FTSDMC020_CR_ISMR
39 #define CR_D3 FTSDMC020_CR_IREF
41 #define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
42 FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
43 #define ACR_D FTSDMC020_ACR_TOC(0x18)
46 * numeric 7 segment display
49 write32 CONFIG_DEBUG_LED, \num
53 * Waiting for SDRAM to set up
56 ldr r0, =CONFIG_FTSDMC020_BASE
58 ldr r1, [r0, #FTSDMC020_OFFSET_CR]
73 /* everything is fine now */
78 * memory initialization
83 /* set SDRAM register */
91 /* set to precharge */
98 /* set mode register */
112 write32 B0_BSR_A, B0_BSR_D