3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define _NOT_USED_ 0xFFFFFFFF
13 /*Orginal table, GPL4 disabled*/
14 const uint sdram_table[] =
16 /* single read (offset 0x00 in upm ram) */
17 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
23 /* burst read (offset 0x08 in upm ram) */
24 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
25 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
26 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
27 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
28 /* single write (offset 0x18 in upm ram) */
29 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
30 /* Load moderegister */
31 0x1FF74C34, /*Precharge*/
33 0x1FB54C35, /*Load moderegister*/
36 /* burst write (offset 0x20 in upm ram) */
37 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
38 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
39 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
40 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
41 /* refresh (offset 0x30 in upm ram) */
42 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
43 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
44 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
45 /* exception (offset 0x3C in upm ram) */
46 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
49 /* GPL5 driven every cycle */
50 /* the display and the DSP */
51 const uint dsp_disp_table[] =
53 /* single read (offset 0x00 in upm ram) */
54 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
55 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
56 /* burst read (offset 0x08 in upm ram) */
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 /* single write (offset 0x18 in upm ram) */
62 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
63 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
64 /* burst write (offset 0x20 in upm ram) */
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69 /* refresh (offset 0x30 in upm ram) */
70 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73 /* exception (offset 0x3C in upm ram) */
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 puts ("Board: FlagaDM V3.0\n");
83 phys_size_t initdram (int board_type)
85 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
86 volatile memctl8xx_t *memctl = &immap->im_memctl;
89 memctl->memc_or2 = CONFIG_SYS_OR2;
90 memctl->memc_br2 = CONFIG_SYS_BR2;
93 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
95 memctl->memc_mptpr = MPTPR_PTP_DIV16;
96 memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;
98 /*Do the initialization of the SDRAM*/
99 /*Start with the precharge cycle*/
100 memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
101 MCR_MLCF(1) | MCR_MAD(0x5));
103 /*Then we need two refresh cycles*/
104 memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;
105 memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
106 MCR_MLCF(2) | MCR_MAD(0x30));
108 /*Mode register programming*/
109 memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
110 memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
111 MCR_MLCF(1) | MCR_MAD(0x1C));
113 /* That should do it, just enable the periodic refresh in burst of 4*/
114 memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;
115 memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
117 size_b0 = 16*1024*1024;
123 memctl->memc_br1 = 0;
124 memctl->memc_br3 = 0;
126 upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
128 memctl->memc_mbmr = MBMR_GPL_B4DIS;
130 memctl->memc_or4 = CONFIG_SYS_OR4;
131 memctl->memc_br4 = CONFIG_SYS_BR4;