1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
10 #include <linux/compiler.h>
12 #include <asm/processor.h>
13 #include <linux/errno.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_liodn.h>
22 #include "../common/qixis.h"
23 #include "../common/vsc3316_3308.h"
24 #include "../common/idt8t49n222a_serdes_clk.h"
25 #include "../common/zm7300.h"
27 #include "b4860qds_qixis.h"
28 #include "b4860qds_crossbar_con.h"
30 #define CLK_MUX_SEL_MASK 0x4
31 #define ETH_PHY_CLK_OUT 0x4
33 DECLARE_GLOBAL_DATA_PTR;
39 struct cpu_type *cpu = gd->arch.cpu;
40 static const char *const freq[] = {"100", "125", "156.25", "161.13",
41 "122.88", "122.88", "122.88"};
44 printf("Board: %sQDS, ", cpu->name);
45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
46 QIXIS_READ(id), QIXIS_READ(arch));
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank: %d\n", sw);
53 else if (sw >= 0x8 && sw <= 0xE)
56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
58 printf("FPGA: v%d (%s), build %d",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor());
61 /* the timestamp string contains "\n" at the end */
62 printf(" on %s", qixis_read_time(buf));
65 * Display the actual SERDES reference clocks as configured by the
66 * dip switches on the board. Note that the SWx registers could
67 * technically be set to force the reference clocks to match the
68 * values that the SERDES expects (or vice versa). For now, however,
69 * we just display both values and hope the user notices when they
72 puts("SERDES Reference Clocks: ");
73 sw = QIXIS_READ(brdcfg[2]);
74 clock = (sw >> 5) & 7;
75 printf("Bank1=%sMHz ", freq[clock]);
76 sw = QIXIS_READ(brdcfg[4]);
77 clock = (sw >> 6) & 3;
78 printf("Bank2=%sMHz\n", freq[clock]);
83 int select_i2c_ch_pca(u8 ch)
87 /* Selecting proper channel via PCA*/
88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
90 printf("PCA: failed to select proper channel.\n");
98 * read_voltage from sensor on I2C bus
99 * We use average of 4 readings, waiting for 532us befor another reading
101 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
102 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
104 static inline int read_voltage(void)
106 int i, ret, voltage_read = 0;
109 for (i = 0; i < NUM_READINGS; i++) {
110 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
111 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
113 printf("VID: failed to read core voltage\n");
116 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
117 printf("VID: Core voltage sensor error\n");
120 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
122 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
123 udelay(WAIT_FOR_ADC);
125 /* calculate the average */
126 voltage_read /= NUM_READINGS;
131 static int adjust_vdd(ulong vdd_override)
133 int re_enable = disable_interrupts();
134 ccsr_gur_t __iomem *gur =
135 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
138 int vdd_target, vdd_last;
139 int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
141 unsigned int orig_i2c_speed;
142 unsigned long vdd_string_override;
144 static const uint16_t vdd[32] = {
177 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
179 printf("VID: I2c failed to switch channel\n");
184 /* get the voltage ID from fuse status register */
185 fusesr = in_be32(&gur->dcfg_fusesr);
186 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
187 FSL_CORENET_DCFG_FUSESR_VID_MASK;
188 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
189 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
190 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
192 vdd_target = vdd[vid];
193 debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
196 /* check override variable for overriding VDD */
197 vdd_string = env_get("b4qds_vdd_mv");
198 if (vdd_override == 0 && vdd_string &&
199 !strict_strtoul(vdd_string, 10, &vdd_string_override))
200 vdd_override = vdd_string_override;
201 if (vdd_override >= 819 && vdd_override <= 1212) {
202 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
203 debug("VDD override is %lu\n", vdd_override);
204 } else if (vdd_override != 0) {
205 printf("Invalid value.\n");
208 if (vdd_target == 0) {
209 printf("VID: VID not used\n");
215 * Read voltage monitor to check real voltage.
216 * Voltage monitor LSB is 4mv.
218 vdd_last = read_voltage();
220 printf("VID: abort VID adjustment\n");
225 debug("VID: Core voltage is at %d mV\n", vdd_last);
226 ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
228 printf("VID: I2c failed to switch channel to DPM\n");
233 /* Round up to the value of step of Voltage regulator */
234 voltage = roundup(vdd_target, ZM_STEP);
235 debug("VID: rounded up voltage = %d\n", voltage);
237 /* lower the speed to 100kHz to access ZM7300 device */
238 debug("VID: Setting bus speed to 100KHz if not already set\n");
239 orig_i2c_speed = i2c_get_bus_speed();
240 if (orig_i2c_speed != 100000)
241 i2c_set_bus_speed(100000);
243 /* Read the existing level on board, if equal to requsted one,
245 existing_voltage = zm_read_voltage();
247 /* allowing the voltage difference of one step 0.0125V acceptable */
248 if ((existing_voltage >= voltage) &&
249 (existing_voltage < (voltage + ZM_STEP))) {
250 debug("VID: voltage already set as requested,returning\n");
251 ret = existing_voltage;
254 debug("VID: Changing voltage for board from %dmV to %dmV\n",
255 existing_voltage/10, voltage/10);
257 if (zm_disable_wp() < 0) {
261 /* Change Voltage: the change is done through all the steps in the
262 way, to avoid reset to the board due to power good signal fail
263 in big voltage change gap jump.
265 if (existing_voltage > voltage) {
266 temp_voltage = existing_voltage - ZM_STEP;
267 while (temp_voltage >= voltage) {
268 ret = zm_write_voltage(temp_voltage);
269 if (ret == temp_voltage) {
270 temp_voltage -= ZM_STEP;
272 /* ZM7300 device failed to set
275 ("VID:Stepping down vol failed:%dmV\n",
282 temp_voltage = existing_voltage + ZM_STEP;
283 while (temp_voltage < (voltage + ZM_STEP)) {
284 ret = zm_write_voltage(temp_voltage);
285 if (ret == temp_voltage) {
286 temp_voltage += ZM_STEP;
288 /* ZM7300 device failed to set
291 ("VID:Stepping up vol failed:%dmV\n",
299 if (zm_enable_wp() < 0)
302 /* restore the speed to 400kHz */
303 out: debug("VID: Restore the I2C bus speed to %dKHz\n",
304 orig_i2c_speed/1000);
305 i2c_set_bus_speed(orig_i2c_speed);
309 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
311 printf("VID: I2c failed to switch channel\n");
315 vdd_last = read_voltage();
316 select_i2c_ch_pca(I2C_CH_DEFAULT);
319 printf("VID: Core voltage %d mV\n", vdd_last);
329 int configure_vsc3316_3308(void)
331 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
332 unsigned int num_vsc16_con, num_vsc08_con;
333 u32 serdes1_prtcl, serdes2_prtcl;
335 char buffer[HWCONFIG_BUFFER_SIZE];
338 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
339 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
340 if (!serdes1_prtcl) {
341 printf("SERDES1 is not enabled\n");
344 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
345 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
347 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
348 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
349 if (!serdes2_prtcl) {
350 printf("SERDES2 is not enabled\n");
353 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
354 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
356 switch (serdes1_prtcl) {
366 * Lanes: C,D,E,F,G,H: CPRI
368 debug("Configuring crossbar to use onboard SGMII PHYs:"
369 "srds_prctl:%x\n", serdes1_prtcl);
370 num_vsc16_con = NUM_CON_VSC3316;
371 /* Configure VSC3316 crossbar switch */
372 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
374 ret = vsc3316_config(VSC3316_TX_ADDRESS,
375 vsc16_tx_4sfp_sgmii_12_56,
379 ret = vsc3316_config(VSC3316_RX_ADDRESS,
380 vsc16_rx_4sfp_sgmii_12_56,
416 * Lanes: E,F,G,H: CPRI
418 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
419 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
420 num_vsc16_con = NUM_CON_VSC3316;
421 /* Configure VSC3316 crossbar switch */
422 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
424 ret = vsc3316_config(VSC3316_TX_ADDRESS,
425 vsc16_tx_sfp_sgmii_aurora,
429 ret = vsc3316_config(VSC3316_RX_ADDRESS,
430 vsc16_rx_sfp_sgmii_aurora,
439 #ifdef CONFIG_ARCH_B4420
445 * Lanes: A,B,C,D: SGMII
446 * Lanes: E,F,G,H: CPRI
448 debug("Configuring crossbar to use onboard SGMII PHYs:"
449 "srds_prctl:%x\n", serdes1_prtcl);
450 num_vsc16_con = NUM_CON_VSC3316;
451 /* Configure VSC3316 crossbar switch */
452 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
454 ret = vsc3316_config(VSC3316_TX_ADDRESS,
455 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
458 ret = vsc3316_config(VSC3316_RX_ADDRESS,
459 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
472 num_vsc16_con = NUM_CON_VSC3316;
473 /* Configure VSC3316 crossbar switch */
474 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
476 ret = vsc3316_config(VSC3316_TX_ADDRESS,
477 vsc16_tx_sfp, num_vsc16_con);
480 ret = vsc3316_config(VSC3316_RX_ADDRESS,
481 vsc16_rx_sfp, num_vsc16_con);
489 printf("WARNING:VSC crossbars programming not supported for:%x"
490 " SerDes1 Protocol.\n", serdes1_prtcl);
494 num_vsc08_con = NUM_CON_VSC3308;
495 /* Configure VSC3308 crossbar switch */
496 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
497 switch (serdes2_prtcl) {
498 #ifdef CONFIG_ARCH_B4420
510 ret = vsc3308_config(VSC3308_TX_ADDRESS,
511 vsc08_tx_amc, num_vsc08_con);
514 ret = vsc3308_config(VSC3308_RX_ADDRESS,
515 vsc08_rx_amc, num_vsc08_con);
541 * Extract hwconfig from environment since environment
542 * is not setup properly yet
544 env_get_f("hwconfig", buffer, sizeof(buffer));
547 if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
548 "sfp_amc", "sfp", buf)) {
549 #ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
550 /* change default VSC3308 for XFI erratum */
551 ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
552 vsc08_tx_sfp, num_vsc08_con);
556 ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
557 vsc08_rx_sfp, num_vsc08_con);
561 ret = vsc3308_config(VSC3308_TX_ADDRESS,
562 vsc08_tx_sfp, num_vsc08_con);
566 ret = vsc3308_config(VSC3308_RX_ADDRESS,
567 vsc08_rx_sfp, num_vsc08_con);
572 ret = vsc3308_config(VSC3308_TX_ADDRESS,
573 vsc08_tx_amc, num_vsc08_con);
577 ret = vsc3308_config(VSC3308_RX_ADDRESS,
578 vsc08_rx_amc, num_vsc08_con);
588 printf("WARNING:VSC crossbars programming not supported for: %x"
589 " SerDes2 Protocol.\n", serdes2_prtcl);
596 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
600 /* Steps For SerDes PLLs reset and reconfiguration
601 * or PLL power-up procedure
603 debug("CALIBRATE PLL:%d\n", pll_num);
604 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
605 SRDS_RSTCTL_SDRST_B);
607 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
608 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
610 setbits_be32(&srds_regs->bank[pll_num].rstctl,
612 setbits_be32(&srds_regs->bank[pll_num].rstctl,
613 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
614 | SRDS_RSTCTL_SDRST_B));
618 /* Check whether PLL has been locked or not */
619 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
621 rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
622 debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
629 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
632 u32 fcap, dcbias, bcap, pllcr1, pllcr0;
634 if (calibrate_pll(srds_regs, pll_num)) {
636 /* Read fcap, dcbias and bcap value */
637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
638 SRDS_PLLCR0_DCBIAS_OUT_EN);
639 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
641 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
642 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
644 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
645 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
646 SRDS_PLLCR0_DCBIAS_OUT_EN);
647 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
649 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
650 debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
652 if (fcap == 0 && bcap == 1) {
654 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
655 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
656 | SRDS_RSTCTL_SDRST_B));
657 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
658 SRDS_PLLCR1_BCAP_EN);
659 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
660 SRDS_PLLCR1_BCAP_OVD);
661 if (calibrate_pll(srds_regs, pll_num)) {
662 /*save the fcap, dcbias and bcap values*/
663 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
664 SRDS_PLLCR0_DCBIAS_OUT_EN);
665 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
667 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
668 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
669 & SRDS_PLLSR2_BCAP_EN;
670 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
671 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
672 SRDS_PLLCR0_DCBIAS_OUT_EN);
674 (&srds_regs->bank[pll_num].pllsr2) &
676 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
679 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
680 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
681 | SRDS_RSTCTL_SDRST_B));
682 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
683 SRDS_PLLCR1_BYP_CAL);
684 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
685 SRDS_PLLCR1_BCAP_EN);
686 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
687 SRDS_PLLCR1_BCAP_OVD);
688 /* change the fcap and dcbias to the saved
689 * values from Step 3 */
690 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
691 SRDS_PLLCR1_PLL_FCAP);
693 (&srds_regs->bank[pll_num].pllcr1)|
694 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
695 out_be32(&srds_regs->bank[pll_num].pllcr1,
697 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
698 SRDS_PLLCR0_DCBIAS_OVRD);
700 (&srds_regs->bank[pll_num].pllcr0)|
701 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
702 out_be32(&srds_regs->bank[pll_num].pllcr0,
704 ret = calibrate_pll(srds_regs, pll_num);
710 } else { /* Step 5 */
711 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
712 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
713 | SRDS_RSTCTL_SDRST_B));
715 /* Change the fcap, dcbias, and bcap to the
716 * values from Step 1 */
717 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
718 SRDS_PLLCR1_BYP_CAL);
719 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
720 SRDS_PLLCR1_PLL_FCAP);
721 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
722 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
723 out_be32(&srds_regs->bank[pll_num].pllcr1,
725 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
726 SRDS_PLLCR0_DCBIAS_OVRD);
727 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
728 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
729 out_be32(&srds_regs->bank[pll_num].pllcr0,
731 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
732 SRDS_PLLCR1_BCAP_EN);
733 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
734 SRDS_PLLCR1_BCAP_OVD);
735 ret = calibrate_pll(srds_regs, pll_num);
744 static int check_serdes_pll_locks(void)
746 serdes_corenet_t *srds1_regs =
747 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
748 serdes_corenet_t *srds2_regs =
749 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
752 debug("\nSerDes1 Lock check\n");
753 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
754 ret1 = check_pll_locks(srds1_regs, i);
756 printf("SerDes1, PLL:%d didnt lock\n", i);
760 debug("\nSerDes2 Lock check\n");
761 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
762 ret2 = check_pll_locks(srds2_regs, i);
764 printf("SerDes2, PLL:%d didnt lock\n", i);
772 int config_serdes1_refclks(void)
774 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
775 serdes_corenet_t *srds_regs =
776 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
777 u32 serdes1_prtcl, lane;
778 unsigned int flag_sgmii_aurora_prtcl = 0;
782 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
783 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
784 if (!serdes1_prtcl) {
785 printf("SERDES1 is not enabled\n");
788 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
789 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
791 /* To prevent generation of reset request from SerDes
792 * while changing the refclks, By setting SRDS_RST_MSK bit,
793 * SerDes reset event cannot cause a reset request
795 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
797 /* Reconfigure IDT idt8t49n222a device for CPRI to work
798 * For this SerDes1's Refclk1 and refclk2 need to be set
801 switch (serdes1_prtcl) {
829 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
830 " for srds_prctl:%x\n", serdes1_prtcl);
831 ret = select_i2c_ch_pca(I2C_CH_IDT);
833 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
834 SERDES_REFCLK_122_88,
835 SERDES_REFCLK_122_88, 0);
837 printf("IDT8T49N222A configuration failed.\n");
840 debug("IDT8T49N222A configured.\n");
844 select_i2c_ch_pca(I2C_CH_DEFAULT);
846 /* Change SerDes1's Refclk1 to 125MHz for on board
847 * SGMIIs or Aurora to work
849 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
850 enum srds_prtcl lane_prtcl = serdes_get_prtcl
851 (0, serdes1_prtcl, lane);
852 switch (lane_prtcl) {
853 case SGMII_FM1_DTSEC1:
854 case SGMII_FM1_DTSEC2:
855 case SGMII_FM1_DTSEC3:
856 case SGMII_FM1_DTSEC4:
857 case SGMII_FM1_DTSEC5:
858 case SGMII_FM1_DTSEC6:
860 flag_sgmii_aurora_prtcl++;
867 if (flag_sgmii_aurora_prtcl)
868 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
870 /* Steps For SerDes PLLs reset and reconfiguration after
871 * changing SerDes's refclks
873 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
874 debug("For PLL%d reset and reconfiguration after"
875 " changing refclks\n", i+1);
876 clrbits_be32(&srds_regs->bank[i].rstctl,
877 SRDS_RSTCTL_SDRST_B);
879 clrbits_be32(&srds_regs->bank[i].rstctl,
880 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
882 setbits_be32(&srds_regs->bank[i].rstctl,
884 setbits_be32(&srds_regs->bank[i].rstctl,
885 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
886 | SRDS_RSTCTL_SDRST_B));
890 printf("WARNING:IDT8T49N222A configuration not"
891 " supported for:%x SerDes1 Protocol.\n",
896 /* Clearing SRDS_RST_MSK bit as now
897 * SerDes reset event can cause a reset request
899 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
903 int config_serdes2_refclks(void)
905 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
906 serdes_corenet_t *srds2_regs =
907 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
912 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
913 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
914 if (!serdes2_prtcl) {
915 debug("SERDES2 is not enabled\n");
918 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
919 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
921 /* To prevent generation of reset request from SerDes
922 * while changing the refclks, By setting SRDS_RST_MSK bit,
923 * SerDes reset event cannot cause a reset request
925 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
927 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
928 * For this SerDes2's Refclk1 need to be set to 100MHz
930 switch (serdes2_prtcl) {
931 #ifdef CONFIG_ARCH_B4420
939 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
941 ret = select_i2c_ch_pca(I2C_CH_IDT);
943 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
945 SERDES_REFCLK_156_25, 0);
947 printf("IDT8T49N222A configuration failed.\n");
950 debug("IDT8T49N222A configured.\n");
954 select_i2c_ch_pca(I2C_CH_DEFAULT);
956 /* Steps For SerDes PLLs reset and reconfiguration after
957 * changing SerDes's refclks
959 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
960 clrbits_be32(&srds2_regs->bank[i].rstctl,
961 SRDS_RSTCTL_SDRST_B);
963 clrbits_be32(&srds2_regs->bank[i].rstctl,
964 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
966 setbits_be32(&srds2_regs->bank[i].rstctl,
968 setbits_be32(&srds2_regs->bank[i].rstctl,
969 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
970 | SRDS_RSTCTL_SDRST_B));
976 printf("IDT configuration not supported for:%x S2 Protocol.\n",
981 /* Clearing SRDS_RST_MSK bit as now
982 * SerDes reset event can cause a reset request
984 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
988 int board_early_init_r(void)
990 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
991 int flash_esel = find_tlb_idx((void *)flashbase, 1);
993 u32 svr = SVR_SOC_VER(get_svr());
995 /* Create law for MAPLE only for personalities having MAPLE */
996 if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
997 (svr == SVR_B4420) || (svr == SVR_B4220)) {
998 set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
1003 * Remap Boot flash + PROMJET region to caching-inhibited
1004 * so that flash can be erased properly.
1007 /* Flush d-cache and invalidate i-cache of any FLASH data */
1009 invalidate_icache();
1011 if (flash_esel == -1) {
1012 /* very unlikely unless something is messed up */
1013 puts("Error: Could not find TLB for FLASH BASE\n");
1014 flash_esel = 2; /* give our best effort to continue */
1016 /* invalidate existing TLB entry for flash + promjet */
1017 disable_tlb(flash_esel);
1020 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
1021 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
1022 0, flash_esel, BOOKE_PAGESZ_256M, 1);
1025 * Adjust core voltage according to voltage ID
1026 * This function changes I2C mux to channel 2.
1028 if (adjust_vdd(0) < 0)
1029 printf("Warning: Adjusting core voltage failed\n");
1031 /* SerDes1 refclks need to be set again, as default clks
1032 * are not suitable for CPRI and onboard SGMIIs to work
1034 * This function will set SerDes1's Refclk1 and refclk2
1035 * as per SerDes1 protocols
1037 if (config_serdes1_refclks())
1038 printf("SerDes1 Refclks couldn't set properly.\n");
1040 printf("SerDes1 Refclks have been set.\n");
1042 /* SerDes2 refclks need to be set again, as default clks
1043 * are not suitable for PCIe SATA to work
1044 * This function will set SerDes2's Refclk1 and refclk2
1045 * for SerDes2 protocols having PCIe in them
1046 * for PCIe SATA to work
1048 ret = config_serdes2_refclks();
1050 printf("SerDes2 Refclks have been set.\n");
1051 else if (ret == -ENODEV)
1052 printf("SerDes disable, Refclks couldn't change.\n");
1054 printf("SerDes2 Refclk reconfiguring failed.\n");
1056 #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
1057 defined(CONFIG_SYS_FSL_ERRATUM_A006475)
1058 /* Rechecking the SerDes locks after all SerDes configurations
1059 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
1060 * and at cold temperatures.
1061 * Following sequence ensure the proper locking of SerDes PLLs.
1063 if (SVR_MAJ(get_svr()) == 1) {
1064 if (check_serdes_pll_locks())
1065 printf("SerDes plls still not locked properly.\n");
1067 printf("SerDes plls have been locked well.\n");
1071 /* Configure VSC3316 and VSC3308 crossbar switches */
1072 if (configure_vsc3316_3308())
1073 printf("VSC:failed to configure VSC3316/3308.\n");
1075 printf("VSC:VSC3316/3308 successfully configured.\n");
1077 select_i2c_ch_pca(I2C_CH_DEFAULT);
1082 unsigned long get_board_sys_clk(void)
1084 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
1086 switch ((sysclk_conf & 0x0C) >> 2) {
1097 unsigned long get_board_ddr_clk(void)
1099 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
1101 switch (ddrclk_conf & 0x03) {
1112 static int serdes_refclock(u8 sw, u8 sdclk)
1119 brdcfg4 = QIXIS_READ(brdcfg[4]);
1120 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
1121 return SRDS_PLLCR0_RFCK_SEL_125;
1123 clock = (sw >> 5) & 7;
1125 clock = (sw >> 6) & 3;
1129 ret = SRDS_PLLCR0_RFCK_SEL_100;
1132 ret = SRDS_PLLCR0_RFCK_SEL_125;
1135 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
1138 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
1143 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
1153 #define NUM_SRDS_BANKS 2
1155 int misc_init_r(void)
1158 serdes_corenet_t *srds_regs =
1159 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
1160 u32 actual[NUM_SRDS_BANKS];
1164 sw = QIXIS_READ(brdcfg[2]);
1165 clock = serdes_refclock(sw, 1);
1169 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
1171 sw = QIXIS_READ(brdcfg[4]);
1172 clock = serdes_refclock(sw, 2);
1176 printf("Warning: SDREFCLK2 switch setting unsupported\n");
1178 for (i = 0; i < NUM_SRDS_BANKS; i++) {
1179 u32 pllcr0 = srds_regs->bank[i].pllcr0;
1180 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
1181 if (expected != actual[i]) {
1182 printf("Warning: SERDES bank %u expects reference clock"
1183 " %sMHz, but actual is %sMHz\n", i + 1,
1184 serdes_clock_to_string(expected),
1185 serdes_clock_to_string(actual[i]));
1192 int ft_board_setup(void *blob, bd_t *bd)
1197 ft_cpu_setup(blob, bd);
1199 base = env_get_bootm_low();
1200 size = env_get_bootm_size();
1202 fdt_fixup_memory(blob, (u64)base, (u64)size);
1205 pci_of_setup(blob, bd);
1208 fdt_fixup_liodn(blob);
1210 #ifdef CONFIG_HAS_FSL_DR_USB
1211 fsl_fdt_fixup_dr_usb(blob, bd);
1214 #ifdef CONFIG_SYS_DPAA_FMAN
1215 fdt_fixup_fman_ethernet(blob);
1216 fdt_fixup_board_enet(blob);
1223 * Dump board switch settings.
1224 * The bits that cannot be read/sampled via some FPGA or some
1225 * registers, they will be displayed as
1226 * underscore in binary format. mask[] has those bits.
1227 * Some bits are calculated differently than the actual switches
1228 * if booting with overriding by FPGA.
1230 void qixis_dump_switch(void)
1236 * Any bit with 1 means that bit cannot be reverse engineered.
1237 * It will be displayed as _ in binary format.
1239 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
1241 u8 brdcfg[16], dutcfg[16];
1243 for (i = 0; i < 16; i++) {
1244 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
1245 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
1248 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
1250 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
1251 ((dutcfg[2] & 0x07) << 4) | \
1252 ((dutcfg[6] & 0x10) >> 1) | \
1253 ((dutcfg[6] & 0x80) >> 5) | \
1254 ((dutcfg[1] & 0x40) >> 5) | \
1258 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
1259 ((brdcfg[1] & 0xc0) >> 2) | \
1262 puts("DIP switch settings:\n");
1263 for (i = 0; i < 5; i++) {
1264 printf("SW%d = 0b%s (0x%02x)\n",
1265 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);