2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
22 #include "../common/qixis.h"
23 #include "../common/vsc3316_3308.h"
24 #include "../common/idt8t49n222a_serdes_clk.h"
26 #include "b4860qds_qixis.h"
27 #include "b4860qds_crossbar_con.h"
29 #define CLK_MUX_SEL_MASK 0x4
30 #define ETH_PHY_CLK_OUT 0x4
33 DECLARE_GLOBAL_DATA_PTR;
39 struct cpu_type *cpu = gd->arch.cpu;
40 static const char *const freq[] = {"100", "125", "156.25", "161.13",
41 "122.88", "122.88", "122.88"};
44 printf("Board: %sQDS, ", cpu->name);
45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
46 QIXIS_READ(id), QIXIS_READ(arch));
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank: %d\n", sw);
53 else if (sw >= 0x8 && sw <= 0xE)
56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
58 printf("FPGA: v%d (%s), build %d",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor());
61 /* the timestamp string contains "\n" at the end */
62 printf(" on %s", qixis_read_time(buf));
65 * Display the actual SERDES reference clocks as configured by the
66 * dip switches on the board. Note that the SWx registers could
67 * technically be set to force the reference clocks to match the
68 * values that the SERDES expects (or vice versa). For now, however,
69 * we just display both values and hope the user notices when they
72 puts("SERDES Reference Clocks: ");
73 sw = QIXIS_READ(brdcfg[2]);
74 clock = (sw >> 5) & 7;
75 printf("Bank1=%sMHz ", freq[clock]);
76 sw = QIXIS_READ(brdcfg[4]);
77 clock = (sw >> 6) & 3;
78 printf("Bank2=%sMHz\n", freq[clock]);
83 int select_i2c_ch_pca(u8 ch)
87 /* Selecting proper channel via PCA*/
88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
90 printf("PCA: failed to select proper channel.\n");
97 int configure_vsc3316_3308(void)
99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 unsigned int num_vsc16_con, num_vsc08_con;
101 u32 serdes1_prtcl, serdes2_prtcl;
104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
106 if (!serdes1_prtcl) {
107 printf("SERDES1 is not enabled\n");
110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
115 if (!serdes2_prtcl) {
116 printf("SERDES2 is not enabled\n");
119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
122 switch (serdes1_prtcl) {
131 * Lanes: C,D,E,F,G,H: CPRI
133 debug("Configuring crossbar to use onboard SGMII PHYs:"
134 "srds_prctl:%x\n", serdes1_prtcl);
135 num_vsc16_con = NUM_CON_VSC3316;
136 /* Configure VSC3316 crossbar switch */
137 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
139 ret = vsc3316_config(VSC3316_TX_ADDRESS,
140 vsc16_tx_4sfp_sgmii_12_56,
144 ret = vsc3316_config(VSC3316_RX_ADDRESS,
145 vsc16_rx_4sfp_sgmii_12_56,
154 #ifdef CONFIG_PPC_B4420
159 * Lanes: A,B,C,D: SGMII
160 * Lanes: E,F,G,H: CPRI
162 debug("Configuring crossbar to use onboard SGMII PHYs:"
163 "srds_prctl:%x\n", serdes1_prtcl);
164 num_vsc16_con = NUM_CON_VSC3316;
165 /* Configure VSC3316 crossbar switch */
166 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
168 ret = vsc3316_config(VSC3316_TX_ADDRESS,
169 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
172 ret = vsc3316_config(VSC3316_RX_ADDRESS,
173 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
186 num_vsc16_con = NUM_CON_VSC3316;
187 /* Configure VSC3316 crossbar switch */
188 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
190 ret = vsc3316_config(VSC3316_TX_ADDRESS,
191 vsc16_tx_sfp, num_vsc16_con);
194 ret = vsc3316_config(VSC3316_RX_ADDRESS,
195 vsc16_rx_sfp, num_vsc16_con);
203 printf("WARNING:VSC crossbars programming not supported for:%x"
204 " SerDes1 Protocol.\n", serdes1_prtcl);
208 switch (serdes2_prtcl) {
217 num_vsc08_con = NUM_CON_VSC3308;
218 /* Configure VSC3308 crossbar switch */
219 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
221 ret = vsc3308_config(VSC3308_TX_ADDRESS,
222 vsc08_tx_amc, num_vsc08_con);
225 ret = vsc3308_config(VSC3308_RX_ADDRESS,
226 vsc08_rx_amc, num_vsc08_con);
234 printf("WARNING:VSC crossbars programming not supported for: %x"
235 " SerDes2 Protocol.\n", serdes2_prtcl);
242 int config_serdes1_refclks(void)
244 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
245 serdes_corenet_t *srds_regs =
246 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
247 u32 serdes1_prtcl, lane;
248 unsigned int flag_sgmii_prtcl = 0;
251 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
252 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
253 if (!serdes1_prtcl) {
254 printf("SERDES1 is not enabled\n");
257 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
258 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
260 /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
262 for (i = 0; i < PLL_NUM; i++)
263 clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
264 /* Reconfigure IDT idt8t49n222a device for CPRI to work
265 * For this SerDes1's Refclk1 and refclk2 need to be set
268 switch (serdes1_prtcl) {
273 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
274 " for srds_prctl:%x\n", serdes1_prtcl);
275 ret = select_i2c_ch_pca(I2C_CH_IDT);
277 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
278 SERDES_REFCLK_122_88,
279 SERDES_REFCLK_122_88, 0);
281 printf("IDT8T49N222A configuration failed.\n");
284 printf("IDT8T49N222A configured.\n");
288 select_i2c_ch_pca(I2C_CH_DEFAULT);
290 /* Change SerDes1's Refclk1 to 125MHz for on board
293 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
294 enum srds_prtcl lane_prtcl = serdes_get_prtcl
295 (0, serdes1_prtcl, lane);
296 switch (lane_prtcl) {
297 case SGMII_FM1_DTSEC1:
298 case SGMII_FM1_DTSEC2:
299 case SGMII_FM1_DTSEC3:
300 case SGMII_FM1_DTSEC4:
301 case SGMII_FM1_DTSEC5:
302 case SGMII_FM1_DTSEC6:
310 if (flag_sgmii_prtcl)
311 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
313 /* Steps For SerDes PLLs reset and reconfiguration after
314 * changing SerDes's refclks
316 for (i = 0; i < PLL_NUM; i++) {
317 debug("For PLL%d reset and reconfiguration after"
318 " changing refclks\n", i+1);
319 clrbits_be32(&srds_regs->bank[i].rstctl,
320 SRDS_RSTCTL_SDRST_B);
322 clrbits_be32(&srds_regs->bank[i].rstctl,
323 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
325 setbits_be32(&srds_regs->bank[i].rstctl,
327 setbits_be32(&srds_regs->bank[i].rstctl,
328 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
329 | SRDS_RSTCTL_SDRST_B));
333 printf("WARNING:IDT8T49N222A configuration not"
334 " supported for:%x SerDes1 Protocol.\n",
342 int board_early_init_r(void)
344 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
345 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
348 * Remap Boot flash + PROMJET region to caching-inhibited
349 * so that flash can be erased properly.
352 /* Flush d-cache and invalidate i-cache of any FLASH data */
356 /* invalidate existing TLB entry for flash + promjet */
357 disable_tlb(flash_esel);
359 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
360 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
361 0, flash_esel, BOOKE_PAGESZ_256M, 1);
364 #ifdef CONFIG_SYS_DPAA_QBMAN
367 /* SerDes1 refclks need to be set again, as default clks
368 * are not suitable for CPRI and onboard SGMIIs to work
370 * This function will set SerDes1's Refclk1 and refclk2
371 * as per SerDes1 protocols
373 if (config_serdes1_refclks())
374 printf("SerDes1 Refclks couldn't set properly.\n");
376 printf("SerDes1 Refclks have been set.\n");
378 /* Configure VSC3316 and VSC3308 crossbar switches */
379 if (configure_vsc3316_3308())
380 printf("VSC:failed to configure VSC3316/3308.\n");
382 printf("VSC:VSC3316/3308 successfully configured.\n");
384 select_i2c_ch_pca(I2C_CH_DEFAULT);
389 unsigned long get_board_sys_clk(void)
391 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
393 switch ((sysclk_conf & 0x0C) >> 2) {
404 unsigned long get_board_ddr_clk(void)
406 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
408 switch (ddrclk_conf & 0x03) {
419 static int serdes_refclock(u8 sw, u8 sdclk)
426 brdcfg4 = QIXIS_READ(brdcfg[4]);
427 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
428 return SRDS_PLLCR0_RFCK_SEL_125;
430 clock = (sw >> 5) & 7;
432 clock = (sw >> 6) & 3;
436 ret = SRDS_PLLCR0_RFCK_SEL_100;
439 ret = SRDS_PLLCR0_RFCK_SEL_125;
442 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
445 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
450 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
460 #define NUM_SRDS_BANKS 2
462 int misc_init_r(void)
465 serdes_corenet_t *srds_regs =
466 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
467 u32 actual[NUM_SRDS_BANKS];
471 sw = QIXIS_READ(brdcfg[2]);
472 clock = serdes_refclock(sw, 1);
476 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
478 sw = QIXIS_READ(brdcfg[4]);
479 clock = serdes_refclock(sw, 2);
483 printf("Warning: SDREFCLK2 switch setting unsupported\n");
485 for (i = 0; i < NUM_SRDS_BANKS; i++) {
486 u32 pllcr0 = srds_regs->bank[i].pllcr0;
487 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
488 if (expected != actual[i]) {
489 printf("Warning: SERDES bank %u expects reference clock"
490 " %sMHz, but actual is %sMHz\n", i + 1,
491 serdes_clock_to_string(expected),
492 serdes_clock_to_string(actual[i]));
499 void ft_board_setup(void *blob, bd_t *bd)
504 ft_cpu_setup(blob, bd);
506 base = getenv_bootm_low();
507 size = getenv_bootm_size();
509 fdt_fixup_memory(blob, (u64)base, (u64)size);
512 pci_of_setup(blob, bd);
515 fdt_fixup_liodn(blob);
517 #ifdef CONFIG_HAS_FSL_DR_USB
518 fdt_fixup_dr_usb(blob, bd);
521 #ifdef CONFIG_SYS_DPAA_FMAN
522 fdt_fixup_fman_ethernet(blob);
523 fdt_fixup_board_enet(blob);
528 * Dump board switch settings.
529 * The bits that cannot be read/sampled via some FPGA or some
530 * registers, they will be displayed as
531 * underscore in binary format. mask[] has those bits.
532 * Some bits are calculated differently than the actual switches
533 * if booting with overriding by FPGA.
535 void qixis_dump_switch(void)
541 * Any bit with 1 means that bit cannot be reverse engineered.
542 * It will be displayed as _ in binary format.
544 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
546 u8 brdcfg[16], dutcfg[16];
548 for (i = 0; i < 16; i++) {
549 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
550 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
553 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
555 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
556 ((dutcfg[2] & 0x07) << 4) | \
557 ((dutcfg[6] & 0x10) >> 1) | \
558 ((dutcfg[6] & 0x80) >> 5) | \
559 ((dutcfg[1] & 0x40) >> 5) | \
563 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
564 ((brdcfg[1] & 0xc0) >> 2) | \
567 puts("DIP switch settings:\n");
568 for (i = 0; i < 5; i++) {
569 printf("SW%d = 0b%s (0x%02x)\n",
570 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);