2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Author: Sandeep Kumar Singh <sandeep@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
11 * This file handles the board muxing between the Fman Ethernet MACs and
12 * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
13 * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
14 * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
15 * one Fman device on B4860. The SERDES configuration is used to determine
16 * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
17 * to which PHYs. So for a given Fman MAC, there is one and only PHY it
18 * connects to. MACs cannot be routed to PHYs dynamically. This configuration
19 * is done at boot time by reading SERDES protocol from RCW.
24 #include <asm/fsl_serdes.h>
28 #include <fdt_support.h>
29 #include <asm/fsl_dtsec.h>
31 #include "../common/ngpixis.h"
32 #include "../common/fman.h"
33 #include "../common/qixis.h"
34 #include "b4860qds_qixis.h"
36 #define EMI_NONE 0xFFFFFFFF
38 #ifdef CONFIG_FMAN_ENET
41 * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
42 * lane at index is mapped to slot number n. A value of '0' will mean
43 * that the mapping must be determined dynamically, or that the lane maps to
44 * something other than a board slot
46 static u8 lane_to_slot[] = {
54 * This function initializes the lane_to_slot[] array. It reads RCW to check
55 * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
56 * lane_to_slot[] accordingly
58 static void initialize_lane_to_slot(void)
60 unsigned int serdes2_prtcl;
61 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
62 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
63 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
64 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
65 debug("Initializing lane to slot: Serdes2 protocol: %x\n",
68 switch (serdes2_prtcl) {
73 * Lanes: A,B,C,D: SGMII
83 * Lanes: E,F,G,H: XAUI2
89 * Lanes: A,B,C,D: SGMII
90 * Lanes: E,F,G,H: XAUI2
96 * Lanes: A,B,C,D: XAUI2
97 * Lanes: E,F,G,H: XAUI2
105 * Lanes: E,F,G,H: XAUI2
111 * Lanes: A,B,C,D: PCI
112 * Lanes: E,F,G,H: XAUI2
118 * Lanes: A,B,C,D: PCI
119 * Lanes: E,F: SGMII 3&4
128 * Lanes: E,F,G,H: XAUI2
130 lane_to_slot[12] = 2;
131 lane_to_slot[13] = lane_to_slot[12];
132 lane_to_slot[14] = lane_to_slot[12];
133 lane_to_slot[15] = lane_to_slot[12];
137 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
144 #endif /* #ifdef CONFIG_FMAN_ENET */
146 int board_eth_init(bd_t *bis)
148 #ifdef CONFIG_FMAN_ENET
149 struct memac_mdio_info memac_mdio_info;
150 struct memac_mdio_info tg_memac_mdio_info;
152 unsigned int serdes1_prtcl, serdes2_prtcl;
155 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
156 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
157 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
158 if (!serdes1_prtcl) {
159 printf("SERDES1 is not enabled\n");
162 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
163 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
165 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
166 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
167 if (!serdes2_prtcl) {
168 printf("SERDES2 is not enabled\n");
171 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
172 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
174 printf("Initializing Fman\n");
176 initialize_lane_to_slot();
178 memac_mdio_info.regs =
179 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
180 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
182 /* Register the real 1G MDIO bus */
183 fm_memac_mdio_init(bis, &memac_mdio_info);
185 tg_memac_mdio_info.regs =
186 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
187 tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
189 /* Register the real 10G MDIO bus */
190 fm_memac_mdio_init(bis, &tg_memac_mdio_info);
193 * Program the two on board DTSEC PHY addresses assuming that they are
194 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
195 * 6 to on board SGMII phys
197 fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
198 fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
200 switch (serdes1_prtcl) {
202 /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
203 debug("Setting phy addresses for FM1_DTSEC5: %x and"
204 "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
205 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
206 fm_info_set_phy_address(FM1_DTSEC5,
207 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
208 fm_info_set_phy_address(FM1_DTSEC6,
209 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
211 #ifdef CONFIG_PPC_B4420
213 /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
214 debug("Setting phy addresses for FM1_DTSEC3: %x and"
215 "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
216 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
217 /* Fixing Serdes clock by programming FPGA register */
218 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
219 fm_info_set_phy_address(FM1_DTSEC3,
220 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
221 fm_info_set_phy_address(FM1_DTSEC4,
222 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
226 printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
230 switch (serdes2_prtcl) {
232 debug("Setting phy addresses on SGMII Riser card for"
233 "FM1_DTSEC ports: \n");
234 fm_info_set_phy_address(FM1_DTSEC1,
235 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
236 fm_info_set_phy_address(FM1_DTSEC2,
237 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
238 fm_info_set_phy_address(FM1_DTSEC3,
239 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
240 fm_info_set_phy_address(FM1_DTSEC4,
241 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
244 debug("Setting phy addresses on SGMII Riser card for"
245 "FM1_DTSEC ports: \n");
246 fm_info_set_phy_address(FM1_DTSEC1,
247 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
248 fm_info_set_phy_address(FM1_DTSEC2,
249 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
250 fm_info_set_phy_address(FM1_DTSEC3,
251 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
255 debug("Setting phy addresses on SGMII Riser card for"
256 "FM1_DTSEC ports: \n");
257 fm_info_set_phy_address(FM1_DTSEC3,
258 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
259 fm_info_set_phy_address(FM1_DTSEC4,
260 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
263 /* XAUI in Slot1 and Slot2 */
264 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
265 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
266 fm_info_set_phy_address(FM1_10GEC1,
267 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
268 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
269 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
270 fm_info_set_phy_address(FM1_10GEC2,
271 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
275 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
276 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
277 fm_info_set_phy_address(FM1_10GEC2,
278 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
281 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
286 /*set PHY address for QSGMII Riser Card on slot2*/
287 bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
288 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
291 switch (serdes2_prtcl) {
294 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
295 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
302 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
303 int idx = i - FM1_DTSEC1;
305 switch (fm_info_get_enet_if(i)) {
306 case PHY_INTERFACE_MODE_SGMII:
308 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
310 case PHY_INTERFACE_MODE_NONE:
311 fm_info_set_phy_address(i, 0);
314 printf("Fman1: DTSEC%u set to unknown interface %i\n",
315 idx + 1, fm_info_get_enet_if(i));
316 fm_info_set_phy_address(i, 0);
321 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
322 int idx = i - FM1_10GEC1;
324 switch (fm_info_get_enet_if(i)) {
325 case PHY_INTERFACE_MODE_XGMII:
327 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
330 printf("Fman1: 10GSEC%u set to unknown interface %i\n",
331 idx + 1, fm_info_get_enet_if(i));
332 fm_info_set_phy_address(i, 0);
341 return pci_eth_init(bis);
344 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
345 enum fm_port port, int offset)
350 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
351 phy = fm_info_get_phy_address(port);
353 sprintf(alias, "phy_sgmii_%x", phy);
354 fdt_set_phy_handle(fdt, compat, addr, alias);
358 void fdt_fixup_board_enet(void *fdt)
363 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
364 switch (fm_info_get_enet_if(i)) {
365 case PHY_INTERFACE_MODE_NONE:
366 sprintf(alias, "ethernet%u", i);
367 fdt_status_disabled_by_alias(fdt, alias);