3 - BSC9131 is integrated device that targets Femto base station market.
4 It combines Power Architecture e500v2 and DSP StarCore SC3850 core
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
8 The BSC9131 SoC includes the following function and features:
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
12 . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
15 Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
17 . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
18 Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
21 ECC, up to 400-MHz clock/800 MHz data rate
22 . Dedicated security engine featuring trusted boot
24 . OCNDMA with four bidirectional channels
26 . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
27 including IEEE 1588. v2 hardware support and virtualization (eTSEC)
28 . eTSEC 1 supports RGMII/RMII
29 . eTSEC 2 supports RGMII
30 . High-speed USB 2.0 host and device controller with ULPI interface
31 . Enhanced secure digital (SD/MMC) host controller (eSDHC)
32 . Antenna interface controller (AIC), supporting three industry standard
33 JESD207/three custom ADI RF interfaces (two dual port and one single port)
34 and three MAXIM's MaxPHY serial interfaces
35 . ADI lanes support both full duplex FDD support and half duplex TDD support
36 . Universal Subscriber Identity Module (USIM) interface that facilitates
37 communication to SIM cards or Eurochip pre-paid phone cards
38 . TDM with one TDM port
39 . Two DUART, four eSPI, and two I2C controllers
40 . Integrated Flash memory controller (IFC)
41 . TDM with 256 channels
43 . Sixteen 32-bit timers
45 The e500 core subsystem within the Power Architecture consists of the following:
46 . 32-Kbyte L1 instruction cache
47 . 32-Kbyte L1 data cache
48 . 256-Kbyte L2 cache/L2 memory/L2 stash
49 . programmable interrupt controller (PIC)
53 The SC3850 core subsystem consists of the following:
54 . 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
55 . 32 Kbyte 8-way level 1 data cache (L1 DCache)
56 . 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
57 . Memory management unit (MMU)
58 . Enhanced programmable interrupt controller (EPIC)
59 . Debug and profiling unit (DPU)
62 BSC9131RDB board Overview
63 -------------------------
64 1Gbyte DDR3 (on board DDR)
65 128Mbyte 2K page size NAND Flash
66 256 Kbit M24256 I2C EEPROM
67 128 Mbit SPI Flash memory
69 eTSEC1: Connected to RGMII PHY
70 eTSEC2: Connected to RGMII PHY
71 DUART interface: supports one UARTs up to 115200 bps for console display
74 Frequency Combinations Supported
75 --------------------------------
76 Core MHz/CCB MHz/DDR(MT/s)
80 Boot Methods Supported
81 -----------------------
91 To build the u-boot for BSC9131RDB:
95 make BSC9131RDB_SPIFLASH
99 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
100 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
101 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
102 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
103 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
104 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
105 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
106 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
107 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
108 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
112 To place a new u-boot image in the NAND flash and then boot
113 with that new image temporarily, use this:
114 tftp 1000000 u-boot-nand.bin
116 nand write 1000000 0 100000
119 Using the Device Tree Source File
120 ---------------------------------
121 To create the DTB (Device Tree Binary) image file,
122 use a command similar to this:
124 dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
126 Likely, that .dts file will come from here;
128 linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
132 Place a linux uImage in the TFTP disk area.
135 tftp 2000000 rootfs.ext2.gz.uboot
136 tftp c00000 bsc9131rdb.dtb
137 bootm 1000000 2000000 c00000