2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <linux/compiler.h>
27 #include <asm/fsl_law.h>
28 #include <asm/fsl_ddr_sdram.h>
29 #include <asm/global_data.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 static void sdram_init(void)
35 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
36 #if CONFIG_DDR_CLK_FREQ == 100000000
37 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
38 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
39 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
40 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
41 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
43 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
44 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
45 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
46 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
47 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
48 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
49 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
50 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
51 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
53 __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
54 __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
55 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
56 #elif CONFIG_DDR_CLK_FREQ == 133000000
57 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
58 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
59 __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
60 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
61 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
63 __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
64 __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
65 __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
66 __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
67 __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
68 __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
69 __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
70 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
71 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
73 __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
74 __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
75 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
77 puts("Not a valid DDR Freq Found! Please Reset\n");
79 asm volatile("sync;isync");
82 /* Let the controller go */
83 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
85 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
88 void board_init_f(ulong bootflag)
91 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
93 /* initialize selected port with appropriate baud rate */
94 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
96 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
98 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
99 gd->bus_clk / 16 / CONFIG_BAUDRATE);
101 puts("\nNAND boot... ");
103 /* Initialize the DDR3 */
106 /* copy code to RAM and jump to it - this should not return */
107 /* NOTE - code has to be copied out of NAND buffer before
108 * other blocks can be read.
110 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
113 void board_init_r(gd_t *gd, ulong dest_addr)
121 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
123 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
126 void puts(const char *str)