git.sur5r.net Git - u-boot/blob - board/freescale/c29xpcie/tlb.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <asm/mmu.h>
  12
  13 struct fsl_e_tlb_entry tlb_table[] = {
  14         /* TLB 0 - for temp stack in cache */
  15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  16                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17                         0, 0, BOOKE_PAGESZ_4K, 0),
  18         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
  19                         CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  20                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  21                         0, 0, BOOKE_PAGESZ_4K, 0),
  22         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
  23                         CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25                         0, 0, BOOKE_PAGESZ_4K, 0),
  26         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
  27                         CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  28                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  29                         0, 0, BOOKE_PAGESZ_4K, 0),
  30
  31         /* TLB 1 */
  32         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  33                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  34                         0, 0, BOOKE_PAGESZ_1M, 1),
  35
  36         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  37                         MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  38                         0, 1, BOOKE_PAGESZ_64M, 1),
  39
  40 #ifdef CONFIG_PCI
  41         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  42                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  43                         0, 2, BOOKE_PAGESZ_256M, 1),
  44
  45         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  46                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  47                         0, 3, BOOKE_PAGESZ_256K, 1),
  48 #endif
  49
  50         SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
  51                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  52                         0, 4, BOOKE_PAGESZ_4K, 1),
  53
  54         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  55                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56                         0, 5, BOOKE_PAGESZ_16K, 1),
  57
  58         SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
  59                         CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
  60                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  61                         0, 6, BOOKE_PAGESZ_256K, 1),
  62         SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
  63                         CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
  64                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  65                         0, 7, BOOKE_PAGESZ_256K, 1),
  66
  67 #ifdef CONFIG_SYS_RAMBOOT
  68         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
  69                         CONFIG_SYS_DDR_SDRAM_BASE,
  70                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  71                         0, 8, BOOKE_PAGESZ_256M, 1),
  72         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
  73                         CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
  74                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  75                         0, 9, BOOKE_PAGESZ_256M, 1),
  76 #endif
  77 };
  78
  79 int num_tlb_entries = ARRAY_SIZE(tlb_table);