2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * Author: Shaveta Leekha <shaveta@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #include "idt8t49n222a_serdes_clk.h"
23 #define DEVICE_ID_REG 0x00
25 static int check_pll_status(u8 idt_addr)
30 ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
32 printf("IDT:0x%x could not read status register from device.\n",
38 debug("idt8t49n222a PLL is LOCKED: %x\n", val);
40 printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
47 int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
48 enum serdes_refclk refclk1,
49 enum serdes_refclk refclk2, u8 feedback)
54 debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
57 ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
59 debug("IDT:0x%x could not read DEV_ID from device.\n",
64 if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
65 debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
69 if (serdes_num != 1 && serdes_num != 2) {
70 debug("serdes_num should be 1 for SerDes1 and"
75 if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
76 || (refclk1 != SERDES_REFCLK_122_88
77 && refclk2 == SERDES_REFCLK_122_88)) {
78 debug("Only one refclk at 122.88MHz is not supported."
79 " Please set both refclk1 & refclk2 to 122.88MHz"
80 " or both not to 122.88MHz.\n");
84 if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
85 && refclk1 != SERDES_REFCLK_125
86 && refclk1 != SERDES_REFCLK_156_25) {
87 debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
92 if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
93 && refclk2 != SERDES_REFCLK_125
94 && refclk2 != SERDES_REFCLK_156_25) {
95 debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
100 if (feedback != 0 && feedback != 1) {
101 debug("valid values for feedback are 0(default) or 1.\n");
105 /* Configuring IDT for output refclks as
106 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
108 if (refclk1 == SERDES_REFCLK_122_88 &&
109 refclk2 == SERDES_REFCLK_122_88) {
110 printf("Setting refclk1:122.88 and refclk2:122.88\n");
111 for (i = 0; i < NUM_IDT_REGS; i++)
112 i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
113 idt_conf_122_88[i][1]);
116 for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
117 i2c_reg_write(idt_addr,
118 idt_conf_122_88_feedback[i][0],
119 idt_conf_122_88_feedback[i][1]);
123 if (refclk1 != SERDES_REFCLK_122_88 &&
124 refclk2 != SERDES_REFCLK_122_88) {
125 for (i = 0; i < NUM_IDT_REGS; i++)
126 i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
127 idt_conf_not_122_88[i][1]);
130 /* Configuring IDT for output refclks as
131 * Refclk1 = 100MHz Refclk2 = 125MHz
133 if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
134 printf("Setting refclk1:100 and refclk2:125\n");
135 i2c_reg_write(idt_addr, 0x11, 0x10);
138 /* Configuring IDT for output refclks as
139 * Refclk1 = 125MHz Refclk2 = 125MHz
141 if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
142 printf("Setting refclk1:125 and refclk2:125\n");
143 i2c_reg_write(idt_addr, 0x10, 0x10);
144 i2c_reg_write(idt_addr, 0x11, 0x10);
147 /* Configuring IDT for output refclks as
148 * Refclk1 = 125MHz Refclk2 = 100MHz
150 if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
151 printf("Setting refclk1:125 and refclk2:100\n");
152 i2c_reg_write(idt_addr, 0x10, 0x10);
155 /* Configuring IDT for output refclks as
156 * Refclk1 = 156.25MHz Refclk2 = 156.25MHz
158 if (refclk1 == SERDES_REFCLK_156_25 &&
159 refclk2 == SERDES_REFCLK_156_25) {
160 printf("Setting refclk1:156.25 and refclk2:156.25\n");
161 for (i = 0; i < NUM_IDT_REGS_156_25; i++)
162 i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
163 idt_conf_156_25[i][1]);
166 /* Configuring IDT for output refclks as
167 * Refclk1 = 100MHz Refclk2 = 156.25MHz
169 if (refclk1 == SERDES_REFCLK_100 &&
170 refclk2 == SERDES_REFCLK_156_25) {
171 printf("Setting refclk1:100 and refclk2:156.25\n");
172 for (i = 0; i < NUM_IDT_REGS_156_25; i++)
173 i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
174 idt_conf_100_156_25[i][1]);
177 /* Configuring IDT for output refclks as
178 * Refclk1 = 125MHz Refclk2 = 156.25MHz
180 if (refclk1 == SERDES_REFCLK_125 &&
181 refclk2 == SERDES_REFCLK_156_25) {
182 printf("Setting refclk1:125 and refclk2:156.25\n");
183 for (i = 0; i < NUM_IDT_REGS_156_25; i++)
184 i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
185 idt_conf_125_156_25[i][1]);
188 /* Configuring IDT for output refclks as
189 * Refclk1 = 156.25MHz Refclk2 = 100MHz
191 if (refclk1 == SERDES_REFCLK_156_25 &&
192 refclk2 == SERDES_REFCLK_100) {
193 printf("Setting refclk1:156.25 and refclk2:100\n");
194 for (i = 0; i < NUM_IDT_REGS_156_25; i++)
195 i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
196 idt_conf_156_25_100[i][1]);
199 /* Configuring IDT for output refclks as
200 * Refclk1 = 156.25MHz Refclk2 = 125MHz
202 if (refclk1 == SERDES_REFCLK_156_25 &&
203 refclk2 == SERDES_REFCLK_125) {
204 printf("Setting refclk1:156.25 and refclk2:125\n");
205 for (i = 0; i < NUM_IDT_REGS_156_25; i++)
206 i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
207 idt_conf_156_25_125[i][1]);
210 /* waiting for maximum of 1 second if PLL doesn'r get locked
211 * initially. then check the status again.
213 if (check_pll_status(idt_addr)) {
215 if (check_pll_status(idt_addr))